OV - exec - Loop 102

	Loop Id: 102	Module: exec	Source: advec_mom_kernel.f90:184-184	Coverage: 4.60%

0x421029 VMOVUPD	(%RBX,%RAX,1),%ZMM3    [5]

0x421030 VMOVUPD	(%R9,%RAX,1),%ZMM10    [2]

0x421037 VFMSUB132PD	(%RDI,%RAX,1),%ZMM10,%ZMM3    [4]

0x42103e VADDPD	(%R13,%RAX,1),%ZMM3,%ZMM12    [3]

0x421046 VDIVPD	(%R11,%RAX,1),%ZMM12,%ZMM14    [1]

0x42104d VMOVUPD	%ZMM14,(%RDI,%RAX,1)    [4]

0x421054 VMOVUPD	0x40(%RBX,%RAX,1),%ZMM9    [5]

0x42105c VMOVUPD	0x40(%R9,%RAX,1),%ZMM13    [2]

0x421064 VFMSUB132PD	0x40(%RDI,%RAX,1),%ZMM13,%ZMM9    [4]

0x42106c VADDPD	0x40(%R13,%RAX,1),%ZMM9,%ZMM1    [3]

0x421074 VDIVPD	0x40(%R11,%RAX,1),%ZMM1,%ZMM11    [1]

0x42107c VMOVUPD	%ZMM11,0x40(%RDI,%RAX,1)    [4]

0x421084 VMOVUPD	0x80(%RBX,%RAX,1),%ZMM0    [5]

0x42108c VMOVUPD	0x80(%R9,%RAX,1),%ZMM6    [2]

0x421094 VFMSUB132PD	0x80(%RDI,%RAX,1),%ZMM6,%ZMM0    [4]

0x42109c VADDPD	0x80(%R13,%RAX,1),%ZMM0,%ZMM7    [3]

0x4210a4 VDIVPD	0x80(%R11,%RAX,1),%ZMM7,%ZMM5    [1]

0x4210ac VMOVUPD	%ZMM5,0x80(%RDI,%RAX,1)    [4]

0x4210b4 VMOVUPD	0xc0(%RBX,%RAX,1),%ZMM15    [5]

0x4210bc VMOVUPD	0xc0(%R9,%RAX,1),%ZMM2    [2]

0x4210c4 VFMSUB132PD	0xc0(%RDI,%RAX,1),%ZMM2,%ZMM15    [4]

0x4210cc VADDPD	0xc0(%R13,%RAX,1),%ZMM15,%ZMM8    [3]

0x4210d4 VDIVPD	0xc0(%R11,%RAX,1),%ZMM8,%ZMM4    [1]

0x4210dc VMOVUPD	%ZMM4,0xc0(%RDI,%RAX,1)    [4]

0x4210e4 ADD	$0x100,%RAX

0x4210ea CMP	%RAX,%R10

0x4210ed JNE	421029

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90: 184 - 184

--------------------------------------------------------------------------------

184:           vel1 (j,k)=(vel1 (j,k)*node_mass_pre(j,k)+mom_flux(j-1,k)-mom_flux(j,k))/node_mass_post(j,k)

Coverage (%)	Name	Source Location	Module
○97.63	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.37	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	6.40
Bottlenecks	P0,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:184-184
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	64.00
CQA cycles if no scalar integer	64.00
CQA cycles if FP arith vectorized	64.00
CQA cycles if fully vectorized	64.00
Front-end cycles	7.67
P0 cycles	10.00
P1 cycles	4.00
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	2.00
P5 cycles	10.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.40
P11 cycles	6.67
DIV/SQRT cycles	64.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	38.00
Nb loads	20.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	32.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	1280.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	6.40
Bottlenecks	P0,
Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source	advec_mom_kernel.f90:184-184
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	64.00
CQA cycles if no scalar integer	64.00
CQA cycles if FP arith vectorized	64.00
CQA cycles if fully vectorized	64.00
Front-end cycles	7.67
P0 cycles	10.00
P1 cycles	4.00
P2 cycles	6.67
P3 cycles	6.67
P4 cycles	2.00
P5 cycles	10.00
P6 cycles	1.00
P7 cycles	2.00
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	0.40
P11 cycles	6.67
DIV/SQRT cycles	64.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	27.00
Nb uops	38.00
Nb loads	20.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	2.00
Nb FLOP add-sub	32.00
Nb FLOP mul	0.00
Nb FLOP fma	32.00
Nb FLOP div	32.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	24.00
Bytes prefetched	0.00
Bytes loaded	1280.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:184-184
Module	exec

The loop is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:184.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 64.00 to 10.00 cycles (6.40x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 64.00 to 6.00 cycles (10.67x speedup).

FMA

Detected 32 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:184
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:184
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:184
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:184

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (32 inside FMA instructions)
32: multiply (all inside FMA instructions)
32: divide

The binary loop is loading 1280 bytes (160 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	38
loop length	202
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	0.60	6.67	6.67	2.00	10.00	1.00	2.00	2.00	2.00	0.40	6.67
cycles	10.00	4.00	6.67	6.67	2.00	10.00	1.00	2.00	2.00	2.00	0.40	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	64.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.67
Dispatch	10.00
DIV/SQRT	64.00
Data deps.	1.00
Overall L1	64.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 64.00 cycles. At this rate:

10% of peak load performance is reached (20.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 421029

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RBX,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R9,%RAX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMSUB132PD (%RDI,%RAX,1),%ZMM10,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD (%R13,%RAX,1),%ZMM3,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD (%R11,%RAX,1),%ZMM12,%ZMM14	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VMOVUPD %ZMM14,(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%RBX,%RAX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%R9,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMSUB132PD 0x40(%RDI,%RAX,1),%ZMM13,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD 0x40(%R11,%RAX,1),%ZMM1,%ZMM11	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VMOVUPD %ZMM11,0x40(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%RBX,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x80(%R9,%RAX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMSUB132PD 0x80(%RDI,%RAX,1),%ZMM6,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD 0x80(%R11,%RAX,1),%ZMM7,%ZMM5	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VMOVUPD %ZMM5,0x80(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0xc0(%R9,%RAX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMSUB132PD 0xc0(%RDI,%RAX,1),%ZMM2,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD 0xc0(%R13,%RAX,1),%ZMM15,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD 0xc0(%R11,%RAX,1),%ZMM8,%ZMM4	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VMOVUPD %ZMM4,0xc0(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x100,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 421029 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1629>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Function	__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0
Source file and lines	advec_mom_kernel.f90:184-184
Module	exec

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 64.00 to 6.00 cycles (10.67x speedup).

FMA

Detected 32 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VDIVPD: 4 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:184
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:184
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:184
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/advec_mom_kernel.f90:184

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 128 FP arithmetical operations:

64: addition or subtraction (32 inside FMA instructions)
32: multiply (all inside FMA instructions)
32: divide

The binary loop is loading 1280 bytes (160 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.

General properties

nb instructions	27
nb uops	38
loop length	202
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	16
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	7.67 cycles
front end	7.67 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.00	0.60	6.67	6.67	2.00	10.00	1.00	2.00	2.00	2.00	0.40	6.67
cycles	10.00	4.00	6.67	6.67	2.00	10.00	1.00	2.00	2.00	2.00	0.40	6.67

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions	64.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	7.67
Dispatch	10.00
DIV/SQRT	64.00
Data deps.	1.00
Overall L1	64.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	100%
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 64.00 cycles. At this rate:

10% of peak load performance is reached (20.00 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (4.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 421029

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
VMOVUPD (%RBX,%RAX,1),%ZMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD (%R9,%RAX,1),%ZMM10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMSUB132PD (%RDI,%RAX,1),%ZMM10,%ZMM3	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD (%R13,%RAX,1),%ZMM3,%ZMM12	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD (%R11,%RAX,1),%ZMM12,%ZMM14	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VMOVUPD %ZMM14,(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x40(%RBX,%RAX,1),%ZMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x40(%R9,%RAX,1),%ZMM13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMSUB132PD 0x40(%RDI,%RAX,1),%ZMM13,%ZMM9	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD 0x40(%R13,%RAX,1),%ZMM9,%ZMM1	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD 0x40(%R11,%RAX,1),%ZMM1,%ZMM11	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VMOVUPD %ZMM11,0x40(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0x80(%RBX,%RAX,1),%ZMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0x80(%R9,%RAX,1),%ZMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMSUB132PD 0x80(%RDI,%RAX,1),%ZMM6,%ZMM0	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD 0x80(%R13,%RAX,1),%ZMM0,%ZMM7	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD 0x80(%R11,%RAX,1),%ZMM7,%ZMM5	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VMOVUPD %ZMM5,0x80(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
VMOVUPD 0xc0(%RBX,%RAX,1),%ZMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VMOVUPD 0xc0(%R9,%RAX,1),%ZMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	0-1	0.50	vect (100.0%)
VFMSUB132PD 0xc0(%RDI,%RAX,1),%ZMM2,%ZMM15	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	4	0.50	vect (100.0%)
VADDPD 0xc0(%R13,%RAX,1),%ZMM15,%ZMM8	1	0.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.65	vect (100.0%)
VDIVPD 0xc0(%R11,%RAX,1),%ZMM8,%ZMM4	4	2.50	0	0.33	0.33	0	0.50	0	0	0	0	0	0.33	22-24	16	vect (100.0%)
VMOVUPD %ZMM4,0xc0(%RDI,%RAX,1)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0-1	1	vect (100.0%)
ADD $0x100,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %RAX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
JNE 421029 <__advec_mom_kernel_mod_MOD_advec_mom_kernel._omp_fn.0+0x1629>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

FMA

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code