OV - exec - Function __pack_kernel_module_MOD_clover_unpack_message_top._omp

	Function: __pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0	Module: exec	Source: pack_kernel.f90:296-300	Coverage (incl. loops): 0.01% \| (excl. loops): 0.01%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 296 - 300

--------------------------------------------------------------------------------

296:       !$OMP PARALLEL DO PRIVATE(index)

297:       DO j=x_min-depth,x_max+x_inc+depth

298:         index= buffer_offset + k+(j+depth-1)*depth

299:         !index= buffer_offset + j + depth+(k-1)*(x_max+x_inc+(2*depth))

300:         field(j,y_max+y_inc+k)=top_rcv_buffer(index)

0x435930 PUSH	%RBP

0x435931 MOV	%RSP,%RBP

0x435934 PUSH	%R13

0x435936 PUSH	%R12

0x435938 PUSH	%RBX

0x435939 MOV	%RDI,%RBX

0x43593c SUB	$0x8,%RSP

0x435940 MOV	0x58(%RDI),%R13D

0x435944 CALL	402370 <@plt_start@+0x350>

0x435949 MOV	%EAX,%R12D

0x43594c CALL	4022e0 <@plt_start@+0x2c0>

0x435951 MOV	%EAX,%ECX

0x435953 MOV	0x5c(%RBX),%EAX

0x435956 INC	%EAX

0x435958 SUB	%R13D,%EAX

0x43595b CLTD

0x43595c IDIV	%R12D

0x43595f CMP	%EDX,%ECX

0x435961 JL	435b88

0x435967 IMUL	%EAX,%ECX

0x43596a ADD	%ECX,%EDX

0x43596c ADD	%EDX,%EAX

0x43596e CMP	%EAX,%EDX

0x435970 JGE	435b76

0x435976 MOV	0x8(%RBX),%RSI

0x43597a ADD	%R13D,%EDX

0x43597d LEA	(%R13,%RAX,1),%R9D

0x435982 MOVSXD	(%RSI),%R13

0x435985 MOV	0x10(%RBX),%R12

0x435989 MOV	%R13,%R11

0x43598c LEA	-0x1(%RDX,%R11,1),%ESI

0x435991 MOV	0x50(%RBX),%R10D

0x435995 MOV	(%R12),%ECX

0x435999 IMUL	%R11D,%ESI

0x43599d ADD	%R10D,%ECX

0x4359a0 MOV	0x40(%RBX),%RDI

0x4359a4 MOVSXD	%ESI,%R11

0x4359a7 MOVSXD	%ECX,%RAX

0x4359aa ADD	%R11,%RAX

0x4359ad IMUL	%RDI,%RAX

0x4359b1 IMUL	%RDI,%R13

0x4359b5 MOV	0x38(%RBX),%RDI

0x4359b9 ADD	0x48(%RBX),%RAX

0x4359bd LEA	(%RDI,%RAX,8),%R12

0x4359c1 MOV	(%RBX),%RSI

0x4359c4 MOV	0x54(%RBX),%EAX

0x4359c7 MOV	0x20(%RBX),%R8

0x4359cb ADD	(%RSI),%EAX

0x4359cd ADD	%R10D,%EAX

0x4359d0 CLTQ

0x4359d2 IMUL	0x28(%RBX),%RAX

0x4359d7 MOVSXD	%EDX,%R10

0x4359da LEA	(,%R8,8),%RCX

0x4359e2 IMUL	%R10,%R8

0x4359e6 ADD	0x30(%RBX),%RAX

0x4359ea MOV	%EDX,%EDI

0x4359ec MOV	0x18(%RBX),%RBX

0x4359f0 VMOVSD	(%R12),%XMM0

0x4359f6 ADD	%R8,%RAX

0x4359f9 NOT	%EDI

0x4359fb LEA	(%RBX,%RAX,8),%R11

0x4359ff SAL	$0x3,%R13

0x435a03 ADD	%R9D,%EDI

0x435a06 LEA	0x1(%RDX),%R8D

0x435a0a VMOVSD	%XMM0,(%R11)

0x435a0f AND	$0x7,%EDI

0x435a12 ADD	%R13,%R12

0x435a15 ADD	%RCX,%R11

0x435a18 CMP	%R8D,%R9D

0x435a1b JLE	435b76

0x435a21 TEST	%EDI,%EDI

0x435a23 JE	435ae1

0x435a29 CMP	$0x1,%EDI

0x435a2c JE	435ac4

0x435a32 CMP	$0x2,%EDI

0x435a35 JE	435ab0

0x435a37 CMP	$0x3,%EDI

0x435a3a JE	435a9c

0x435a3c CMP	$0x4,%EDI

0x435a3f JE	435a88

0x435a41 CMP	$0x5,%EDI

0x435a44 JE	435a74

0x435a46 CMP	$0x6,%EDI

0x435a49 JE	435a60

0x435a4b VMOVSD	(%R12),%XMM1

0x435a51 LEA	0x2(%RDX),%R8D

0x435a55 VMOVSD	%XMM1,(%R11)

0x435a5a ADD	%R13,%R12

0x435a5d ADD	%RCX,%R11

0x435a60 VMOVSD	(%R12),%XMM2

0x435a66 INC	%R8D

0x435a69 VMOVSD	%XMM2,(%R11)

0x435a6e ADD	%R13,%R12

0x435a71 ADD	%RCX,%R11

0x435a74 VMOVSD	(%R12),%XMM3

0x435a7a INC	%R8D

0x435a7d VMOVSD	%XMM3,(%R11)

0x435a82 ADD	%R13,%R12

0x435a85 ADD	%RCX,%R11

0x435a88 VMOVSD	(%R12),%XMM4

0x435a8e INC	%R8D

0x435a91 VMOVSD	%XMM4,(%R11)

0x435a96 ADD	%R13,%R12

0x435a99 ADD	%RCX,%R11

0x435a9c VMOVSD	(%R12),%XMM5

0x435aa2 INC	%R8D

0x435aa5 VMOVSD	%XMM5,(%R11)

0x435aaa ADD	%R13,%R12

0x435aad ADD	%RCX,%R11

0x435ab0 VMOVSD	(%R12),%XMM6

0x435ab6 INC	%R8D

0x435ab9 VMOVSD	%XMM6,(%R11)

0x435abe ADD	%R13,%R12

0x435ac1 ADD	%RCX,%R11

0x435ac4 VMOVSD	(%R12),%XMM7

0x435aca INC	%R8D

0x435acd VMOVSD	%XMM7,(%R11)

0x435ad2 ADD	%R13,%R12

0x435ad5 ADD	%RCX,%R11

0x435ad8 CMP	%R8D,%R9D

0x435adb JLE	435b76

(247) 0x435ae1 VMOVSD	(%R12),%XMM8

(247) 0x435ae7 ADD	%R13,%R12

(247) 0x435aea VMOVSD	%XMM8,(%R11)

(247) 0x435aef VMOVSD	(%R12),%XMM9

(247) 0x435af5 ADD	%RCX,%R11

(247) 0x435af8 VMOVSD	%XMM9,(%R11)

(247) 0x435afd ADD	%R13,%R12

(247) 0x435b00 VMOVSD	(%R12),%XMM10

(247) 0x435b06 ADD	%RCX,%R11

(247) 0x435b09 VMOVSD	%XMM10,(%R11)

(247) 0x435b0e ADD	%R13,%R12

(247) 0x435b11 VMOVSD	(%R12),%XMM11

(247) 0x435b17 ADD	%RCX,%R11

(247) 0x435b1a VMOVSD	%XMM11,(%R11)

(247) 0x435b1f ADD	%R13,%R12

(247) 0x435b22 VMOVSD	(%R12),%XMM12

(247) 0x435b28 ADD	%RCX,%R11

(247) 0x435b2b VMOVSD	%XMM12,(%R11)

(247) 0x435b30 ADD	%R13,%R12

(247) 0x435b33 VMOVSD	(%R12),%XMM13

(247) 0x435b39 ADD	%RCX,%R11

(247) 0x435b3c VMOVSD	%XMM13,(%R11)

(247) 0x435b41 ADD	%R13,%R12

(247) 0x435b44 VMOVSD	(%R12),%XMM14

(247) 0x435b4a ADD	%RCX,%R11

(247) 0x435b4d VMOVSD	%XMM14,(%R11)

(247) 0x435b52 ADD	%R13,%R12

(247) 0x435b55 VMOVSD	(%R12),%XMM15

(247) 0x435b5b ADD	%RCX,%R11

(247) 0x435b5e ADD	$0x8,%R8D

(247) 0x435b62 VMOVSD	%XMM15,(%R11)

(247) 0x435b67 ADD	%R13,%R12

(247) 0x435b6a ADD	%RCX,%R11

(247) 0x435b6d CMP	%R8D,%R9D

(247) 0x435b70 JG	435ae1

0x435b76 ADD	$0x8,%RSP

0x435b7a POP	%RBX

0x435b7b POP	%R12

0x435b7d POP	%R13

0x435b7f POP	%RBP

0x435b80 RET

0x435b81 NOPL	(%RAX)

0x435b88 INC	%EAX

0x435b8a XOR	%EDX,%EDX

0x435b8c JMP	435967

0x435b91 NOPW	%CS:(%RAX,%RAX,1)

0x435b9c NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○100.00	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_7

Source file and lines	pack_kernel.f90:296-300
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:296-300.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.00 to 6.50 cycles (3.54x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 23.00 to 1.64 cycles (14.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:296
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:296

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:296

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:296
CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:300

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	133
nb uops	138
loop length	475
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.00 cycles
front end	23.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.00	16.00	10.00	10.00	7.00	16.00	16.00	7.00	7.00	7.00	16.00	10.00
cycles	16.00	21.90	10.00	10.00	7.00	16.00	16.00	7.00	7.00	7.00	16.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	23.00
Dispatch	21.90
DIV/SQRT	6.00
Overall L1	23.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	11%
store	12%
mul	6%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.00 cycles. At this rate:

3% of peak load performance is reached (7.48 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.78 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 23.00 to 21.90 cycles (1.05x speedup).

ASM code

In the binary file, the address of the function is: 435930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x58(%RDI),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x5c(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 435b88 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x258>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 435b76 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x246>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R13,%RAX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD (%RSI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RDX,%R11,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x50(%RBX),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R12),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
IMUL %R11D,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R10D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x40(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %ESI,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %ECX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R11,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RDI,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x38(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x48(%RBX),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
LEA (%RDI,%RAX,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x54(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD (%RSI),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %R10D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
IMUL 0x28(%RBX),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOVSXD %EDX,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
LEA (,%R8,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD 0x30(%RBX),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R12),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOT %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RBX,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R9D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RDX),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSD %XMM0,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 435b76 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x246>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %EDI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 435ae1 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x1b1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435ac4 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x194>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435ab0 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x180>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435a9c <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x16c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435a88 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x158>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435a74 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x144>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435a60 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x130>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R12),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x2(%RDX),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSD %XMM1,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM2,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM3,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM4,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM5,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM6,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM7,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 435b76 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x246>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 435967 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x37>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_7

Source file and lines	pack_kernel.f90:296-300
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 23.00 to 6.50 cycles (3.54x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:296
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:296

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:296

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:296
CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:300

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 172 bytes. The binary function is storing 64 bytes.

General properties

nb instructions	133
nb uops	138
loop length	475
used x86 registers	14
used mmx registers	0
used xmm registers	8
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	23.00 cycles
front end	23.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	16.00	16.00	10.00	10.00	7.00	16.00	16.00	7.00	7.00	7.00	16.00	10.00
cycles	16.00	21.90	10.00	10.00	7.00	16.00	16.00	7.00	7.00	7.00	16.00	10.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	23.00
Dispatch	21.90
DIV/SQRT	6.00
Overall L1	23.00

Vectorization ratios

INT

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	7%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	11%
store	12%
mul	6%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 23.00 cycles. At this rate:

3% of peak load performance is reached (7.48 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (2.78 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 435930

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x58(%RDI),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x5c(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 435b88 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x258>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 435b76 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x246>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R13,%RAX,1),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOVSXD (%RSI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x10(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RDX,%R11,1),%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x50(%RBX),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV (%R12),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
IMUL %R11D,%ESI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R10D,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV 0x40(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %ESI,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOVSXD %ECX,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
ADD %R11,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %RDI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RDI,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x38(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x48(%RBX),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
LEA (%RDI,%RAX,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x54(%RBX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD (%RSI),%EAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %R10D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTQ	1	0	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.33	scal (12.5%)
IMUL 0x28(%RBX),%RAX	1	0	1	0.33	0.33	0	0	0	0	0	0	0	0.33	3	1	N/A
MOVSXD %EDX,%R10	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
LEA (,%R8,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD 0x30(%RBX),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %EDX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD (%R12),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R8,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
NOT %EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RBX,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x3,%R13	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
ADD %R9D,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%RDX),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSD %XMM0,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
AND $0x7,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 435b76 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x246>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
TEST %EDI,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
JE 435ae1 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x1b1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x1,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435ac4 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x194>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x2,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435ab0 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x180>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x3,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435a9c <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x16c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x4,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435a88 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x158>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x5,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435a74 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x144>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
CMP $0x6,%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JE 435a60 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x130>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
VMOVSD (%R12),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA 0x2(%RDX),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
VMOVSD %XMM1,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM2,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM3	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM3,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM4,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM5,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM6,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD (%R12),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
INC %R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
VMOVSD %XMM7,(%R11)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R13,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %R8D,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JLE 435b76 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x246>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD $0x8,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 435967 <__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0+0x37>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼__pack_kernel_module_MOD_clover_unpack_message_top._omp_fn.0–	0.01	0.00
○Loop 247 - pack_kernel.f90:300-300 - exec	0.01	0.01

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