OV - exec - Function __pack_kernel_module_MOD_clover_unpack_message_bottom._omp

	Function: __pack_kernel_module_MOD_clover_unpack_message_bottom._omp_fn.0	Module: exec	Source: pack_kernel.f90:389-395	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90: 389 - 395

--------------------------------------------------------------------------------

389:     !$OMP PARALLEL

390:     DO k=1,depth

391:       !$OMP DO PRIVATE(index)

392:       DO j=x_min-depth,x_max+x_inc+depth

393:         index= buffer_offset + k+(j+depth-1)*depth

394:         !index= buffer_offset + j+depth+(k-1)*(x_max+x_inc+(2*depth))

395:         field(j,y_min-k)=bottom_rcv_buffer(index)

0x4353f0 PUSH	%RBP

0x4353f1 MOV	%RSP,%RBP

0x4353f4 PUSH	%R15

0x4353f6 PUSH	%R14

0x4353f8 PUSH	%R13

0x4353fa PUSH	%R12

0x4353fc PUSH	%RBX

0x4353fd SUB	$0x38,%RSP

0x435401 MOV	0x18(%RDI),%RSI

0x435405 MOV	0x58(%RDI),%RAX

0x435409 MOV	(%RSI),%R8D

0x43540c MOV	0x50(%RDI),%RDX

0x435410 MOV	0x48(%RDI),%R14

0x435414 MOV	0x38(%RDI),%RCX

0x435418 MOV	0x30(%RDI),%RBX

0x43541c TEST	%R8D,%R8D

0x43541f MOV	%RAX,-0x40(%RBP)

0x435423 MOV	%RDX,-0x48(%RBP)

0x435427 MOV	%R14,-0x50(%RBP)

0x43542b MOV	%RCX,-0x58(%RBP)

0x43542f MOV	%RBX,-0x60(%RBP)

0x435433 MOV	%R8D,-0x38(%RBP)

0x435437 MOV	0x60(%RDI),%R13D

0x43543b JLE	4356a0

0x435441 MOV	%RDI,%R15

0x435444 CALL	402370 <@plt_start@+0x350>

0x435449 MOV	%EAX,-0x34(%RBP)

0x43544c CALL	4022e0 <@plt_start@+0x2c0>

0x435451 MOV	-0x38(%RBP),%ECX

0x435454 SAL	$0x3,%R14

0x435458 LEA	0x1(%RCX),%EDI

0x43545b MOV	$0x1,%R9D

0x435461 MOV	%R14,%RBX

0x435464 MOV	%EDI,-0x38(%RBP)

0x435467 MOV	%EAX,%R12D

0x43546a MOV	%R9D,%R14D

0x43546d JMP	43548a

0x43546f NOP

(244) 0x435470 CALL	402360 <@plt_start@+0x340>

(244) 0x435475 MOV	-0x38(%RBP),%EAX

(244) 0x435478 INC	%R14D

(244) 0x43547b CMP	%EAX,%R14D

(244) 0x43547e JE	4356a0

(244) 0x435484 MOV	0x18(%R15),%RDX

(244) 0x435488 MOV	(%RDX),%ECX

(244) 0x43548a MOV	0x8(%R15),%R11

(244) 0x43548e MOV	(%R15),%R10

(244) 0x435491 MOV	(%R11),%EAX

(244) 0x435494 MOV	(%R10),%ESI

(244) 0x435497 ADD	%R13D,%EAX

(244) 0x43549a SUB	%ECX,%ESI

(244) 0x43549c LEA	0x1(%RCX,%RAX,1),%EAX

(244) 0x4354a0 SUB	%ESI,%EAX

(244) 0x4354a2 CLTD

(244) 0x4354a3 IDIVL	-0x34(%RBP)

(244) 0x4354a6 CMP	%EDX,%R12D

(244) 0x4354a9 JL	435690

(244) 0x4354af MOV	%EAX,%R8D

(244) 0x4354b2 IMUL	%R12D,%R8D

(244) 0x4354b6 ADD	%R8D,%EDX

(244) 0x4354b9 ADD	%EDX,%EAX

(244) 0x4354bb CMP	%EAX,%EDX

(244) 0x4354bd JGE	435470

(244) 0x4354bf ADD	%ESI,%EDX

(244) 0x4354c1 MOV	0x20(%R15),%R9

(244) 0x4354c5 LEA	-0x1(%RDX,%RCX,1),%R8D

(244) 0x4354ca MOV	(%R9),%R10D

(244) 0x4354cd MOVSXD	%ECX,%RDI

(244) 0x4354d0 IMUL	%R8D,%ECX

(244) 0x4354d4 ADD	%R14D,%R10D

(244) 0x4354d7 MOV	-0x60(%RBP),%R11

(244) 0x4354db ADD	%ESI,%EAX

(244) 0x4354dd MOVSXD	%ECX,%RCX

(244) 0x4354e0 MOVSXD	%R10D,%RSI

(244) 0x4354e3 ADD	%RSI,%RCX

(244) 0x4354e6 MOV	0x10(%R15),%R10

(244) 0x4354ea IMUL	%R11,%RCX

(244) 0x4354ee MOV	(%R10),%R8D

(244) 0x4354f1 IMUL	%R11,%RDI

(244) 0x4354f5 MOV	-0x58(%RBP),%R11

(244) 0x4354f9 MOV	0x28(%R15),%R9

(244) 0x4354fd ADD	%R11,%RCX

(244) 0x435500 SUB	%R14D,%R8D

(244) 0x435503 MOV	-0x48(%RBP),%R11

(244) 0x435507 LEA	(%R9,%RCX,8),%RSI

(244) 0x43550b MOVSXD	%R8D,%RCX

(244) 0x43550e MOV	-0x50(%RBP),%R8

(244) 0x435512 IMUL	%R11,%RCX

(244) 0x435516 MOVSXD	%EDX,%R10

(244) 0x435519 IMUL	%R8,%R10

(244) 0x43551d MOV	-0x40(%RBP),%R9

(244) 0x435521 MOV	0x40(%R15),%R11

(244) 0x435525 ADD	%R9,%RCX

(244) 0x435528 MOV	%EDX,%R9D

(244) 0x43552b VMOVSD	(%RSI),%XMM0

(244) 0x43552f ADD	%R10,%RCX

(244) 0x435532 NOT	%R9D

(244) 0x435535 LEA	(%R11,%RCX,8),%RCX

(244) 0x435539 SAL	$0x3,%RDI

(244) 0x43553d ADD	%EAX,%R9D

(244) 0x435540 LEA	0x1(%RDX),%R10D

(244) 0x435544 VMOVSD	%XMM0,(%RCX)

(244) 0x435548 AND	$0x7,%R9D

(244) 0x43554c ADD	%RDI,%RSI

(244) 0x43554f ADD	%RBX,%RCX

(244) 0x435552 CMP	%R10D,%EAX

(244) 0x435555 JLE	435470

(244) 0x43555b TEST	%R9D,%R9D

(244) 0x43555e JE	43560d

(244) 0x435564 CMP	$0x1,%R9D

(244) 0x435568 JE	4355f3

(244) 0x43556e CMP	$0x2,%R9D

(244) 0x435572 JE	4355e2

(244) 0x435574 CMP	$0x3,%R9D

(244) 0x435578 JE	4355d1

(244) 0x43557a CMP	$0x4,%R9D

(244) 0x43557e JE	4355c0

(244) 0x435580 CMP	$0x5,%R9D

(244) 0x435584 JE	4355af

(244) 0x435586 CMP	$0x6,%R9D

(244) 0x43558a JE	43559e

(244) 0x43558c VMOVSD	(%RSI),%XMM1

(244) 0x435590 LEA	0x2(%RDX),%R10D

(244) 0x435594 VMOVSD	%XMM1,(%RCX)

(244) 0x435598 ADD	%RDI,%RSI

(244) 0x43559b ADD	%RBX,%RCX

(244) 0x43559e VMOVSD	(%RSI),%XMM2

(244) 0x4355a2 INC	%R10D

(244) 0x4355a5 VMOVSD	%XMM2,(%RCX)

(244) 0x4355a9 ADD	%RDI,%RSI

(244) 0x4355ac ADD	%RBX,%RCX

(244) 0x4355af VMOVSD	(%RSI),%XMM3

(244) 0x4355b3 INC	%R10D

(244) 0x4355b6 VMOVSD	%XMM3,(%RCX)

(244) 0x4355ba ADD	%RDI,%RSI

(244) 0x4355bd ADD	%RBX,%RCX

(244) 0x4355c0 VMOVSD	(%RSI),%XMM4

(244) 0x4355c4 INC	%R10D

(244) 0x4355c7 VMOVSD	%XMM4,(%RCX)

(244) 0x4355cb ADD	%RDI,%RSI

(244) 0x4355ce ADD	%RBX,%RCX

(244) 0x4355d1 VMOVSD	(%RSI),%XMM5

(244) 0x4355d5 INC	%R10D

(244) 0x4355d8 VMOVSD	%XMM5,(%RCX)

(244) 0x4355dc ADD	%RDI,%RSI

(244) 0x4355df ADD	%RBX,%RCX

(244) 0x4355e2 VMOVSD	(%RSI),%XMM6

(244) 0x4355e6 INC	%R10D

(244) 0x4355e9 VMOVSD	%XMM6,(%RCX)

(244) 0x4355ed ADD	%RDI,%RSI

(244) 0x4355f0 ADD	%RBX,%RCX

(244) 0x4355f3 VMOVSD	(%RSI),%XMM7

(244) 0x4355f7 INC	%R10D

(244) 0x4355fa VMOVSD	%XMM7,(%RCX)

(244) 0x4355fe ADD	%RDI,%RSI

(244) 0x435601 ADD	%RBX,%RCX

(244) 0x435604 CMP	%R10D,%EAX

(244) 0x435607 JLE	435470

  (245) 0x43560d VMOVSD	(%RSI),%XMM8

  (245) 0x435611 ADD	%RDI,%RSI

  (245) 0x435614 VMOVSD	%XMM8,(%RCX)

  (245) 0x435618 VMOVSD	(%RSI),%XMM9

  (245) 0x43561c ADD	%RBX,%RCX

  (245) 0x43561f VMOVSD	%XMM9,(%RCX)

  (245) 0x435623 ADD	%RDI,%RSI

  (245) 0x435626 VMOVSD	(%RSI),%XMM10

  (245) 0x43562a ADD	%RBX,%RCX

  (245) 0x43562d VMOVSD	%XMM10,(%RCX)

  (245) 0x435631 ADD	%RDI,%RSI

  (245) 0x435634 VMOVSD	(%RSI),%XMM11

  (245) 0x435638 ADD	%RBX,%RCX

  (245) 0x43563b VMOVSD	%XMM11,(%RCX)

  (245) 0x43563f ADD	%RDI,%RSI

  (245) 0x435642 VMOVSD	(%RSI),%XMM12

  (245) 0x435646 ADD	%RBX,%RCX

  (245) 0x435649 VMOVSD	%XMM12,(%RCX)

  (245) 0x43564d ADD	%RDI,%RSI

  (245) 0x435650 VMOVSD	(%RSI),%XMM13

  (245) 0x435654 ADD	%RBX,%RCX

  (245) 0x435657 VMOVSD	%XMM13,(%RCX)

  (245) 0x43565b ADD	%RDI,%RSI

  (245) 0x43565e VMOVSD	(%RSI),%XMM14

  (245) 0x435662 ADD	%RBX,%RCX

  (245) 0x435665 VMOVSD	%XMM14,(%RCX)

  (245) 0x435669 ADD	%RDI,%RSI

  (245) 0x43566c VMOVSD	(%RSI),%XMM15

  (245) 0x435670 ADD	%RBX,%RCX

  (245) 0x435673 ADD	$0x8,%R10D

  (245) 0x435677 VMOVSD	%XMM15,(%RCX)

  (245) 0x43567b ADD	%RDI,%RSI

  (245) 0x43567e ADD	%RBX,%RCX

  (245) 0x435681 CMP	%R10D,%EAX

  (245) 0x435684 JG	43560d

(244) 0x435686 JMP	435470

0x43568b NOPL	(%RAX,%RAX,1)

(244) 0x435690 INC	%EAX

(244) 0x435692 XOR	%EDX,%EDX

(244) 0x435694 JMP	4354af

0x435699 NOPL	(%RAX)

0x4356a0 ADD	$0x38,%RSP

0x4356a4 POP	%RBX

0x4356a5 POP	%R12

0x4356a7 POP	%R13

0x4356a9 POP	%R14

0x4356ab POP	%R15

0x4356ad POP	%RBP

0x4356ae RET

0x4356af NOP

Coverage (%)	Name	Source Location	Module
○99.59	gomp_thread_start	team.c:130	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	pack_kernel.f90:389-395
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:389-395.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 8.50 to 0.66 cycles (12.95x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:390
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:390

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	49
nb uops	51
loop length	156
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.00	5.33	5.33	8.00	1.00	1.50	8.00	8.00	8.00	1.00	5.33
cycles	1.50	1.00	5.33	5.33	8.00	1.00	1.50	8.00	8.00	8.00	1.00	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	8.00
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

3% of peak load performance is reached (7.06 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 8.50 to 8.00 cycles (1.06x speedup).

ASM code

In the binary file, the address of the function is: 4353f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x50(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %R8D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8D,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x60(%RDI),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JLE 4356a0 <__pack_kernel_module_MOD_clover_unpack_message_bottom._omp_fn.0+0x2b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA 0x1(%RCX),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JMP 43548a <__pack_kernel_module_MOD_clover_unpack_message_bottom._omp_fn.0+0x9a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	pack_kernel.f90:389-395
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:390
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/pack_kernel.f90:390

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 52 bytes.

General properties

nb instructions	49
nb uops	51
loop length	156
used x86 registers	14
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.50 cycles
front end	8.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	1.50	1.00	5.33	5.33	8.00	1.00	1.50	8.00	8.00	8.00	1.00	5.33
cycles	1.50	1.00	5.33	5.33	8.00	1.00	1.50	8.00	8.00	8.00	1.00	5.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.50
Dispatch	8.00
Overall L1	8.50

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 8.50 cycles. At this rate:

3% of peak load performance is reached (7.06 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (6.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4353f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI),%R8D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x50(%RDI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%RDI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%RDI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RDI),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
TEST %R8D,%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	scal (6.3%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8D,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x60(%RDI),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
JLE 4356a0 <__pack_kernel_module_MOD_clover_unpack_message_bottom._omp_fn.0+0x2b0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,-0x34(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV -0x38(%RBP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SAL $0x3,%R14	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
LEA 0x1(%RCX),%EDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV $0x1,%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %R14,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %EDI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JMP 43548a <__pack_kernel_module_MOD_clover_unpack_message_bottom._omp_fn.0+0x9a>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5.84	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD $0x38,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼__pack_kernel_module_MOD_clover_unpack_message_bottom._omp_fn.0–	0.01	0.00
▼Loop 244 - pack_kernel.f90:390-395 - exec–	0.01	0.01
○Loop 245 - pack_kernel.f90:395-395 - exec	0.01	0.01

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code