OV - exec - Function __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp

	Function: __ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0	Module: exec	Source: ideal_gas_kernel.f90:45-55	Coverage (incl. loops): 4.95% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90: 45 - 55

--------------------------------------------------------------------------------

45:     !$OMP PARALLEL

46:     !$OMP DO PRIVATE(v,pressurebyenergy,pressurebyvolume,sound_speed_squared)

47:     DO k=y_min,y_max

48:     !$OMP SIMD

49:       DO j=x_min,x_max

50:         v=1.0_8/density(j,k)

51:         pressure(j,k)=(1.4_8-1.0_8)*density(j,k)*energy(j,k)

52:         pressurebyenergy=(1.4_8-1.0_8)*density(j,k)

53:         pressurebyvolume=-density(j,k)*pressure(j,k)

54:         sound_speed_squared=v*v*(pressure(j,k)*pressurebyenergy-pressurebyvolume)

55:         soundspeed(j,k)=SQRT(sound_speed_squared)

0x430850 PUSH	%RBP

0x430851 MOV	%RSP,%RBP

0x430854 PUSH	%R15

0x430856 PUSH	%R14

0x430858 PUSH	%R13

0x43085a PUSH	%R12

0x43085c MOV	%RDI,%R12

0x43085f PUSH	%RBX

0x430860 AND	$-0x40,%RSP

0x430864 ADD	$-0x80,%RSP

0x430868 MOV	0x10(%RDI),%RAX

0x43086c MOV	(%RAX),%R14D

0x43086f CALL	402370 <@plt_start@+0x350>

0x430874 MOV	%EAX,%R13D

0x430877 CALL	4022e0 <@plt_start@+0x2c0>

0x43087c MOV	0x18(%R12),%RDX

0x430881 MOV	%EAX,%ECX

0x430883 MOV	(%RDX),%EAX

0x430885 INC	%EAX

0x430887 SUB	%R14D,%EAX

0x43088a CLTD

0x43088b IDIV	%R13D

0x43088e CMP	%EDX,%ECX

0x430890 JL	430e9b

0x430896 IMUL	%EAX,%ECX

0x430899 ADD	%ECX,%EDX

0x43089b ADD	%EDX,%EAX

0x43089d CMP	%EAX,%EDX

0x43089f JGE	430e7e

0x4308a5 MOV	0x8(%R12),%RDI

0x4308aa MOV	(%R12),%RSI

0x4308ae MOV	(%RDI),%R11D

0x4308b1 ADD	%R14D,%EDX

0x4308b4 MOV	0x40(%R12),%RDI

0x4308b9 MOVSXD	%EDX,%RCX

0x4308bc MOV	0x28(%R12),%R8

0x4308c1 MOVSXD	(%RSI),%R15

0x4308c4 MOV	%RDI,0x38(%RSP)

0x4308c9 MOV	0x48(%R12),%RSI

0x4308ce IMUL	%RCX,%RDI

0x4308d2 MOV	%R8,0x78(%RSP)

0x4308d7 MOV	0x50(%R12),%R8

0x4308dc MOV	0x30(%R12),%R9

0x4308e1 ADD	%R15,%RSI

0x4308e4 ADD	%RDI,%RSI

0x4308e7 MOV	%R8,0x30(%RSP)

0x4308ec MOV	0x58(%R12),%RDI

0x4308f1 IMUL	%RCX,%R8

0x4308f5 MOV	%R9,0x70(%RSP)

0x4308fa MOV	0x60(%R12),%R9

0x4308ff MOV	0x38(%R12),%R13

0x430904 ADD	%R15,%RDI

0x430907 ADD	%R8,%RDI

0x43090a MOV	%R9,0x40(%RSP)

0x43090f MOV	0x68(%R12),%R8

0x430914 IMUL	%RCX,%R9

0x430918 MOV	%R13,0x68(%RSP)

0x43091d MOV	0x70(%R12),%R13

0x430922 ADD	%R15,%R8

0x430925 IMUL	%R13,%RCX

0x430929 ADD	%R9,%R8

0x43092c MOV	0x78(%R12),%R9

0x430931 ADD	%R14D,%EAX

0x430934 ADD	%R15,%R9

0x430937 ADD	%RCX,%R9

0x43093a MOV	%EAX,0x58(%RSP)

0x43093e CMP	%R11D,%R15D

0x430941 LEA	0x1(%R11),%EAX

0x430945 MOV	%R15D,%ECX

0x430948 MOV	%R15D,0x48(%RSP)

0x43094d MOV	%R11D,0x4c(%RSP)

0x430952 MOV	%R15,0x18(%RSP)

0x430957 MOV	%R13,0x28(%RSP)

0x43095c MOV	0x20(%R12),%R10

0x430961 CMOVLE	%EAX,%ECX

0x430964 JG	430ea4

0x43096a SUB	%R15D,%R11D

0x43096d LEA	0x1(%R11),%EBX

0x430971 MOV	%EBX,0x24(%RSP)

0x430975 SHR	$0x3,%EBX

0x430978 SAL	$0x6,%RBX

0x43097c VMOVSD	0x70afc(%RIP),%XMM7

0x430984 VMOVSD	0x70fc4(%RIP),%XMM6

0x43098c MOV	%R11D,0x5c(%RSP)

0x430991 MOV	%RBX,0x60(%RSP)

0x430996 MOV	%ECX,0x20(%RSP)

0x43099a MOV	%R12,0x10(%RSP)

0x43099f VMOVSD	0x70fb1(%RIP),%XMM5

0x4309a7 VBROADCASTSD	%XMM7,%YMM9

0x4309ac VBROADCASTSD	%XMM6,%YMM8

0x4309b1 NOPL	(%RAX)

(212) 0x4309b8 CMPL	$0x6,0x5c(%RSP)

(212) 0x4309bd JBE	430e90

(212) 0x4309c3 MOV	0x70(%RSP),%R11

(212) 0x4309c8 MOV	0x60(%RSP),%R15

(212) 0x4309cd LEA	(%R11,%R8,8),%RBX

(212) 0x4309d1 LEA	-0x40(%R15),%R11

(212) 0x4309d5 MOV	0x78(%RSP),%R12

(212) 0x4309da MOV	0x68(%RSP),%R13

(212) 0x4309df SHR	$0x6,%R11

(212) 0x4309e3 INC	%R11

(212) 0x4309e6 LEA	(%R12,%RDI,8),%RCX

(212) 0x4309ea VBROADCASTSD	0x70a8c(%RIP),%ZMM4

(212) 0x4309f4 VBROADCASTSD	0x70f52(%RIP),%ZMM3

(212) 0x4309fe VBROADCASTSD	0x70f50(%RIP),%ZMM2

(212) 0x430a08 LEA	(%R10,%RSI,8),%R14

(212) 0x430a0c LEA	(%R13,%R9,8),%R12

(212) 0x430a11 XOR	%EAX,%EAX

(212) 0x430a13 AND	$0x3,%R11D

(212) 0x430a17 JE	430b16

(212) 0x430a1d CMP	$0x1,%R11

(212) 0x430a21 JE	430ac0

(212) 0x430a27 CMP	$0x2,%R11

(212) 0x430a2b JE	430a75

(212) 0x430a2d VMOVUPD	(%R14),%ZMM1

(212) 0x430a33 MOV	$0x40,%EAX

(212) 0x430a38 VMULPD	(%RCX),%ZMM1,%ZMM0

(212) 0x430a3e VDIVPD	%ZMM1,%ZMM4,%ZMM10

(212) 0x430a44 VMULPD	%ZMM10,%ZMM10,%ZMM14

(212) 0x430a4a VMULPD	%ZMM3,%ZMM0,%ZMM11

(212) 0x430a50 VMOVUPD	%ZMM11,(%RBX)

(212) 0x430a56 VMULPD	(%R14),%ZMM2,%ZMM12

(212) 0x430a5c VMULPD	%ZMM11,%ZMM12,%ZMM13

(212) 0x430a62 VMULPD	%ZMM14,%ZMM13,%ZMM15

(212) 0x430a68 VSQRTPD	%ZMM15,%ZMM1

(212) 0x430a6e VMOVUPD	%ZMM1,(%R12)

(212) 0x430a75 VMOVUPD	(%R14,%RAX,1),%ZMM0

(212) 0x430a7c VMULPD	(%RCX,%RAX,1),%ZMM0,%ZMM11

(212) 0x430a83 VDIVPD	%ZMM0,%ZMM4,%ZMM10

(212) 0x430a89 VMULPD	%ZMM10,%ZMM10,%ZMM15

(212) 0x430a8f VMULPD	%ZMM3,%ZMM11,%ZMM12

(212) 0x430a95 VMOVUPD	%ZMM12,(%RBX,%RAX,1)

(212) 0x430a9c VMULPD	(%R14,%RAX,1),%ZMM2,%ZMM13

(212) 0x430aa3 VMULPD	%ZMM12,%ZMM13,%ZMM14

(212) 0x430aa9 VMULPD	%ZMM15,%ZMM14,%ZMM1

(212) 0x430aaf VSQRTPD	%ZMM1,%ZMM0

(212) 0x430ab5 VMOVUPD	%ZMM0,(%R12,%RAX,1)

(212) 0x430abc ADD	$0x40,%RAX

(212) 0x430ac0 VMOVUPD	(%R14,%RAX,1),%ZMM11

(212) 0x430ac7 VMULPD	(%RCX,%RAX,1),%ZMM11,%ZMM12

(212) 0x430ace VDIVPD	%ZMM11,%ZMM4,%ZMM10

(212) 0x430ad4 VMULPD	%ZMM10,%ZMM10,%ZMM1

(212) 0x430ada VMULPD	%ZMM3,%ZMM12,%ZMM13

(212) 0x430ae0 VMOVUPD	%ZMM13,(%RBX,%RAX,1)

(212) 0x430ae7 VMULPD	(%R14,%RAX,1),%ZMM2,%ZMM14

(212) 0x430aee VMULPD	%ZMM13,%ZMM14,%ZMM15

(212) 0x430af4 VMULPD	%ZMM1,%ZMM15,%ZMM0

(212) 0x430afa VSQRTPD	%ZMM0,%ZMM11

(212) 0x430b00 VMOVUPD	%ZMM11,(%R12,%RAX,1)

(212) 0x430b07 ADD	$0x40,%RAX

(212) 0x430b0b CMP	%RAX,0x60(%RSP)

(212) 0x430b10 JE	430c55

(212) 0x430b16 MOV	0x60(%RSP),%R13

  (213) 0x430b1b VMOVUPD	(%R14,%RAX,1),%ZMM12

  (213) 0x430b22 VMULPD	(%RCX,%RAX,1),%ZMM12,%ZMM13

  (213) 0x430b29 VDIVPD	%ZMM12,%ZMM4,%ZMM10

  (213) 0x430b2f VMULPD	%ZMM10,%ZMM10,%ZMM0

  (213) 0x430b35 VMULPD	%ZMM3,%ZMM13,%ZMM14

  (213) 0x430b3b VMOVUPD	%ZMM14,(%RBX,%RAX,1)

  (213) 0x430b42 VMULPD	(%R14,%RAX,1),%ZMM2,%ZMM15

  (213) 0x430b49 VMULPD	%ZMM14,%ZMM15,%ZMM1

  (213) 0x430b4f VMULPD	%ZMM0,%ZMM1,%ZMM11

  (213) 0x430b55 VSQRTPD	%ZMM11,%ZMM12

  (213) 0x430b5b VMOVUPD	%ZMM12,(%R12,%RAX,1)

  (213) 0x430b62 VMOVUPD	0x40(%R14,%RAX,1),%ZMM13

  (213) 0x430b6a VMULPD	0x40(%RCX,%RAX,1),%ZMM13,%ZMM14

  (213) 0x430b72 VDIVPD	%ZMM13,%ZMM4,%ZMM10

  (213) 0x430b78 VMULPD	%ZMM10,%ZMM10,%ZMM11

  (213) 0x430b7e VMULPD	%ZMM3,%ZMM14,%ZMM15

  (213) 0x430b84 VMOVUPD	%ZMM15,0x40(%RBX,%RAX,1)

  (213) 0x430b8c VMULPD	0x40(%R14,%RAX,1),%ZMM2,%ZMM1

  (213) 0x430b94 VMULPD	%ZMM15,%ZMM1,%ZMM0

  (213) 0x430b9a VMULPD	%ZMM11,%ZMM0,%ZMM12

  (213) 0x430ba0 VSQRTPD	%ZMM12,%ZMM13

  (213) 0x430ba6 VMOVUPD	%ZMM13,0x40(%R12,%RAX,1)

  (213) 0x430bae VMOVUPD	0x80(%R14,%RAX,1),%ZMM14

  (213) 0x430bb6 VMULPD	0x80(%RCX,%RAX,1),%ZMM14,%ZMM15

  (213) 0x430bbe VDIVPD	%ZMM14,%ZMM4,%ZMM10

  (213) 0x430bc4 VMULPD	%ZMM10,%ZMM10,%ZMM12

  (213) 0x430bca VMULPD	%ZMM3,%ZMM15,%ZMM1

  (213) 0x430bd0 VMOVUPD	%ZMM1,0x80(%RBX,%RAX,1)

  (213) 0x430bd8 VMULPD	0x80(%R14,%RAX,1),%ZMM2,%ZMM0

  (213) 0x430be0 VMULPD	%ZMM1,%ZMM0,%ZMM11

  (213) 0x430be6 VMULPD	%ZMM12,%ZMM11,%ZMM13

  (213) 0x430bec VSQRTPD	%ZMM13,%ZMM14

  (213) 0x430bf2 VMOVUPD	%ZMM14,0x80(%R12,%RAX,1)

  (213) 0x430bfa VMOVUPD	0xc0(%R14,%RAX,1),%ZMM15

  (213) 0x430c02 VMULPD	0xc0(%RCX,%RAX,1),%ZMM15,%ZMM1

  (213) 0x430c0a VDIVPD	%ZMM15,%ZMM4,%ZMM10

  (213) 0x430c10 VMULPD	%ZMM10,%ZMM10,%ZMM13

  (213) 0x430c16 VMULPD	%ZMM3,%ZMM1,%ZMM11

  (213) 0x430c1c VMOVUPD	%ZMM11,0xc0(%RBX,%RAX,1)

  (213) 0x430c24 VMULPD	0xc0(%R14,%RAX,1),%ZMM2,%ZMM0

  (213) 0x430c2c VMULPD	%ZMM11,%ZMM0,%ZMM12

  (213) 0x430c32 VMULPD	%ZMM13,%ZMM12,%ZMM14

  (213) 0x430c38 VSQRTPD	%ZMM14,%ZMM15

  (213) 0x430c3e VMOVUPD	%ZMM15,0xc0(%R12,%RAX,1)

  (213) 0x430c46 ADD	$0x100,%RAX

  (213) 0x430c4c CMP	%RAX,%R13

  (213) 0x430c4f JNE	430b1b

(212) 0x430c55 MOV	0x24(%RSP),%R14D

(212) 0x430c5a MOV	0x48(%RSP),%EAX

(212) 0x430c5e MOV	%R14D,%ECX

(212) 0x430c61 AND	$-0x8,%ECX

(212) 0x430c64 ADD	%ECX,%EAX

(212) 0x430c66 AND	$0x7,%R14D

(212) 0x430c6a JE	430e3c

(212) 0x430c70 MOV	0x5c(%RSP),%EBX

(212) 0x430c74 SUB	%ECX,%EBX

(212) 0x430c76 LEA	0x1(%RBX),%R11D

(212) 0x430c7a CMP	$0x2,%EBX

(212) 0x430c7d JBE	430cf3

(212) 0x430c7f LEA	(%RSI,%RCX,1),%R12

(212) 0x430c83 LEA	(%R10,%R12,8),%RBX

(212) 0x430c87 VMOVUPD	(%RBX),%YMM4

(212) 0x430c8b MOV	0x78(%RSP),%R13

(212) 0x430c90 VDIVPD	%YMM4,%YMM9,%YMM3

(212) 0x430c94 LEA	(%RDI,%RCX,1),%R15

(212) 0x430c98 VMULPD	(%R13,%R15,8),%YMM4,%YMM2

(212) 0x430c9f MOV	0x70(%RSP),%R14

(212) 0x430ca4 LEA	(%R9,%RCX,1),%R12

(212) 0x430ca8 VBROADCASTSD	0x70ca7(%RIP),%YMM1

(212) 0x430cb1 ADD	%R8,%RCX

(212) 0x430cb4 VMULPD	%YMM8,%YMM2,%YMM10

(212) 0x430cb9 VMOVUPD	%YMM10,(%R14,%RCX,8)

(212) 0x430cbf VMULPD	(%RBX),%YMM1,%YMM11

(212) 0x430cc3 MOV	%R11D,%EBX

(212) 0x430cc6 AND	$-0x4,%EBX

(212) 0x430cc9 MOV	0x68(%RSP),%RCX

(212) 0x430cce ADD	%EBX,%EAX

(212) 0x430cd0 VMULPD	%YMM10,%YMM11,%YMM0

(212) 0x430cd5 AND	$0x3,%R11D

(212) 0x430cd9 VMULPD	%YMM3,%YMM3,%YMM12

(212) 0x430cdd VMULPD	%YMM12,%YMM0,%YMM13

(212) 0x430ce2 VSQRTPD	%YMM13,%YMM14

(212) 0x430ce7 VMOVUPD	%YMM14,(%RCX,%R12,8)

(212) 0x430ced JE	430e3c

(212) 0x430cf3 MOV	0x18(%RSP),%R15

(212) 0x430cf8 MOV	%RSI,%R11

(212) 0x430cfb MOV	%R9,%R14

(212) 0x430cfe MOVSXD	%EAX,%RCX

(212) 0x430d01 SUB	%R15,%R14

(212) 0x430d04 SUB	%R15,%R11

(212) 0x430d07 MOV	%R14,0x50(%RSP)

(212) 0x430d0c LEA	(%R11,%RCX,1),%R14

(212) 0x430d10 VMOVSD	(%R10,%R14,8),%XMM15

(212) 0x430d16 MOV	%RDI,%R13

(212) 0x430d19 VDIVSD	%XMM15,%XMM7,%XMM4

(212) 0x430d1e MOV	0x78(%RSP),%RBX

(212) 0x430d23 SUB	%R15,%R13

(212) 0x430d26 MOV	%R8,%R12

(212) 0x430d29 SUB	%R15,%R12

(212) 0x430d2c LEA	(%RCX,%R13,1),%R15

(212) 0x430d30 VMULSD	(%RBX,%R15,8),%XMM15,%XMM3

(212) 0x430d36 MOV	0x70(%RSP),%RBX

(212) 0x430d3b LEA	(%RCX,%R12,1),%R15

(212) 0x430d3f VMULSD	%XMM6,%XMM3,%XMM2

(212) 0x430d43 VMOVSD	%XMM2,(%RBX,%R15,8)

(212) 0x430d49 VMULSD	(%R10,%R14,8),%XMM5,%XMM10

(212) 0x430d4f MOV	0x50(%RSP),%R14

(212) 0x430d54 MOV	0x68(%RSP),%R15

(212) 0x430d59 ADD	%R14,%RCX

(212) 0x430d5c VMULSD	%XMM2,%XMM10,%XMM1

(212) 0x430d60 VMULSD	%XMM4,%XMM4,%XMM11

(212) 0x430d64 VMULSD	%XMM11,%XMM1,%XMM0

(212) 0x430d69 VSQRTSD	%XMM0,%XMM0,%XMM0

(212) 0x430d6d VMOVSD	%XMM0,(%R15,%RCX,8)

(212) 0x430d73 LEA	0x1(%RAX),%ECX

(212) 0x430d76 CMP	%ECX,0x4c(%RSP)

(212) 0x430d7a JL	430e3c

(212) 0x430d80 MOVSXD	%ECX,%RCX

(212) 0x430d83 LEA	(%R11,%RCX,1),%R14

(212) 0x430d87 VMOVSD	(%R10,%R14,8),%XMM12

(212) 0x430d8d MOV	0x78(%RSP),%RBX

(212) 0x430d92 VDIVSD	%XMM12,%XMM7,%XMM13

(212) 0x430d97 LEA	(%R13,%RCX,1),%R15

(212) 0x430d9c VMULSD	(%RBX,%R15,8),%XMM12,%XMM14

(212) 0x430da2 MOV	0x70(%RSP),%RBX

(212) 0x430da7 LEA	(%R12,%RCX,1),%R15

(212) 0x430dab ADD	$0x2,%EAX

(212) 0x430dae VMULSD	%XMM6,%XMM14,%XMM15

(212) 0x430db2 VMOVSD	%XMM15,(%RBX,%R15,8)

(212) 0x430db8 VMULSD	(%R10,%R14,8),%XMM5,%XMM4

(212) 0x430dbe MOV	0x50(%RSP),%R15

(212) 0x430dc3 MOV	0x68(%RSP),%R14

(212) 0x430dc8 ADD	%R15,%RCX

(212) 0x430dcb VMULSD	%XMM15,%XMM4,%XMM3

(212) 0x430dd0 VMULSD	%XMM13,%XMM13,%XMM2

(212) 0x430dd5 VMULSD	%XMM2,%XMM3,%XMM10

(212) 0x430dd9 VSQRTSD	%XMM10,%XMM10,%XMM10

(212) 0x430dde VMOVSD	%XMM10,(%R14,%RCX,8)

(212) 0x430de4 CMP	%EAX,0x4c(%RSP)

(212) 0x430de8 JL	430e3c

(212) 0x430dea CLTQ

(212) 0x430dec ADD	%RAX,%R11

(212) 0x430def VMOVSD	(%R10,%R11,8),%XMM1

(212) 0x430df5 MOV	0x78(%RSP),%RCX

(212) 0x430dfa VDIVSD	%XMM1,%XMM7,%XMM11

(212) 0x430dfe ADD	%RAX,%R13

(212) 0x430e01 VMULSD	(%RCX,%R13,8),%XMM1,%XMM0

(212) 0x430e07 MOV	0x70(%RSP),%R13

(212) 0x430e0c ADD	%RAX,%R12

(212) 0x430e0f ADD	%RAX,%R15

(212) 0x430e12 VMULSD	%XMM6,%XMM0,%XMM12

(212) 0x430e16 VMOVSD	%XMM12,(%R13,%R12,8)

(212) 0x430e1d VMULSD	(%R10,%R11,8),%XMM5,%XMM13

(212) 0x430e23 VMULSD	%XMM12,%XMM13,%XMM14

(212) 0x430e28 VMULSD	%XMM11,%XMM11,%XMM15

(212) 0x430e2d VMULSD	%XMM15,%XMM14,%XMM4

(212) 0x430e32 VSQRTSD	%XMM4,%XMM4,%XMM4

(212) 0x430e36 VMOVSD	%XMM4,(%R14,%R15,8)

(212) 0x430e3c MOV	0x38(%RSP),%RAX

(212) 0x430e41 MOV	0x30(%RSP),%R11

(212) 0x430e46 MOV	0x40(%RSP),%R12

(212) 0x430e4b MOV	0x28(%RSP),%RBX

(212) 0x430e50 INC	%EDX

(212) 0x430e52 ADD	%RAX,%RSI

(212) 0x430e55 ADD	%R11,%RDI

(212) 0x430e58 ADD	%R12,%R8

(212) 0x430e5b ADD	%RBX,%R9

(212) 0x430e5e CMP	%EDX,0x58(%RSP)

(212) 0x430e62 JG	4309b8

0x430e68 MOV	0x20(%RSP),%ECX

0x430e6c MOV	0x10(%RSP),%R12

0x430e71 VZEROUPPER

0x430e74 MOV	%ECX,%EBX

0x430e76 MOV	%EBX,0x80(%R12)

0x430e7e LEA	-0x28(%RBP),%RSP

0x430e82 POP	%RBX

0x430e83 POP	%R12

0x430e85 POP	%R13

0x430e87 POP	%R14

0x430e89 POP	%R15

0x430e8b POP	%RBP

0x430e8c RET

0x430e8d NOPL	(%RAX)

(212) 0x430e90 MOV	0x48(%RSP),%EAX

(212) 0x430e94 XOR	%ECX,%ECX

(212) 0x430e96 JMP	430c70

0x430e9b INC	%EAX

0x430e9d XOR	%EDX,%EDX

0x430e9f JMP	430896

0x430ea4 XOR	%R15D,%R15D

0x430ea7 NOPW	(%RAX,%RAX,1)

(211) 0x430eb0 INC	%EDX

(211) 0x430eb2 CMP	%ECX,%EAX

(211) 0x430eb4 JE	430ed0

(211) 0x430eb6 CMP	%EDX,0x58(%RSP)

(211) 0x430eba JG	430eb0

0x430ebc TEST	%R15B,%R15B

0x430ebf JNE	430e76

0x430ec1 LEA	-0x28(%RBP),%RSP

0x430ec5 POP	%RBX

0x430ec6 POP	%R12

0x430ec8 POP	%R13

0x430eca POP	%R14

0x430ecc POP	%R15

0x430ece POP	%RBP

0x430ecf RET

(211) 0x430ed0 CMP	%EDX,0x58(%RSP)

(211) 0x430ed4 JLE	430e74

(211) 0x430ed6 MOV	%EAX,%EBX

(211) 0x430ed8 MOV	$0x1,%R15D

(211) 0x430ede JMP	430eb0

Coverage (%)	Name	Source Location	Module
○97.62	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.38	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:45-55.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.00 to 2.17 cycles (9.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:55

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 180 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	120
nb uops	126
loop length	441
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.00 cycles
front end	21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.80	8.80	13.00	13.00	12.50	8.80	8.80	12.50	12.50	12.50	8.80	13.00
cycles	8.80	12.93	13.00	13.00	12.50	8.80	8.80	12.50	12.50	12.50	8.80	13.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	21.00
Dispatch	13.00
DIV/SQRT	6.00
Overall L1	21.00

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	10%
load	11%
store	9%
mul	10%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	9%
mul	10%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.00 cycles. At this rate:

4% of peak load performance is reached (8.57 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.00 to 13.00 cycles (1.62x speedup).

ASM code

In the binary file, the address of the function is: 430850

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%R12),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 430e9b <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x64b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 430e7e <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x62e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x40(%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EDX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV 0x28(%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD (%RSI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R8,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R9,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%R12),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R15,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %RCX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R13,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x70(%R12),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R15,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
IMUL %R13,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x78(%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %EAX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R11D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%R11),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R11D,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMOVLE %EAX,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
JG 430ea4 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x654>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %R15D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%R11),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EBX,0x24(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SHR $0x3,%EBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
SAL $0x6,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
VMOVSD 0x70afc(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x70fc4(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11D,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RBX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ECX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R12,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x70fb1(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VBROADCASTSD %XMM7,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x10(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EBX,0x80(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 430896 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x46>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R15B,%R15B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 430e76 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x626>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	ideal_gas_kernel.f90:45-55
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.00 to 2.17 cycles (9.69x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:55

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/ideal_gas_kernel.f90:46

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 180 bytes. The binary function is storing 108 bytes.

General properties

nb instructions	120
nb uops	126
loop length	441
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	0
nb stack references	17

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.00 cycles
front end	21.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.80	8.80	13.00	13.00	12.50	8.80	8.80	12.50	12.50	12.50	8.80	13.00
cycles	8.80	12.93	13.00	13.00	12.50	8.80	8.80	12.50	12.50	12.50	8.80	13.00

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	21.00
Dispatch	13.00
DIV/SQRT	6.00
Overall L1	21.00

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

INT

all	10%
load	11%
store	9%
mul	10%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	9%
mul	10%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.00 cycles. At this rate:

4% of peak load performance is reached (8.57 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.14 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 430850

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R14D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%R12),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 430e9b <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x64b>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 430e7e <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x62e>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x8(%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R14D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x40(%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EDX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV 0x28(%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD (%RSI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%R12),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R8,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R15,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDI,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%R12),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R9,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x38(%R12),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R15,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%R12),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %RCX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV %R13,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x70(%R12),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R15,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
IMUL %R13,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x78(%R12),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %EAX,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R11D,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%R11),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R11D,0x4c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x18(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R12),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMOVLE %EAX,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
JG 430ea4 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x654>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %R15D,%R11D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%R11),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EBX,0x24(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SHR $0x3,%EBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
SAL $0x6,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
VMOVSD 0x70afc(%RIP),%XMM7	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD 0x70fc4(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R11D,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RBX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %ECX,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R12,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x70fb1(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VBROADCASTSD %XMM7,%YMM9	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM6,%YMM8	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x10(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EBX,0x80(%R12)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 430896 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x46>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %R15D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R15B,%R15B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 430e76 <__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0+0x626>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

Name	Coverage (%)	Time (s)
▼__ideal_gas_kernel_module_MOD_ideal_gas_kernel._omp_fn.0–	4.95	1.75
▼Loop 212 - ideal_gas_kernel.f90:48-55 - exec–	0.00	0.00
○Loop 213 - ideal_gas_kernel.f90:50-55 - exec	4.95	1.75
○Loop 211 - ideal_gas_kernel.f90:45-48 - exec	0.00	0.00

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