OV - exec - Function __field_summary_kernel_module_MOD_field_summary_kernel._omp

	Function: __field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0	Module: exec	Source: field_summary_kernel.f90:54-71	Coverage (incl. loops): 0.30% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90: 54 - 71

--------------------------------------------------------------------------------

54:     !$OMP PARALLEL

55:     !$OMP DO PRIVATE(vsqrd,cell_vol,cell_mass) REDUCTION(+ : vol,mass,press,ie,ke)

56:     DO k=y_min,y_max

57:     !$OMP SIMD

58:       DO j=x_min,x_max

59:         vsqrd=0.0

60:         DO kv=k,k+1

61:           DO jv=j,j+1

62:             vsqrd=vsqrd+0.25*(xvel0(jv,kv)**2+yvel0(jv,kv)**2)

63:           ENDDO

64:         ENDDO

65:         cell_vol=volume(j,k)

66:         cell_mass=cell_vol*density0(j,k)

67:         vol=vol+cell_vol

68:         mass=mass+cell_mass

69:         ie=ie+cell_mass*energy0(j,k)

70:         ke=ke+cell_mass*0.5*vsqrd

71:         press=press+cell_vol*pressure(j,k)

0x42a810 PUSH	%RBP

0x42a811 MOV	%RSP,%RBP

0x42a814 PUSH	%R15

0x42a816 PUSH	%R14

0x42a818 PUSH	%R13

0x42a81a MOV	%RDI,%R13

0x42a81d PUSH	%R12

0x42a81f PUSH	%RBX

0x42a820 SUB	$0x58,%RSP

0x42a824 MOV	0x10(%RDI),%RAX

0x42a828 MOV	(%RAX),%R12D

0x42a82b CALL	402370 <@plt_start@+0x350>

0x42a830 MOV	%EAX,%EBX

0x42a832 CALL	4022e0 <@plt_start@+0x2c0>

0x42a837 MOV	0x18(%R13),%RDX

0x42a83b MOV	%EAX,%R14D

0x42a83e MOV	(%RDX),%EAX

0x42a840 INC	%EAX

0x42a842 SUB	%R12D,%EAX

0x42a845 CLTD

0x42a846 IDIV	%EBX

0x42a848 CMP	%EDX,%R14D

0x42a84b JL	42ad09

0x42a851 IMUL	%EAX,%R14D

0x42a855 ADD	%EDX,%R14D

0x42a858 ADD	%R14D,%EAX

0x42a85b CMP	%EAX,%R14D

0x42a85e JGE	42acf0

0x42a864 MOV	0xc8(%R13),%RSI

0x42a86b MOV	0xb8(%R13),%RDX

0x42a872 MOV	(%R13),%RCX

0x42a876 MOV	0x8(%R13),%R8

0x42a87a ADD	%R12D,%EAX

0x42a87d ADD	%R12D,%R14D

0x42a880 MOV	(%RCX),%EDI

0x42a882 MOV	(%R8),%R12D

0x42a885 MOVSXD	%R14D,%RCX

0x42a888 LEA	(,%RDX,8),%R10

0x42a890 MOV	%EAX,-0x40(%RBP)

0x42a893 LEA	(,%RSI,8),%RAX

0x42a89b MOV	%R10,-0x48(%RBP)

0x42a89f MOV	%RAX,-0x50(%RBP)

0x42a8a3 MOV	%RDX,%R11

0x42a8a6 LEA	0x1(%RCX),%RAX

0x42a8aa MOV	%RSI,%R10

0x42a8ad IMUL	%RCX,%R11

0x42a8b1 IMUL	%RCX,%R10

0x42a8b5 IMUL	%RAX,%RDX

0x42a8b9 LEA	0x1(%R12),%R9D

0x42a8be MOV	%R9D,-0x38(%RBP)

0x42a8c2 MOV	0xc0(%R13),%R9

0x42a8c9 MOV	0x48(%R13),%R8

0x42a8cd MOV	%EDI,-0x74(%RBP)

0x42a8d0 MOV	0x40(%R13),%RDI

0x42a8d4 ADD	0xd0(%R13),%R10

0x42a8db IMUL	%RAX,%RSI

0x42a8df ADD	%R9,%R11

0x42a8e2 ADD	%R9,%RDX

0x42a8e5 LEA	(%RDI,%R11,8),%RBX

0x42a8e9 LEA	(%R8,%R10,8),%R11

0x42a8ed LEA	(%RDI,%RDX,8),%R10

0x42a8f1 MOV	0xa8(%R13),%RDI

0x42a8f8 MOV	0xd0(%R13),%RDX

0x42a8ff MOV	0x78(%R13),%RAX

0x42a903 ADD	%RSI,%RDX

0x42a906 LEA	(,%RDI,8),%RSI

0x42a90e IMUL	%RCX,%RDI

0x42a912 LEA	(%R8,%RDX,8),%R9

0x42a916 MOV	0x20(%R13),%R8

0x42a91a LEA	(,%RAX,8),%RDX

0x42a922 IMUL	%RCX,%RAX

0x42a926 ADD	0xb0(%R13),%RDI

0x42a92d LEA	(%R8,%RDI,8),%R8

0x42a931 MOV	0x28(%R13),%RDI

0x42a935 ADD	0x80(%R13),%RAX

0x42a93c LEA	(%RDI,%RAX,8),%RDI

0x42a940 MOV	0x88(%R13),%RAX

0x42a947 MOV	%RSI,-0x58(%RBP)

0x42a94b LEA	(,%RAX,8),%RSI

0x42a953 IMUL	%RCX,%RAX

0x42a957 MOV	%RDX,-0x60(%RBP)

0x42a95b MOV	0x30(%R13),%RDX

0x42a95f ADD	0x90(%R13),%RAX

0x42a966 MOV	%RSI,-0x68(%RBP)

0x42a96a LEA	(%RDX,%RAX,8),%RSI

0x42a96e MOV	0x98(%R13),%RAX

0x42a975 VXORPD	%XMM4,%XMM4,%XMM4

0x42a979 LEA	(,%RAX,8),%RDX

0x42a981 IMUL	%RCX,%RAX

0x42a985 MOV	0x38(%R13),%RCX

0x42a989 MOV	%RDX,-0x70(%RBP)

0x42a98d ADD	0xa0(%R13),%RAX

0x42a994 VMOVDDUP	0x76dec(%RIP),%XMM5

0x42a99c MOV	%R13,-0x80(%RBP)

0x42a9a0 VMOVSD	0x76df0(%RIP),%XMM6

0x42a9a8 MOV	-0x74(%RBP),%R13D

0x42a9ac LEA	(%RCX,%RAX,8),%RCX

0x42a9b0 VMOVAPD	%XMM4,%XMM7

0x42a9b4 XOR	%EAX,%EAX

0x42a9b6 VMOVAPD	%XMM4,%XMM2

0x42a9ba VMOVAPD	%XMM4,%XMM8

0x42a9be VMOVAPD	%XMM4,%XMM9

0x42a9c2 KMOVB	%EAX,%K0

0x42a9c6 NOPW	%CS:(%RAX,%RAX,1)

(162) 0x42a9d0 CMP	%R12D,%R13D

(162) 0x42a9d3 JG	42acd2

(162) 0x42a9d9 MOVSXD	%R13D,%RDX

(162) 0x42a9dc VMOVUPD	(%R11,%RDX,8),%XMM0

(162) 0x42a9e2 VMOVUPD	(%R9,%RDX,8),%XMM14

(162) 0x42a9e8 VMULPD	%XMM0,%XMM0,%XMM3

(162) 0x42a9ec VMULPD	%XMM14,%XMM14,%XMM15

(162) 0x42a9f1 VMOVUPD	(%RBX,%RDX,8),%XMM1

(162) 0x42a9f6 VMOVUPD	(%R10,%RDX,8),%XMM13

(162) 0x42a9fc MOV	%R12D,%R15D

(162) 0x42a9ff VFMADD132PD	%XMM1,%XMM3,%XMM1

(162) 0x42aa04 VFMADD132PD	%XMM13,%XMM15,%XMM13

(162) 0x42aa09 SUB	%R13D,%R15D

(162) 0x42aa0c LEA	0x1(%RDX),%RAX

(162) 0x42aa10 AND	$0x1,%R15D

(162) 0x42aa14 VMULPD	%XMM5,%XMM1,%XMM10

(162) 0x42aa18 VMULPD	%XMM5,%XMM13,%XMM1

(162) 0x42aa1c VUNPCKHPD	%XMM10,%XMM10,%XMM11

(162) 0x42aa21 VUNPCKHPD	%XMM1,%XMM1,%XMM0

(162) 0x42aa25 VADDPD	%XMM10,%XMM11,%XMM12

(162) 0x42aa2a VADDPD	%XMM1,%XMM0,%XMM3

(162) 0x42aa2e VMOVSD	(%R8,%RDX,8),%XMM11

(162) 0x42aa34 VADDSD	%XMM3,%XMM12,%XMM10

(162) 0x42aa38 VMULSD	(%RDI,%RDX,8),%XMM11,%XMM12

(162) 0x42aa3d VFMADD231SD	(%RCX,%RDX,8),%XMM11,%XMM2

(162) 0x42aa43 VMULSD	%XMM6,%XMM10,%XMM13

(162) 0x42aa47 VADDSD	%XMM11,%XMM9,%XMM9

(162) 0x42aa4c VFMADD231SD	(%RSI,%RDX,8),%XMM12,%XMM7

(162) 0x42aa52 VADDSD	%XMM12,%XMM8,%XMM8

(162) 0x42aa57 VFMADD231SD	%XMM13,%XMM12,%XMM4

(162) 0x42aa5c CMP	%EAX,%R12D

(162) 0x42aa5f JL	42abeb

(162) 0x42aa65 TEST	%R15D,%R15D

(162) 0x42aa68 JE	42aaf0

(162) 0x42aa6e VMOVUPD	(%R11,%RAX,8),%XMM15

(162) 0x42aa74 VMOVUPD	(%R9,%RAX,8),%XMM12

(162) 0x42aa7a VMULPD	%XMM15,%XMM15,%XMM1

(162) 0x42aa7f VMULPD	%XMM12,%XMM12,%XMM13

(162) 0x42aa84 VMOVUPD	(%RBX,%RAX,8),%XMM14

(162) 0x42aa89 VMOVUPD	(%R10,%RAX,8),%XMM11

(162) 0x42aa8f VFMADD132PD	%XMM14,%XMM1,%XMM14

(162) 0x42aa94 VFMADD132PD	%XMM11,%XMM13,%XMM11

(162) 0x42aa99 VMULPD	%XMM5,%XMM14,%XMM3

(162) 0x42aa9d VMULPD	%XMM5,%XMM11,%XMM14

(162) 0x42aaa1 VUNPCKHPD	%XMM3,%XMM3,%XMM0

(162) 0x42aaa5 VUNPCKHPD	%XMM14,%XMM14,%XMM15

(162) 0x42aaaa VADDPD	%XMM3,%XMM0,%XMM10

(162) 0x42aaae VADDPD	%XMM14,%XMM15,%XMM1

(162) 0x42aab3 VADDSD	%XMM1,%XMM10,%XMM0

(162) 0x42aab7 VMOVSD	(%R8,%RAX,8),%XMM10

(162) 0x42aabd VMULSD	(%RDI,%RAX,8),%XMM10,%XMM3

(162) 0x42aac2 VMULSD	%XMM6,%XMM0,%XMM11

(162) 0x42aac6 VFMADD231SD	(%RCX,%RAX,8),%XMM10,%XMM2

(162) 0x42aacc VADDSD	%XMM10,%XMM9,%XMM9

(162) 0x42aad1 VFMADD231SD	(%RSI,%RAX,8),%XMM3,%XMM7

(162) 0x42aad7 LEA	0x2(%RDX),%RAX

(162) 0x42aadb VFMADD231SD	%XMM11,%XMM3,%XMM4

(162) 0x42aae0 VADDSD	%XMM3,%XMM8,%XMM8

(162) 0x42aae4 CMP	%EAX,%R12D

(162) 0x42aae7 JL	42abeb

(162) 0x42aaed NOPL	(%RAX)

  (163) 0x42aaf0 VMOVUPD	(%R11,%RAX,8),%XMM13

  (163) 0x42aaf6 VMOVUPD	(%R9,%RAX,8),%XMM3

  (163) 0x42aafc VMULPD	%XMM13,%XMM13,%XMM14

  (163) 0x42ab01 VMULPD	%XMM3,%XMM3,%XMM11

  (163) 0x42ab05 VMOVUPD	(%RBX,%RAX,8),%XMM12

  (163) 0x42ab0a VMOVUPD	(%R10,%RAX,8),%XMM10

  (163) 0x42ab10 LEA	0x1(%RAX),%RDX

  (163) 0x42ab14 VFMADD132PD	%XMM12,%XMM14,%XMM12

  (163) 0x42ab19 VFMADD132PD	%XMM10,%XMM11,%XMM10

  (163) 0x42ab1e VMOVUPD	(%R11,%RDX,8),%XMM11

  (163) 0x42ab24 VMOVUPD	(%RBX,%RDX,8),%XMM3

  (163) 0x42ab29 VMULPD	%XMM5,%XMM12,%XMM15

  (163) 0x42ab2d VMULPD	%XMM5,%XMM10,%XMM12

  (163) 0x42ab31 VUNPCKHPD	%XMM15,%XMM15,%XMM1

  (163) 0x42ab36 VUNPCKHPD	%XMM12,%XMM12,%XMM13

  (163) 0x42ab3b VADDPD	%XMM12,%XMM13,%XMM14

  (163) 0x42ab40 VADDPD	%XMM15,%XMM1,%XMM0

  (163) 0x42ab45 VMOVSD	(%R8,%RAX,8),%XMM1

  (163) 0x42ab4b VMULPD	%XMM11,%XMM11,%XMM12

  (163) 0x42ab50 VADDSD	%XMM14,%XMM0,%XMM15

  (163) 0x42ab55 VMULSD	(%RDI,%RAX,8),%XMM1,%XMM10

  (163) 0x42ab5a VFMADD231SD	(%RCX,%RAX,8),%XMM1,%XMM2

  (163) 0x42ab60 VMULSD	%XMM6,%XMM15,%XMM0

  (163) 0x42ab64 VADDSD	%XMM1,%XMM9,%XMM9

  (163) 0x42ab68 VMOVUPD	(%R10,%RDX,8),%XMM1

  (163) 0x42ab6e VFMADD231SD	(%RSI,%RAX,8),%XMM10,%XMM7

  (163) 0x42ab74 VADDSD	%XMM10,%XMM8,%XMM8

  (163) 0x42ab79 VFMADD231SD	%XMM0,%XMM10,%XMM4

  (163) 0x42ab7e VMOVUPD	(%R9,%RDX,8),%XMM10

  (163) 0x42ab84 VFMADD132PD	%XMM3,%XMM12,%XMM3

  (163) 0x42ab89 VMULPD	%XMM10,%XMM10,%XMM0

  (163) 0x42ab8e ADD	$0x2,%RAX

  (163) 0x42ab92 VMULPD	%XMM5,%XMM3,%XMM13

  (163) 0x42ab96 VFMADD132PD	%XMM1,%XMM0,%XMM1

  (163) 0x42ab9b VUNPCKHPD	%XMM13,%XMM13,%XMM14

  (163) 0x42aba0 VMULPD	%XMM5,%XMM1,%XMM11

  (163) 0x42aba4 VADDPD	%XMM13,%XMM14,%XMM15

  (163) 0x42aba9 VMOVSD	(%R8,%RDX,8),%XMM14

  (163) 0x42abaf VFMADD231SD	(%RCX,%RDX,8),%XMM14,%XMM2

  (163) 0x42abb5 VUNPCKHPD	%XMM11,%XMM11,%XMM3

  (163) 0x42abba VADDPD	%XMM11,%XMM3,%XMM12

  (163) 0x42abbf VADDSD	%XMM14,%XMM9,%XMM9

  (163) 0x42abc4 VADDSD	%XMM12,%XMM15,%XMM13

  (163) 0x42abc9 VMULSD	(%RDI,%RDX,8),%XMM14,%XMM15

  (163) 0x42abce VMULSD	%XMM6,%XMM13,%XMM1

  (163) 0x42abd2 VFMADD231SD	(%RSI,%RDX,8),%XMM15,%XMM7

  (163) 0x42abd8 VADDSD	%XMM15,%XMM8,%XMM8

  (163) 0x42abdd VFMADD231SD	%XMM1,%XMM15,%XMM4

  (163) 0x42abe2 CMP	%EAX,%R12D

  (163) 0x42abe5 JGE	42aaf0

(162) 0x42abeb MOV	-0x38(%RBP),%R15D

(162) 0x42abef MOV	$0x1,%EAX

(162) 0x42abf4 KMOVB	%EAX,%K0

(162) 0x42abf8 MOV	-0x48(%RBP),%RDX

(162) 0x42abfc MOV	-0x50(%RBP),%RAX

(162) 0x42ac00 ADD	%RDX,%RBX

(162) 0x42ac03 ADD	%RAX,%R11

(162) 0x42ac06 ADD	%RDX,%R10

(162) 0x42ac09 ADD	%RAX,%R9

(162) 0x42ac0c MOV	-0x58(%RBP),%RDX

(162) 0x42ac10 MOV	-0x60(%RBP),%RAX

(162) 0x42ac14 ADD	%RDX,%R8

(162) 0x42ac17 ADD	%RAX,%RDI

(162) 0x42ac1a MOV	-0x68(%RBP),%RDX

(162) 0x42ac1e MOV	-0x70(%RBP),%RAX

(162) 0x42ac22 INC	%R14D

(162) 0x42ac25 ADD	%RDX,%RSI

(162) 0x42ac28 ADD	%RAX,%RCX

(162) 0x42ac2b CMP	%R14D,-0x40(%RBP)

(162) 0x42ac2f JG	42a9d0

0x42ac35 MOV	-0x80(%RBP),%R13

0x42ac39 KMOVB	%K0,%ECX

0x42ac3d TEST	%CL,%CL

0x42ac3f JE	42ac48

0x42ac41 MOV	%R15D,0xd8(%R13)

0x42ac48 VMOVSD	%XMM2,-0x58(%RBP)

0x42ac4d VMOVSD	%XMM4,-0x50(%RBP)

0x42ac52 VMOVSD	%XMM7,-0x48(%RBP)

0x42ac57 VMOVSD	%XMM8,-0x40(%RBP)

0x42ac5c VMOVSD	%XMM9,-0x38(%RBP)

0x42ac61 CALL	402120 <@plt_start@+0x100>

0x42ac66 MOV	0x50(%R13),%R15

0x42ac6a VMOVSD	-0x38(%RBP),%XMM4

0x42ac6f MOV	0x58(%R13),%RBX

0x42ac73 VADDSD	(%R15),%XMM4,%XMM7

0x42ac78 VMOVSD	-0x40(%RBP),%XMM2

0x42ac7d MOV	0x70(%R13),%RSI

0x42ac81 VMOVSD	%XMM7,(%R15)

0x42ac86 VADDSD	(%RBX),%XMM2,%XMM5

0x42ac8a VMOVSD	-0x58(%RBP),%XMM6

0x42ac8f MOV	0x60(%R13),%RDI

0x42ac93 VMOVSD	%XMM5,(%RBX)

0x42ac97 VADDSD	(%RSI),%XMM6,%XMM9

0x42ac9b VMOVSD	-0x48(%RBP),%XMM8

0x42aca0 MOV	0x68(%R13),%R8

0x42aca4 VMOVSD	%XMM9,(%RSI)

0x42aca8 VADDSD	(%RDI),%XMM8,%XMM10

0x42acac VMOVSD	-0x50(%RBP),%XMM0

0x42acb1 VMOVSD	%XMM10,(%RDI)

0x42acb5 VADDSD	(%R8),%XMM0,%XMM11

0x42acba VMOVSD	%XMM11,(%R8)

0x42acbf ADD	$0x58,%RSP

0x42acc3 POP	%RBX

0x42acc4 POP	%R12

0x42acc6 POP	%R13

0x42acc8 POP	%R14

0x42acca POP	%R15

0x42accc POP	%RBP

0x42accd JMP	402160

(162) 0x42acd2 MOV	-0x38(%RBP),%EDX

(162) 0x42acd5 CMP	%EDX,%R13D

(162) 0x42acd8 JNE	42abf8

(162) 0x42acde MOV	$0x1,%EAX

(162) 0x42ace3 MOV	%R13D,%R15D

(162) 0x42ace6 KMOVB	%EAX,%K0

(162) 0x42acea JMP	42abf8

0x42acef NOP

0x42acf0 VXORPD	%XMM4,%XMM4,%XMM4

0x42acf4 VMOVAPD	%XMM4,%XMM7

0x42acf8 VMOVAPD	%XMM4,%XMM2

0x42acfc VMOVAPD	%XMM4,%XMM8

0x42ad00 VMOVAPD	%XMM4,%XMM9

0x42ad04 JMP	42ac48

0x42ad09 INC	%EAX

0x42ad0b XOR	%EDX,%EDX

0x42ad0d JMP	42a851

0x42ad12 NOPW	%CS:(%RAX,%RAX,1)

0x42ad1d NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module
○97.67	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.33	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:54-71.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.83 to 7.17 cycles (3.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 26.83 to 2.02 cycles (13.26x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 348 bytes (43 double precision FP elements). The binary function is storing 152 bytes (19 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	155
nb uops	161
loop length	654
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.83 cycles
front end	26.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.70	12.00	17.33	17.33	15.00	7.80	7.70	15.00	15.00	15.00	7.80	17.33
cycles	7.70	16.13	17.33	17.33	15.00	7.80	7.70	15.00	15.00	15.00	7.80	17.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	26.83
Dispatch	17.33
DIV/SQRT	6.00
Overall L1	26.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	31%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	18%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	71%

Vector efficiency ratios

INT

all	9%
load	12%
store	10%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	11%
mul	6%
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.83 cycles. At this rate:

6% of peak load performance is reached (12.97 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.66 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 26.83 to 17.33 cycles (1.55x speedup).

ASM code

In the binary file, the address of the function is: 42a810

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x10(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %EBX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 42ad09 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x4f9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%R14D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %EDX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42acf0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x4e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc8(%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%RCX),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R8),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %R14D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (,%RDX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (,%RSI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RCX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RCX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RAX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA 0x1(%R12),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0xc0(%R13),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDI,-0x74(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x40(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0xd0(%R13),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
IMUL %RAX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R9,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDI,%R11,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R10,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%RDX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xa8(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd0(%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (,%RDI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD 0xb0(%R13),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
LEA (%R8,%RDI,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x80(%R13),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
LEA (%RDI,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x88(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RAX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x90(%R13),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RSI,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RAX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x98(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x38(%R13),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD 0xa0(%R13),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VMOVDDUP 0x76dec(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x76df0(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x74(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RAX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
KMOVB %EAX,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVB %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST %CL,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 42ac48 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x438>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,0xd8(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSD %XMM2,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM9,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 402120 <@plt_start@+0x100>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x50(%R13),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x38(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%R13),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDSD (%R15),%XMM4,%XMM7	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD -0x40(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x70(%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM7,(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD (%RBX),%XMM2,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD -0x58(%RBP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x60(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM5,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD (%RSI),%XMM6,%XMM9	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD -0x48(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x68(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM9,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD (%RDI),%XMM8,%XMM10	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD -0x50(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM10,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD (%R8),%XMM0,%XMM11	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM11,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 402160 <@plt_start@+0x140>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 42ac48 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x438>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42a851 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x41>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	field_summary_kernel.f90:54-71
Module	exec

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.83 to 7.17 cycles (3.74x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 3 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/field_summary_kernel.f90:55

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

5 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 5 FP arithmetical operations:

5: addition or subtraction

The binary function is loading 348 bytes (43 double precision FP elements). The binary function is storing 152 bytes (19 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	155
nb uops	161
loop length	654
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	10

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	26.83 cycles
front end	26.83 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	7.70	12.00	17.33	17.33	15.00	7.80	7.70	15.00	15.00	15.00	7.80	17.33
cycles	7.70	16.13	17.33	17.33	15.00	7.80	7.70	15.00	15.00	15.00	7.80	17.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	26.83
Dispatch	17.33
DIV/SQRT	6.00
Overall L1	26.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	31%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	18%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	71%

Vector efficiency ratios

INT

all	9%
load	12%
store	10%
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	16%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	13%
load	12%
store	11%
mul	6%
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	19%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.83 cycles. At this rate:

6% of peak load performance is reached (12.97 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.66 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42a810

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x10(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %EBX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 42ad09 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x4f9>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%R14D	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %EDX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
ADD %R14D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 42acf0 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x4e0>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0xc8(%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R13),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R12D,%R14D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV (%RCX),%EDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R8),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %R14D,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (,%RDX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (,%RSI,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RCX),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RSI,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RCX,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RCX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RAX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA 0x1(%R12),%R9D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R9D,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0xc0(%R13),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x48(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDI,-0x74(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x40(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0xd0(%R13),%R10	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
IMUL %RAX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %R9,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R9,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDI,%R11,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%R10,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RDI,%RDX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xa8(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd0(%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (,%RDI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R8,%RDX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD 0xb0(%R13),%RDI	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
LEA (%R8,%RDI,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x28(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x80(%R13),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
LEA (%RDI,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x88(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RAX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RDX,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%R13),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x90(%R13),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV %RSI,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RAX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x98(%R13),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
LEA (,%RAX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RCX,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x38(%R13),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD 0xa0(%R13),%RAX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
VMOVDDUP 0x76dec(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %R13,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x76df0(%RIP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0x74(%RBP),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RCX,%RAX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
KMOVB %EAX,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x80(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVB %K0,%ECX	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST %CL,%CL	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 42ac48 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x438>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV %R15D,0xd8(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
VMOVSD %XMM2,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM4,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM7,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM8,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM9,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
CALL 402120 <@plt_start@+0x100>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x50(%R13),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD -0x38(%RBP),%XMM4	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x58(%R13),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VADDSD (%R15),%XMM4,%XMM7	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD -0x40(%RBP),%XMM2	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x70(%R13),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM7,(%R15)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD (%RBX),%XMM2,%XMM5	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD -0x58(%RBP),%XMM6	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x60(%R13),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM5,(%RBX)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD (%RSI),%XMM6,%XMM9	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD -0x48(%RBP),%XMM8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x68(%R13),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD %XMM9,(%RSI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD (%RDI),%XMM8,%XMM10	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD -0x50(%RBP),%XMM0	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
VMOVSD %XMM10,(%RDI)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VADDSD (%R8),%XMM0,%XMM11	1	0	0.50	0.33	0.33	0	0.50	0	0	0	0	0	0.33	3	0.50	scal (12.5%)
VMOVSD %XMM11,(%R8)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD $0x58,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 402160 <@plt_start@+0x140>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
VMOVAPD %XMM4,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0-1	0.17	vect (25.0%)
JMP 42ac48 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x438>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 42a851 <__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0+0x41>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼__field_summary_kernel_module_MOD_field_summary_kernel._omp_fn.0–	0.30	0.11
▼Loop 162 - field_summary_kernel.f90:54-71 - exec–	0.00	0.00
○Loop 163 - field_summary_kernel.f90:62-71 - exec	0.30	0.11

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code