OV - exec - Function __calc_dt_kernel_module_MOD_calc_dt_kernel._omp

	Function: __calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0	Module: exec	Source: calc_dt_kernel.f90:89-129	Coverage (incl. loops): 3.43% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90: 89 - 129

--------------------------------------------------------------------------------

89:     !$OMP PARALLEL

90:

91:     !$OMP DO PRIVATE(dsx,dsy,cc,dv1,dv2,div,dtct,dtut,dtvt,dtdivt) REDUCTION(MIN : dt_min_val)

92:     DO k=y_min,y_max

93:     !$OMP SIMD

94:       DO j=x_min,x_max

95:

96:         dsx=celldx(j)

97:         dsy=celldy(k)

98:

99:         cc=soundspeed(j,k)*soundspeed(j,k)

100:         cc=cc+2.0_8*viscosity_a(j,k)/density0(j,k)

101:         cc=MAX(SQRT(cc),g_small)

102:

103:         dtct=dtc_safe*MIN(dsx,dsy)/cc

104:

105:         div=0.0

106:

107:         dv1=(xvel0(j  ,k)+xvel0(j  ,k+1))*xarea(j  ,k)

108:         dv2=(xvel0(j+1,k)+xvel0(j+1,k+1))*xarea(j+1,k)

109:

110:         div=div+dv2-dv1

111:

112:         dtut=dtu_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

113:

114:         dv1=(yvel0(j,k  )+yvel0(j+1,k  ))*yarea(j,k  )

115:         dv2=(yvel0(j,k+1)+yvel0(j+1,k+1))*yarea(j,k+1)

116:

117:         div=div+dv2-dv1

118:

119:         dtvt=dtv_safe*2.0_8*volume(j,k)/MAX(ABS(dv1),ABS(dv2),g_small*volume(j,k))

120:

121:         div=div/(2.0_8*volume(j,k))

122:

123:         IF(div.LT.-g_small)THEN

124:           dtdivt=dtdiv_safe*(-1.0_8/div)

125:         ELSE

126:           dtdivt=g_big

127:         ENDIF

128:

129:         dt_min_val=MIN(dt_min_val,dtct,dtut,dtvt,dtdivt)

0x428ff0 PUSH	%RBP

0x428ff1 MOV	%RSP,%RBP

0x428ff4 PUSH	%R15

0x428ff6 PUSH	%R14

0x428ff8 MOV	%RDI,%R14

0x428ffb PUSH	%R13

0x428ffd PUSH	%R12

0x428fff PUSH	%RBX

0x429000 SUB	$0xc8,%RSP

0x429007 MOV	0x10(%RDI),%RAX

0x42900b MOV	%RDI,-0x70(%RBP)

0x42900f MOV	(%RAX),%R12D

0x429012 CALL	402370 <@plt_start@+0x350>

0x429017 MOV	%EAX,%EBX

0x429019 CALL	4022e0 <@plt_start@+0x2c0>

0x42901e MOV	0x18(%R14),%RDX

0x429022 MOV	%EAX,%ECX

0x429024 MOV	(%RDX),%EAX

0x429026 INC	%EAX

0x429028 SUB	%R12D,%EAX

0x42902b CLTD

0x42902c IDIV	%EBX

0x42902e CMP	%EDX,%ECX

0x429030 JL	4295d1

0x429036 IMUL	%EAX,%ECX

0x429039 VMOVSD	0x78897(%RIP),%XMM9

0x429041 ADD	%ECX,%EDX

0x429043 ADD	%EDX,%EAX

0x429045 CMP	%EAX,%EDX

0x429047 JGE	429598

0x42904d MOV	-0x70(%RBP),%RSI

0x429051 ADD	%R12D,%EDX

0x429054 MOV	0x8(%RSI),%R8

0x429058 MOV	(%RSI),%RDI

0x42905b MOV	0x30(%RSI),%R13

0x42905f ADD	%R12D,%EAX

0x429062 MOV	0x58(%RSI),%R12

0x429066 MOV	%RSI,%RBX

0x429069 MOV	(%R8),%R11D

0x42906c MOV	(%RDI),%R10D

0x42906f MOV	0x38(%RSI),%R15

0x429073 MOV	0x40(%RSI),%RCX

0x429077 MOV	%R13,-0xc8(%RBP)

0x42907e MOV	%R12,-0x60(%RBP)

0x429082 MOV	0xc8(%RBX),%R13

0x429089 MOV	0xd8(%RBX),%R12

0x429090 MOV	0x90(%RSI),%RDI

0x429097 MOV	0x20(%RSI),%R9

0x42909b MOV	0x98(%RSI),%R14

0x4290a2 LEA	0x1(%R11),%R8D

0x4290a6 MOV	%EAX,-0x74(%RBP)

0x4290a9 MOV	%R11D,-0x64(%RBP)

0x4290ad MOV	0x28(%RSI),%RAX

0x4290b1 MOVSXD	%EDX,%R11

0x4290b4 MOV	0x48(%RSI),%RSI

0x4290b8 LEA	(,%R13,8),%RDX

0x4290c0 MOV	%R15,-0xd0(%RBP)

0x4290c7 IMUL	%R11,%R13

0x4290cb MOVSXD	%R10D,%R15

0x4290ce MOV	%RCX,-0xd8(%RBP)

0x4290d5 MOV	%R10D,-0x68(%RBP)

0x4290d9 LEA	(,%R12,8),%RCX

0x4290e1 MOV	0xd0(%RBX),%R10

0x4290e8 MOV	%R9,-0xc0(%RBP)

0x4290ef MOV	%R14,-0x38(%RBP)

0x4290f3 MOV	0x88(%RBX),%R9

0x4290fa MOV	%RSI,-0x48(%RBP)

0x4290fe MOV	%R8D,-0xe4(%RBP)

0x429105 MOV	%RDX,-0x80(%RBP)

0x429109 MOV	%RCX,-0x88(%RBP)

0x429110 MOV	%RAX,-0x40(%RBP)

0x429114 MOV	0xe0(%RBX),%RAX

0x42911b MOV	0xb8(%RBX),%R8

0x429122 ADD	%R15,%R10

0x429125 ADD	%R10,%R13

0x429128 IMUL	%R11,%R12

0x42912c MOV	0xc0(%RBX),%R10

0x429133 LEA	(,%R8,8),%RDX

0x42913b IMUL	%R11,%R8

0x42913f MOV	0x80(%RBX),%RSI

0x429146 ADD	%R15,%RAX

0x429149 ADD	%R15,%R10

0x42914c LEA	(%R9,%R13,8),%R14

0x429150 MOV	0x78(%RBX),%R9

0x429154 ADD	%RAX,%R12

0x429157 ADD	%R10,%R8

0x42915a MOV	0x108(%RBX),%RAX

0x429161 LEA	(%RSI,%R12,8),%R13

0x429165 MOV	%R11,%R10

0x429168 LEA	(%R9,%R8,8),%R12

0x42916c LEA	0x1(%R11),%R8

0x429170 IMUL	%RAX,%R10

0x429174 LEA	(,%RAX,8),%RCX

0x42917c MOV	%RDX,-0x90(%RBP)

0x429183 IMUL	%R8,%RAX

0x429187 MOV	0x110(%RBX),%RDX

0x42918e MOV	0xf8(%RBX),%RSI

0x429195 ADD	%R15,%RDX

0x429198 ADD	%RDX,%RAX

0x42919b MOV	%R8,-0x50(%RBP)

0x42919f LEA	(%RDI,%RAX,8),%R8

0x4291a3 MOV	%R11,%RAX

0x4291a6 IMUL	%RSI,%RAX

0x4291aa MOV	%RCX,-0x98(%RBP)

0x4291b1 MOV	0x100(%RBX),%RCX

0x4291b8 ADD	%RDX,%R10

0x4291bb ADD	%R15,%RCX

0x4291be ADD	%RCX,%RAX

0x4291c1 MOV	0xe8(%RBX),%RCX

0x4291c8 LEA	(%RDI,%R10,8),%R9

0x4291cc LEA	(,%RCX,8),%RDX

0x4291d4 MOV	%RBX,%R10

0x4291d7 IMUL	%R11,%RCX

0x4291db LEA	(,%RSI,8),%RDI

0x4291e3 MOV	0x50(%RBX),%RSI

0x4291e7 MOV	0xf0(%RBX),%RBX

0x4291ee MOV	%RDI,-0xa0(%RBP)

0x4291f5 ADD	%R15,%RBX

0x4291f8 LEA	(%RSI,%RAX,8),%RDI

0x4291fc MOV	0x70(%R10),%RAX

0x429200 MOV	0x128(%R10),%RSI

0x429207 ADD	%RBX,%RCX

0x42920a MOV	%RDX,-0xa8(%RBP)

0x429211 LEA	(%RAX,%RCX,8),%RBX

0x429215 MOV	%R10,%RDX

0x429218 MOV	%R11,%RAX

0x42921b IMUL	%RSI,%RAX

0x42921f MOV	0x130(%RDX),%RCX

0x429226 LEA	(,%RSI,8),%R10

0x42922e ADD	%R15,%RCX

0x429231 MOV	%R10,-0xb0(%RBP)

0x429238 MOV	-0x38(%RBP),%R10

0x42923c ADD	%RCX,%RAX

0x42923f LEA	(%R10,%RAX,8),%RAX

0x429243 MOV	0x118(%RDX),%R10

0x42924a MOV	%R11,-0x58(%RBP)

0x42924e IMUL	%R10,%R11

0x429252 MOV	0x120(%RDX),%RDX

0x429259 MOV	%RAX,-0xf0(%RBP)

0x429260 LEA	(,%R10,8),%RAX

0x429268 ADD	%R15,%RDX

0x42926b MOV	%RAX,-0xb8(%RBP)

0x429272 MOV	%R11,%RAX

0x429275 MOV	-0x60(%RBP),%R11

0x429279 ADD	%RDX,%RAX

0x42927c LEA	(%R11,%RAX,8),%R11

0x429280 MOV	-0x50(%RBP),%RAX

0x429284 IMUL	%RAX,%RSI

0x429288 MOV	%RSI,%RAX

0x42928b MOV	-0x38(%RBP),%RSI

0x42928f ADD	%RCX,%RAX

0x429292 LEA	(%RSI,%RAX,8),%RCX

0x429296 MOV	-0x50(%RBP),%RAX

0x42929a IMUL	%R10,%RAX

0x42929e MOV	-0x60(%RBP),%R10

0x4292a2 MOV	-0x70(%RBP),%RSI

0x4292a6 ADD	%RDX,%RAX

0x4292a9 LEA	(%R10,%RAX,8),%R10

0x4292ad MOV	0xb0(%RSI),%RDX

0x4292b4 MOV	0x68(%RSI),%RAX

0x4292b8 VMOVQ	0x78620(%RIP),%XMM15

0x4292c0 LEA	(%RAX,%RDX,8),%RSI

0x4292c4 MOV	-0x70(%RBP),%RDX

0x4292c8 MOV	%RSI,-0xe0(%RBP)

0x4292cf MOV	0x60(%RDX),%RAX

0x4292d3 MOV	-0x68(%RBP),%ESI

0x4292d6 ADD	0xa8(%RDX),%R15

0x4292dd MOV	-0x64(%RBP),%EDX

0x4292e0 LEA	(%RAX,%R15,8),%R15

0x4292e4 CMP	%EDX,%ESI

0x4292e6 MOV	%ESI,%EDX

0x4292e8 CMOVLE	-0xe4(%RBP),%ESI

0x4292ef XOR	%EAX,%EAX

0x4292f1 MOV	%ESI,-0x60(%RBP)

0x4292f4 MOV	-0x64(%RBP),%ESI

0x4292f7 VMOVQ	0x77e71(%RIP),%XMM5

0x4292ff SUB	%EDX,%ESI

0x429301 MOV	-0x64(%RBP),%EDX

0x429304 MOV	%RSI,-0x38(%RBP)

0x429308 VMOVSD	0x7816e(%RIP),%XMM16

0x429312 MOV	-0xf0(%RBP),%RSI

0x429319 KMOVB	%EAX,%K0

0x42931d CMP	%EDX,-0x68(%RBP)

0x429320 JG	42955a

0x429326 NOPW	%CS:(%RAX,%RAX,1)

  (154) 0x429330 MOV	-0xe0(%RBP),%RAX

  (154) 0x429337 MOV	-0x58(%RBP),%RDX

  (154) 0x42933b VMOVSD	(%R9),%XMM4

  (154) 0x429340 VMOVSD	(%RAX,%RDX,8),%XMM14

  (154) 0x429345 MOV	-0xc0(%RBP),%RAX

  (154) 0x42934c MOV	-0xc8(%RBP),%RDX

  (154) 0x429353 VMOVSD	(%RAX),%XMM8

  (154) 0x429357 VMOVSD	(%RDX),%XMM13

  (154) 0x42935b MOV	-0xd0(%RBP),%RAX

  (154) 0x429362 MOV	-0xd8(%RBP),%RDX

  (154) 0x429369 VADDSD	(%R8),%XMM4,%XMM0

  (154) 0x42936e VMOVSD	(%RAX),%XMM11

  (154) 0x429372 VMOVSD	(%RDX),%XMM10

  (154) 0x429376 VMULSD	(%RDI),%XMM0,%XMM4

  (154) 0x42937a VADDSD	%XMM11,%XMM11,%XMM11

  (154) 0x42937f VADDSD	%XMM10,%XMM10,%XMM10

  (154) 0x429384 VMOVSD	(%RCX),%XMM7

  (154) 0x429388 VMOVSD	(%RSI),%XMM6

  (154) 0x42938c VXORPD	%XMM15,%XMM8,%XMM12

  (154) 0x429391 XOR	%EAX,%EAX

  (154) 0x429393 JMP	4293c5

0x429395 NOPL	(%RAX)

    (155) 0x429398 MOV	-0x40(%RBP),%RDX

    (155) 0x42939c VMOVSD	(%RDX),%XMM29

    (155) 0x4293a2 VMINSD	%XMM21,%XMM29,%XMM30

    (155) 0x4293a8 LEA	0x1(%RAX),%RDX

    (155) 0x4293ac VMINSD	%XMM3,%XMM30,%XMM31

    (155) 0x4293b2 VMINSD	%XMM31,%XMM9,%XMM9

    (155) 0x4293b8 CMP	%RAX,-0x38(%RBP)

    (155) 0x4293bc JE	4294d0

    (155) 0x4293c2 MOV	%RDX,%RAX

    (155) 0x4293c5 VMOVSD	(%R13,%RAX,8),%XMM1

    (155) 0x4293cc VMOVSD	(%RBX,%RAX,8),%XMM18

    (155) 0x4293d3 VADDSD	%XMM1,%XMM1,%XMM3

    (155) 0x4293d7 VMOVAPD	%XMM4,%XMM1

    (155) 0x4293db VMOVSD	0x8(%R8,%RAX,8),%XMM4

    (155) 0x4293e2 VDIVSD	(%R12,%RAX,8),%XMM3,%XMM0

    (155) 0x4293e8 VADDSD	0x8(%R9,%RAX,8),%XMM4,%XMM3

    (155) 0x4293ef VMULSD	%XMM18,%XMM8,%XMM20

    (155) 0x4293f5 VMOVSD	(%R14,%RAX,8),%XMM2

    (155) 0x4293fb VMULSD	0x8(%RDI,%RAX,8),%XMM3,%XMM4

    (155) 0x429401 VFMADD132SD	%XMM2,%XMM0,%XMM2

    (155) 0x429406 VANDPD	%XMM5,%XMM1,%XMM0

    (155) 0x42940a VMAXSD	%XMM20,%XMM0,%XMM0

    (155) 0x429410 VMULSD	%XMM18,%XMM11,%XMM17

    (155) 0x429416 VANDPD	%XMM5,%XMM4,%XMM3

    (155) 0x42941a VMAXSD	%XMM3,%XMM0,%XMM0

    (155) 0x42941e VMOVAPD	%XMM6,%XMM3

    (155) 0x429422 VMOVSD	0x8(%RSI,%RAX,8),%XMM6

    (155) 0x429428 VDIVSD	%XMM0,%XMM17,%XMM21

    (155) 0x42942e VADDSD	%XMM6,%XMM3,%XMM0

    (155) 0x429432 VMOVAPD	%XMM7,%XMM3

    (155) 0x429436 VMOVSD	0x8(%RCX,%RAX,8),%XMM7

    (155) 0x42943c VMULSD	(%R11,%RAX,8),%XMM0,%XMM0

    (155) 0x429442 VADDSD	%XMM7,%XMM3,%XMM3

    (155) 0x429446 VMINSD	(%R15,%RAX,8),%XMM14,%XMM23

    (155) 0x42944d VSQRTSD	%XMM2,%XMM2,%XMM2

    (155) 0x429451 VMULSD	(%R10,%RAX,8),%XMM3,%XMM3

    (155) 0x429457 VSUBSD	%XMM0,%XMM4,%XMM19

    (155) 0x42945d VANDPD	%XMM5,%XMM0,%XMM0

    (155) 0x429461 VADDSD	%XMM18,%XMM18,%XMM25

    (155) 0x429467 VMULSD	%XMM18,%XMM10,%XMM22

    (155) 0x42946d VSUBSD	%XMM1,%XMM3,%XMM1

    (155) 0x429471 VANDPD	%XMM5,%XMM3,%XMM3

    (155) 0x429475 VMAXSD	%XMM0,%XMM3,%XMM3

    (155) 0x429479 VADDSD	%XMM19,%XMM1,%XMM1

    (155) 0x42947f VMULSD	%XMM13,%XMM23,%XMM24

    (155) 0x429485 VMAXSD	%XMM20,%XMM3,%XMM0

    (155) 0x42948b VMAXSD	%XMM2,%XMM8,%XMM2

    (155) 0x42948f VDIVSD	%XMM25,%XMM1,%XMM26

    (155) 0x429495 VDIVSD	%XMM0,%XMM22,%XMM3

    (155) 0x42949b VCOMISD	%XMM26,%XMM12

    (155) 0x4294a1 VDIVSD	%XMM2,%XMM24,%XMM0

    (155) 0x4294a7 VMINSD	%XMM0,%XMM3,%XMM3

    (155) 0x4294ab JBE	429398

    (155) 0x4294b1 VDIVSD	%XMM26,%XMM16,%XMM27

    (155) 0x4294b7 MOV	-0x48(%RBP),%RDX

    (155) 0x4294bb VXORPD	%XMM15,%XMM27,%XMM28

    (155) 0x4294c1 VMULSD	(%RDX),%XMM28,%XMM29

    (155) 0x4294c7 JMP	4293a2

0x4294cc NOPL	(%RAX)

  (154) 0x4294d0 MOV	-0x60(%RBP),%EAX

  (154) 0x4294d3 MOV	$0x1,%EDX

  (154) 0x4294d8 MOV	%EAX,-0x78(%RBP)

  (154) 0x4294db KMOVB	%EDX,%K0

  (154) 0x4294df MOV	-0x50(%RBP),%RAX

  (154) 0x4294e3 MOV	-0x80(%RBP),%RDX

  (154) 0x4294e7 MOV	%RAX,-0x58(%RBP)

  (154) 0x4294eb MOV	-0x88(%RBP),%RAX

  (154) 0x4294f2 ADD	%RDX,%R14

  (154) 0x4294f5 ADD	%RAX,%R13

  (154) 0x4294f8 MOV	-0x98(%RBP),%RAX

  (154) 0x4294ff MOV	-0x90(%RBP),%RDX

  (154) 0x429506 ADD	%RAX,%R9

  (154) 0x429509 ADD	%RAX,%R8

  (154) 0x42950c MOV	-0xa8(%RBP),%RAX

  (154) 0x429513 ADD	%RDX,%R12

  (154) 0x429516 ADD	%RAX,%RBX

  (154) 0x429519 MOV	-0xa0(%RBP),%RDX

  (154) 0x429520 MOV	-0xb8(%RBP),%RAX

  (154) 0x429527 ADD	%RDX,%RDI

  (154) 0x42952a ADD	%RAX,%R11

  (154) 0x42952d MOV	-0xb0(%RBP),%RDX

  (154) 0x429534 ADD	%RAX,%R10

  (154) 0x429537 MOV	-0x50(%RBP),%RAX

  (154) 0x42953b ADD	%RDX,%RSI

  (154) 0x42953e ADD	%RDX,%RCX

  (154) 0x429541 CMP	%EAX,-0x74(%RBP)

  (154) 0x429544 JLE	429580

  (154) 0x429546 LEA	0x1(%RAX),%RDX

  (154) 0x42954a MOV	%RDX,-0x50(%RBP)

  (154) 0x42954e MOV	-0x64(%RBP),%EDX

  (154) 0x429551 CMP	%EDX,-0x68(%RBP)

  (154) 0x429554 JLE	429330

(156) 0x42955a MOV	-0x60(%RBP),%EAX

(156) 0x42955d CMP	%EAX,-0xe4(%RBP)

(156) 0x429563 JNE	4294df

(156) 0x429569 MOV	-0xe4(%RBP),%EDX

(156) 0x42956f MOV	$0x1,%EAX

(156) 0x429574 MOV	%EDX,-0x78(%RBP)

(156) 0x429577 KMOVB	%EAX,%K0

(156) 0x42957b JMP	4294df

0x429580 KMOVB	%K0,%R14D

0x429584 TEST	%R14B,%R14B

0x429587 JE	429598

0x429589 MOV	-0x70(%RBP),%R13

0x42958d MOV	-0x78(%RBP),%R12D

0x429591 MOV	%R12D,0x138(%R13)

0x429598 MOV	-0x70(%RBP),%R9

0x42959c MOV	0xa0(%R9),%RDI

0x4295a3 MOV	(%RDI),%RAX

(153) 0x4295a6 VMOVQ	%RAX,%XMM5

(153) 0x4295ab VMINSD	%XMM5,%XMM9,%XMM8

(153) 0x4295af VMOVQ	%XMM8,%R8

(153) 0x4295b4 LOCK CMPXCHG	%R8,(%RDI)

(153) 0x4295b9 JNE	4295a6

0x4295bb ADD	$0xc8,%RSP

0x4295c2 POP	%RBX

0x4295c3 POP	%R12

0x4295c5 POP	%R13

0x4295c7 POP	%R14

0x4295c9 POP	%R15

0x4295cb POP	%RBP

0x4295cc JMP	402360

0x4295d1 INC	%EAX

0x4295d3 XOR	%EDX,%EDX

0x4295d5 JMP	429036

0x4295da NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
○97.61	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.39	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	calc_dt_kernel.f90:89-129
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:89-129.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 35.50 to 2.83 cycles (12.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 35.50 to 2.52 cycles (14.10x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:91
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:91

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:91

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:91

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 492 bytes. The binary function is storing 200 bytes.

General properties

nb instructions	208
nb uops	213
loop length	914
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	26

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	35.50 cycles
front end	35.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.50	15.00	24.33	24.33	18.00	11.47	11.50	18.00	18.00	18.00	11.53	24.33
cycles	11.50	22.87	24.33	24.33	18.00	11.47	11.50	18.00	18.00	18.00	11.53	24.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	35.50
Dispatch	24.33
DIV/SQRT	6.00
Overall L1	35.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	10%
load	10%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.50 cycles. At this rate:

7% of peak load performance is reached (13.86 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.63 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 35.50 to 24.33 cycles (1.46x speedup).

ASM code

In the binary file, the address of the function is: 428ff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xc8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x10(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RAX),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%R14),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %EBX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 4295d1 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x5e1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSD 0x78897(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 429598 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x5a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x70(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x8(%RSI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R8),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RSI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RSI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd8(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%RSI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RSI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RSI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R11),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,-0x74(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R11D,-0x64(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x28(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EDX,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x48(%RSI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R13,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R11,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %R10D,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %RCX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10D,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (,%R12,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xd0(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8D,-0xe4(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R15,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R10,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R11,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0xc0(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R8,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R11,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x80(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R9,%R13,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x78(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x108(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%R12,8),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R9,%R8,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1(%R11),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (,%RAX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R8,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x110(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf8(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R15,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RAX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RSI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x100(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xe8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%R10,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RCX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R11,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (,%RSI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x50(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RSI,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x128(%R10),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%RCX,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RSI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x130(%RDX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RSI,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R15,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x118(%RDX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R10,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x120(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R10,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R15,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R11,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RSI,%RAX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R10,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x60(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xb0(%RSI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ 0x78620(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RAX,%RDX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0xa8(%RDX),%R15	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV -0x64(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%R15,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVLE -0xe4(%RBP),%ESI	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	1	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x64(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ 0x77e71(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SUB %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x64(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x7816e(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xf0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVB %EAX,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	N/A
CMP %EDX,-0x68(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JG 42955a <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x56a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
KMOVB %K0,%R14D	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST %R14B,%R14B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 429598 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x5a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x70(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12D,0x138(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x70(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa0(%R9),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0xc8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 402360 <@plt_start@+0x340>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 429036 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x46>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	calc_dt_kernel.f90:89-129
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:91
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:91

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:91

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/calc_dt_kernel.f90:91

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 492 bytes. The binary function is storing 200 bytes.

General properties

nb instructions	208
nb uops	213
loop length	914
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	26

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	35.50 cycles
front end	35.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	11.50	15.00	24.33	24.33	18.00	11.47	11.50	18.00	18.00	18.00	11.53	24.33
cycles	11.50	22.87	24.33	24.33	18.00	11.47	11.50	18.00	18.00	18.00	11.53	24.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	35.50
Dispatch	24.33
DIV/SQRT	6.00
Overall L1	35.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	10%
load	10%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 35.50 cycles. At this rate:

7% of peak load performance is reached (13.86 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.63 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 428ff0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
SUB $0xc8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x10(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0x70(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RAX),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%R14),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %EBX	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 4295d1 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x5e1>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
VMOVSD 0x78897(%RIP),%XMM9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 429598 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x5a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x70(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x8(%RSI),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RSI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x30(%RSI),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x58(%RSI),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%R8),%R11D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x38(%RSI),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x40(%RSI),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R13,-0xc8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xd8(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%RSI),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RSI),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RSI),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA 0x1(%R11),%R8D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %EAX,-0x74(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R11D,-0x64(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x28(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOVSXD %EDX,%R11	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV 0x48(%RSI),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R13,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,-0xd0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R11,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOVSXD %R10D,%R15	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %RCX,-0xd8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10D,-0x68(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (,%R12,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xd0(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,-0xc0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x88(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8D,-0xe4(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,-0x88(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R15,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R10,%R13	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
IMUL %R11,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0xc0(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R8,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R11,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x80(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R15,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R9,%R13,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x78(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RAX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x108(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RSI,%R12,8),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R9,%R8,8),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1(%R11),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (,%RAX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,-0x90(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R8,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x110(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf8(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R15,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,-0x50(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RAX,8),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RSI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RCX,-0x98(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x100(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%R10	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R15,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xe8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%R10,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RCX,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RBX,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %R11,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (,%RSI,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x50(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RBX),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,-0xa0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %R15,%RBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RSI,%RAX,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%R10),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x128(%R10),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RBX,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDX,-0xa8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%RCX,8),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RSI,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x130(%RDX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%RSI,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R15,%RCX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R10,-0xb0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%RAX,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x118(%RDX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R10,%R11	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x120(%RDX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,-0xf0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R10,8),%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R15,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RAX,-0xb8(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x60(%RBP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R11,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%RSI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RSI,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RCX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RSI,%RAX,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x50(%RBP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %R10,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV -0x60(%RBP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x70(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%RAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R10,%RAX,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xb0(%RSI),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x68(%RSI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ 0x78620(%RIP),%XMM15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
LEA (%RAX,%RDX,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x70(%RBP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0xe0(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%RDX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x68(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0xa8(%RDX),%R15	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
MOV -0x64(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RAX,%R15,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMOVLE -0xe4(%RBP),%ESI	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	1	0.50	N/A
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %ESI,-0x60(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x64(%RBP),%ESI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVQ 0x77e71(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
SUB %EDX,%ESI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV -0x64(%RBP),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,-0x38(%RBP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VMOVSD 0x7816e(%RIP),%XMM16	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV -0xf0(%RBP),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
KMOVB %EAX,%K0	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	N/A
CMP %EDX,-0x68(%RBP)	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	scal (6.3%)
JG 42955a <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x56a>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
KMOVB %K0,%R14D	1	1	0	0	0	0	0	0	0	0	0	0	0	3	1	N/A
TEST %R14B,%R14B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JE 429598 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x5a8>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV -0x70(%RBP),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV -0x78(%RBP),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12D,0x138(%R13)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV -0x70(%RBP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa0(%R9),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0xc8,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
JMP 402360 <@plt_start@+0x340>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 429036 <__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0+0x46>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
NOPW (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A

Name	Coverage (%)	Time (s)
▼__calc_dt_kernel_module_MOD_calc_dt_kernel._omp_fn.0–	3.43	1.21
○Loop 153 - calc_dt_kernel.f90:91-91 - exec	0.00	0.00
▼Loop 156 - calc_dt_kernel.f90:93-129 - exec–	0.00	0.00
▼Loop 154 - calc_dt_kernel.f90:93-129 - exec–	0.00	0.01
○Loop 155 - calc_dt_kernel.f90:99-129 - exec	3.43	1.21

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