OV - exec - Function __accelerate_kernel_module_MOD_accelerate_kernel._omp

	Function: __accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0	Module: exec	Source: accelerate_kernel.f90:57-76 [...]	Coverage (incl. loops): 5.63% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90: 57 - 76

--------------------------------------------------------------------------------

57:     !$OMP PARALLEL

58:

59:     !$OMP DO PRIVATE(j,k,stepbymass_s)

60:     DO k=y_min,y_max+1

61:     !$OMP SIMD

[...]

67:           *0.25_8)

68:

69:         xvel1(j,k)=xvel0(j,k)-stepbymass_s*(xarea(j  ,k  )*(pressure(j  ,k  )-pressure(j-1,k  ))    &

70:           +xarea(j  ,k-1)*(pressure(j  ,k-1)-pressure(j-1,k-1)))

71:         yvel1(j,k)=yvel0(j,k)-stepbymass_s*(yarea(j  ,k  )*(pressure(j  ,k  )-pressure(j  ,k-1))    &

72:           +yarea(j-1,k  )*(pressure(j-1,k  )-pressure(j-1,k-1)))

73:         xvel1(j,k)=xvel1(j,k)-stepbymass_s*(xarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j-1,k  )) &

74:           +xarea(j  ,k-1)*(viscosity(j  ,k-1)-viscosity(j-1,k-1)))

75:         yvel1(j,k)=yvel1(j,k)-stepbymass_s*(yarea(j  ,k  )*(viscosity(j  ,k  )-viscosity(j  ,k-1)) &

76:           +yarea(j-1,k  )*(viscosity(j-1,k  )-viscosity(j-1,k-1)))

0x4174c0 PUSH	%RBP

0x4174c1 MOV	%RSP,%RBP

0x4174c4 PUSH	%R15

0x4174c6 PUSH	%R14

0x4174c8 PUSH	%R13

0x4174ca PUSH	%R12

0x4174cc PUSH	%RBX

0x4174cd MOV	%RDI,%RBX

0x4174d0 AND	$-0x40,%RSP

0x4174d4 SUB	$0x340,%RSP

0x4174db MOV	0x10(%RDI),%RAX

0x4174df MOV	(%RAX),%R12D

0x4174e2 CALL	402370 <@plt_start@+0x350>

0x4174e7 MOV	%EAX,%R13D

0x4174ea CALL	4022e0 <@plt_start@+0x2c0>

0x4174ef MOV	0x18(%RBX),%RDX

0x4174f3 MOV	%EAX,%ECX

0x4174f5 MOV	(%RDX),%EAX

0x4174f7 ADD	$0x2,%EAX

0x4174fa SUB	%R12D,%EAX

0x4174fd CLTD

0x4174fe IDIV	%R13D

0x417501 CMP	%EDX,%ECX

0x417503 JL	418627

0x417509 IMUL	%EAX,%ECX

0x41750c ADD	%ECX,%EDX

0x41750e ADD	%EDX,%EAX

0x417510 CMP	%EAX,%EDX

0x417512 JGE	418605

0x417518 ADD	%R12D,%EAX

0x41751b MOV	0xa0(%RBX),%R10

0x417522 MOV	%EAX,0x258(%RSP)

0x417529 MOV	0x8(%RBX),%RAX

0x41752d MOV	0x98(%RBX),%RSI

0x417534 MOV	0x88(%RBX),%RDI

0x41753b MOV	(%RBX),%R14

0x41753e MOV	%R10,0x48(%RSP)

0x417543 LEA	(%R12,%RDX,1),%R10D

0x417547 MOV	(%RAX),%EDX

0x417549 MOV	0xb8(%RBX),%RCX

0x417550 MOV	(%R14),%R12D

0x417553 MOV	0xb0(%RBX),%R9

0x41755a MOV	0x90(%RBX),%R11

0x417561 MOV	0x20(%RBX),%R14

0x417565 MOV	%RSI,0x228(%RSP)

0x41756d MOV	%RDI,0x220(%RSP)

0x417575 MOV	0x30(%RBX),%RSI

0x417579 MOV	0x70(%RBX),%RDI

0x41757d MOV	%EDX,0x308(%RSP)

0x417584 ADD	$0x2,%EDX

0x417587 MOV	0xc0(%RBX),%R8

0x41758e MOV	0xa8(%RBX),%R13

0x417595 MOV	0x78(%RBX),%R15

0x417599 VMOVSD	0x80(%RBX),%XMM1

0x4175a1 MOV	%RCX,0x218(%RSP)

0x4175a9 MOV	%R9,0x50(%RSP)

0x4175ae MOV	%R11,0x40(%RSP)

0x4175b3 MOV	0x38(%RBX),%R9

0x4175b7 MOV	0x50(%RBX),%R11

0x4175bb MOV	%RDI,0x210(%RSP)

0x4175c3 MOV	%R10D,0x2c4(%RSP)

0x4175cb MOV	%EDX,0x2c0(%RSP)

0x4175d2 MOV	%RSI,0x278(%RSP)

0x4175da MOV	%R14,0x280(%RSP)

0x4175e2 MOV	0x40(%RBX),%RAX

0x4175e6 MOV	0x58(%RBX),%RSI

0x4175ea MOV	%RAX,0x270(%RSP)

0x4175f2 MOV	0x68(%RBX),%RAX

0x4175f6 MOV	%RSI,0x88(%RSP)

0x4175fe MOV	%RAX,0x138(%RSP)

0x417606 MOVSXD	%R10D,%RAX

0x417609 LEA	(,%RDI,8),%RSI

0x417611 IMUL	%RAX,%RDI

0x417615 MOV	%RSI,0xc8(%RSP)

0x41761d MOVSXD	%R12D,%RSI

0x417620 MOV	%R15,0x70(%RSP)

0x417625 LEA	(%R15,%RSI,1),%R15

0x417629 MOV	%R15,0x148(%RSP)

0x417631 ADD	%RDI,%R15

0x417634 LEA	(,%R15,8),%R10

0x41763c MOV	0x60(%RBX),%RDX

0x417640 MOV	0x28(%RBX),%R14

0x417644 MOV	%R12D,0x25c(%RSP)

0x41764c MOV	%R9,0x288(%RSP)

0x417654 LEA	(%R9,%R10,1),%R12

0x417658 LEA	-0x8(%R9,%R10,1),%R9

0x41765d MOV	0xc8(%RBX),%R10

0x417664 MOV	%RDX,0x140(%RSP)

0x41766c MOV	%R14,0x260(%RSP)

0x417674 MOV	0x48(%RBX),%RDX

0x417678 LEA	(,%R10,8),%R14

0x417680 MOV	%R15,0x1e8(%RSP)

0x417688 MOV	%R10,0xd0(%RSP)

0x417690 MOV	0xd0(%RBX),%R15

0x417697 IMUL	%RAX,%R10

0x41769b MOV	%RDX,0x2c8(%RSP)

0x4176a3 MOV	%R9,0x318(%RSP)

0x4176ab LEA	(%R15,%RSI,1),%RDX

0x4176af LEA	(,%RCX,8),%R9

0x4176b7 IMUL	%RAX,%RCX

0x4176bb MOV	%R12,0x310(%RSP)

0x4176c3 LEA	(%RDX,%R10,1),%R12

0x4176c7 MOV	%R12,0x1d8(%RSP)

0x4176cf MOV	%R11,0x90(%RSP)

0x4176d7 MOV	%R8,0x78(%RSP)

0x4176dc LEA	(%R11,%R12,8),%R11

0x4176e0 LEA	(%R8,%RSI,1),%R12

0x4176e4 MOV	0x280(%RSP),%R8

0x4176ec MOV	%R12,0x150(%RSP)

0x4176f4 ADD	%RCX,%R12

0x4176f7 MOV	%R11,0x320(%RSP)

0x4176ff MOV	%RCX,%R11

0x417702 LEA	(%R8,%R12,8),%RCX

0x417706 MOV	%R14,0xd8(%RSP)

0x41770e MOV	%R9,0xe0(%RSP)

0x417716 MOV	%R12,0x1d0(%RSP)

0x41771e MOV	%RCX,0x328(%RSP)

0x417726 MOV	0xd8(%RBX),%R12

0x41772d MOV	0xe0(%RBX),%RDX

0x417734 LEA	(,%R12,8),%R14

0x41773c MOV	%R12,0xe8(%RSP)

0x417744 IMUL	%RAX,%R12

0x417748 MOV	0x140(%RSP),%R9

0x417750 ADD	%RSI,%RDX

0x417753 LEA	(%RDX,%R12,1),%R8

0x417757 LEA	(%R9,%R8,8),%RCX

0x41775b MOV	%RCX,0x208(%RSP)

0x417763 MOV	0xf8(%RBX),%RCX

0x41776a MOV	0x100(%RBX),%RDX

0x417771 MOV	%R14,0xf0(%RSP)

0x417779 MOV	%RCX,0xf8(%RSP)

0x417781 LEA	(,%RCX,8),%R14

0x417789 IMUL	%RAX,%RCX

0x41778d MOV	0x88(%RSP),%R9

0x417795 ADD	%RSI,%RDX

0x417798 MOV	%R8,0x1c0(%RSP)

0x4177a0 LEA	(%RDX,%RCX,1),%R8

0x4177a4 MOV	%R14,0x100(%RSP)

0x4177ac MOV	%R8,0x1b8(%RSP)

0x4177b4 LEA	(%R9,%R8,8),%R14

0x4177b8 MOV	0x108(%RBX),%R8

0x4177bf MOV	0x110(%RBX),%R9

0x4177c6 LEA	(,%R8,8),%RDX

0x4177ce MOV	%R8,0x108(%RSP)

0x4177d6 IMUL	%RAX,%R8

0x4177da MOV	%R14,0x330(%RSP)

0x4177e2 MOV	%RDX,0xc0(%RSP)

0x4177ea LEA	(%RSI,%R9,1),%R14

0x4177ee MOV	0x138(%RSP),%RDX

0x4177f6 ADD	%R8,%R14

0x4177f9 MOV	%R14,0x1a8(%RSP)

0x417801 LEA	(%RDX,%R14,8),%R14

0x417805 MOV	0x70(%RSP),%RDX

0x41780a LEA	(%R15,%R10,1),%R10

0x41780e ADD	%RDI,%RDX

0x417811 MOV	0x90(%RSP),%R15

0x417819 MOV	0x288(%RSP),%RDI

0x417821 MOV	%R14,0x338(%RSP)

0x417829 LEA	(%RDI,%RDX,8),%R14

0x41782d LEA	(%R15,%R10,8),%RDX

0x417831 MOV	0x78(%RSP),%RDI

0x417836 MOV	0x220(%RSP),%R15

0x41783e LEA	(%RDI,%R11,1),%R11

0x417842 MOV	%R14,0x198(%RSP)

0x41784a MOV	%R15,%RDI

0x41784d MOV	0x280(%RSP),%R14

0x417855 IMUL	%RAX,%RDI

0x417859 LEA	(%R14,%R11,8),%R10

0x41785d MOV	0x40(%RSP),%R11

0x417862 MOV	%RDX,0x2b8(%RSP)

0x41786a LEA	(%RDI,%R11,1),%RDX

0x41786e MOV	%R13,0x268(%RSP)

0x417876 MOV	%R10,0x2b0(%RSP)

0x41787e MOV	%RDX,0x190(%RSP)

0x417886 MOV	0x270(%RSP),%R10

0x41788e LEA	(,%R15,8),%R14

0x417896 LEA	(%R10,%RDX,8),%R15

0x41789a MOV	0xe0(%RBX),%RDX

0x4178a1 MOV	0xe8(%RBX),%R10

0x4178a8 ADD	0x100(%RBX),%RCX

0x4178af ADD	%R12,%RDX

0x4178b2 LEA	(%R8,%R9,1),%R8

0x4178b6 MOV	%RCX,%R12

0x4178b9 MOV	0x228(%RSP),%R9

0x4178c1 MOV	0x88(%RSP),%RCX

0x4178c9 MOV	%RDX,0x188(%RSP)

0x4178d1 MOV	%R10,%RDX

0x4178d4 IMUL	%RAX,%RDX

0x4178d8 IMUL	%RAX,%R13

0x4178dc MOV	%R14,0xb8(%RSP)

0x4178e4 IMUL	%R9,%RAX

0x4178e8 LEA	(%RCX,%R12,8),%R14

0x4178ec MOV	%R15,0x2a8(%RSP)

0x4178f4 MOV	0x48(%RSP),%RCX

0x4178f9 MOV	0xf0(%RBX),%R12

0x417900 LEA	(,%R10,8),%R15

0x417908 MOV	%R10,0xb0(%RSP)

0x417910 LEA	(,%R9,8),%R10

0x417918 MOV	0x50(%RSP),%R9

0x41791d LEA	(%RDX,%R12,1),%RBX

0x417921 ADD	%RSI,%R11

0x417924 MOV	%R8,0x178(%RSP)

0x41792c ADD	%RSI,%R12

0x41792f LEA	(%RSI,%R9,1),%R8

0x417933 LEA	(%RSI,%RCX,1),%RSI

0x417937 ADD	%R11,%RDI

0x41793a MOV	%R14,0x2a0(%RSP)

0x417942 MOV	%RBX,0x180(%RSP)

0x41794a LEA	(%RAX,%RCX,1),%R14

0x41794e MOV	0x2c8(%RSP),%RBX

0x417956 MOV	%RSI,0x168(%RSP)

0x41795e ADD	%RAX,%RSI

0x417961 MOV	0x268(%RSP),%RAX

0x417969 ADD	%RDX,%R12

0x41796c MOV	%RDI,0x1c8(%RSP)

0x417974 SAL	$0x3,%RDI

0x417978 MOV	%R15,0xa0(%RSP)

0x417980 MOV	%R8,0x158(%RSP)

0x417988 LEA	(%RBX,%R14,8),%R15

0x41798c ADD	%R13,%R8

0x41798f MOV	%R11,0x160(%RSP)

0x417997 MOV	%RDI,0x1f0(%RSP)

0x41799f LEA	(,%RAX,8),%R11

0x4179a7 LEA	(,%R12,8),%RDI

0x4179af LEA	(,%RSI,8),%RDX

0x4179b7 MOV	%R14,0x170(%RSP)

0x4179bf MOV	%R10,0x98(%RSP)

0x4179c7 MOV	%R15,0x298(%RSP)

0x4179cf MOV	%R12,0x1b0(%RSP)

0x4179d7 MOV	%R8,0x1e0(%RSP)

0x4179df MOV	%RSI,0x1a0(%RSP)

0x4179e7 MOV	%R11,0xa8(%RSP)

0x4179ef MOV	%RDI,0x200(%RSP)

0x4179f7 MOV	%RDX,0x1f8(%RSP)

0x4179ff MOV	0x308(%RSP),%EAX

0x417a06 MOV	0x25c(%RSP),%R10D

0x417a0e MOV	0x278(%RSP),%R12

0x417a16 SUB	%R10D,%EAX

0x417a19 LEA	0x2(%RAX),%EBX

0x417a1c LEA	(%R13,%R9,1),%R13

0x417a21 MOV	%EBX,%R9D

0x417a24 LEA	(%R12,%R8,8),%RCX

0x417a28 SHR	$0x3,%R9D

0x417a2c MOV	%EAX,0x5c(%RSP)

0x417a30 LEA	(%R12,%R13,8),%R14

0x417a34 INC	%EAX

0x417a36 LEA	-0x8(%RCX),%R15

0x417a3a SAL	$0x6,%R9

0x417a3e VMOVSD	0x89d42(%RIP),%XMM5

0x417a46 MOV	%RCX,0x68(%RSP)

0x417a4b MOV	%R14,0x38(%RSP)

0x417a50 MOVQ	$0,0x290(%RSP)

0x417a5c MOV	%EBX,0x80(%RSP)

0x417a63 MOV	%EAX,0x84(%RSP)

0x417a6a MOV	%R15,0x60(%RSP)

0x417a6f MOV	%R9,0x2d0(%RSP)

0x417a77 VBROADCASTSD	%XMM1,%YMM7

0x417a7c VBROADCASTSD	%XMM5,%YMM6

0x417a81 NOPL	(%RAX)

(63) 0x417a88 MOV	0x2c0(%RSP),%R8D

(63) 0x417a90 CMP	%R8D,0x25c(%RSP)

(63) 0x417a98 JGE	418447

(63) 0x417a9e MOV	0x2c4(%RSP),%EAX

(63) 0x417aa5 MOV	0x228(%RSP),%RDX

(63) 0x417aad DEC	%EAX

(63) 0x417aaf MOV	0x210(%RSP),%R11

(63) 0x417ab7 MOV	0x268(%RSP),%RSI

(63) 0x417abf MOV	0x218(%RSP),%RDI

(63) 0x417ac7 MOV	0x220(%RSP),%RCX

(63) 0x417acf CLTQ

(63) 0x417ad1 IMUL	%RAX,%R11

(63) 0x417ad5 IMUL	%RAX,%RSI

(63) 0x417ad9 IMUL	%RAX,%RDI

(63) 0x417add IMUL	%RAX,%RCX

(63) 0x417ae1 IMUL	%RDX,%RAX

(63) 0x417ae5 CMPL	$0x6,0x84(%RSP)

(63) 0x417aed MOV	%R11,0x250(%RSP)

(63) 0x417af5 MOV	%RSI,0x248(%RSP)

(63) 0x417afd MOV	%RDI,0x240(%RSP)

(63) 0x417b05 MOV	%RCX,0x238(%RSP)

(63) 0x417b0d MOV	%RAX,0x230(%RSP)

(63) 0x417b15 MOV	%RAX,%RDX

(63) 0x417b18 JBE	418618

(63) 0x417b1e MOV	0x158(%RSP),%RBX

(63) 0x417b26 MOV	0x148(%RSP),%R12

(63) 0x417b2e MOV	0x278(%RSP),%R8

(63) 0x417b36 LEA	(%RSI,%RBX,1),%R15

(63) 0x417b3a MOV	0x150(%RSP),%RBX

(63) 0x417b42 MOV	0x288(%RSP),%R13

(63) 0x417b4a MOV	0x290(%RSP),%R14

(63) 0x417b52 SAL	$0x3,%R15

(63) 0x417b56 ADD	%R11,%R12

(63) 0x417b59 MOV	0x68(%RSP),%RSI

(63) 0x417b5e LEA	-0x8(%R8,%R15,1),%R9

(63) 0x417b63 LEA	(%R8,%R15,1),%R11

(63) 0x417b67 ADD	%RDI,%RBX

(63) 0x417b6a MOV	0x60(%RSP),%RAX

(63) 0x417b6f MOV	0x280(%RSP),%RDI

(63) 0x417b77 SAL	$0x3,%R12

(63) 0x417b7b MOV	0x160(%RSP),%R8

(63) 0x417b83 LEA	-0x8(%R13,%R12,1),%R10

(63) 0x417b88 ADD	%R14,%RSI

(63) 0x417b8b ADD	%R13,%R12

(63) 0x417b8e LEA	(%RAX,%R14,1),%R15

(63) 0x417b92 ADD	%RCX,%R8

(63) 0x417b95 MOV	0x1f8(%RSP),%RAX

(63) 0x417b9d MOV	0x200(%RSP),%RCX

(63) 0x417ba5 LEA	(%RDI,%RBX,8),%R14

(63) 0x417ba9 MOV	%R10,0x308(%RSP)

(63) 0x417bb1 MOV	0x2c8(%RSP),%RBX

(63) 0x417bb9 MOV	0x270(%RSP),%R10

(63) 0x417bc1 MOV	%R12,0x2f8(%RSP)

(63) 0x417bc9 MOV	%RSI,0x2e8(%RSP)

(63) 0x417bd1 MOV	0x1f0(%RSP),%R12

(63) 0x417bd9 MOV	0x260(%RSP),%RSI

(63) 0x417be1 SAL	$0x3,%R8

(63) 0x417be5 LEA	(%R10,%R12,1),%R13

(63) 0x417be9 LEA	(%RAX,%RBX,1),%RDI

(63) 0x417bed MOV	%R9,0x300(%RSP)

(63) 0x417bf5 MOV	%R11,0x2f0(%RSP)

(63) 0x417bfd LEA	(%RCX,%RSI,1),%R9

(63) 0x417c01 LEA	(%R10,%R8,1),%R11

(63) 0x417c05 LEA	-0x8(%R10,%R12,1),%R12

(63) 0x417c0a LEA	-0x8(%R10,%R8,1),%R10

(63) 0x417c0f LEA	-0x8(%RSI,%RCX,1),%R8

(63) 0x417c14 LEA	-0x8(%RBX,%RAX,1),%RSI

(63) 0x417c19 MOV	0x168(%RSP),%RAX

(63) 0x417c21 MOV	%R15,0x2e0(%RSP)

(63) 0x417c29 ADD	%RDX,%RAX

(63) 0x417c2c SAL	$0x3,%RAX

(63) 0x417c30 LEA	(%RBX,%RAX,1),%RCX

(63) 0x417c34 LEA	-0x8(%RBX,%RAX,1),%RDX

(63) 0x417c39 MOV	%RDX,0x2d8(%RSP)

(63) 0x417c41 MOV	0x338(%RSP),%RBX

(63) 0x417c49 MOV	%RCX,0x338(%RSP)

(63) 0x417c51 VBROADCASTSD	0x89b2d(%RIP),%ZMM3

(63) 0x417c5b MOV	0x208(%RSP),%R15

(63) 0x417c63 VBROADCASTSD	%XMM1,%ZMM4

(63) 0x417c69 XOR	%EAX,%EAX

(63) 0x417c6b NOPL	(%RAX,%RAX,1)

  (65) 0x417c70 MOV	0x2f0(%RSP),%RCX

  (65) 0x417c78 MOV	0x2f8(%RSP),%RDX

  (65) 0x417c80 VMOVUPD	(%RCX,%RAX,1),%ZMM0

  (65) 0x417c87 MOV	0x300(%RSP),%RCX

  (65) 0x417c8f VMULPD	(%RDX,%RAX,1),%ZMM0,%ZMM9

  (65) 0x417c96 MOV	0x308(%RSP),%RDX

  (65) 0x417c9e VMOVUPD	(%R13,%RAX,1),%ZMM15

  (65) 0x417ca6 VMOVUPD	(%RDX,%RAX,1),%ZMM2

  (65) 0x417cad MOV	0x2e0(%RSP),%RDX

  (65) 0x417cb5 VFMADD231PD	(%RCX,%RAX,1),%ZMM2,%ZMM9

  (65) 0x417cbc VMOVUPD	(%RDX,%RAX,1),%ZMM8

  (65) 0x417cc3 MOV	0x318(%RSP),%RCX

  (65) 0x417ccb MOV	0x2e8(%RSP),%RDX

  (65) 0x417cd3 VMULPD	(%RCX,%RAX,1),%ZMM8,%ZMM10

  (65) 0x417cda MOV	0x310(%RSP),%RCX

  (65) 0x417ce2 VSUBPD	(%R12,%RAX,1),%ZMM15,%ZMM0

  (65) 0x417ce9 VMOVUPD	(%RCX,%RAX,1),%ZMM11

  (65) 0x417cf0 MOV	0x320(%RSP),%RCX

  (65) 0x417cf8 VFMADD231PD	(%RDX,%RAX,1),%ZMM11,%ZMM10

  (65) 0x417cff MOV	0x328(%RSP),%RDX

  (65) 0x417d07 VADDPD	%ZMM10,%ZMM9,%ZMM12

  (65) 0x417d0d VMOVUPD	(%R11,%RAX,1),%ZMM9

  (65) 0x417d14 VSUBPD	(%R10,%RAX,1),%ZMM9,%ZMM2

  (65) 0x417d1b VMULPD	%ZMM3,%ZMM12,%ZMM13

  (65) 0x417d21 VMULPD	(%R14,%RAX,1),%ZMM2,%ZMM8

  (65) 0x417d28 VDIVPD	%ZMM13,%ZMM4,%ZMM14

  (65) 0x417d2e VFMADD231PD	(%RDX,%RAX,1),%ZMM0,%ZMM8

  (65) 0x417d35 VFNMADD213PD	(%RCX,%RAX,1),%ZMM14,%ZMM8

  (65) 0x417d3c VMOVUPD	%ZMM8,(%R15,%RAX,1)

  (65) 0x417d43 VMOVUPD	(%R12,%RAX,1),%ZMM12

  (65) 0x417d4a VMOVUPD	(%R13,%RAX,1),%ZMM10

  (65) 0x417d52 VSUBPD	(%R10,%RAX,1),%ZMM12,%ZMM13

  (65) 0x417d59 VSUBPD	(%R11,%RAX,1),%ZMM10,%ZMM11

  (65) 0x417d60 VMULPD	(%R8,%RAX,1),%ZMM13,%ZMM15

  (65) 0x417d67 VFMADD231PD	(%R9,%RAX,1),%ZMM11,%ZMM15

  (65) 0x417d6e MOV	0x330(%RSP),%RCX

  (65) 0x417d76 VFNMADD213PD	(%RCX,%RAX,1),%ZMM14,%ZMM15

  (65) 0x417d7d MOV	0x338(%RSP),%RCX

  (65) 0x417d85 VMOVUPD	%ZMM15,(%RBX,%RAX,1)

  (65) 0x417d8c VMOVUPD	(%RCX,%RAX,1),%ZMM2

  (65) 0x417d93 MOV	0x2d8(%RSP),%RCX

  (65) 0x417d9b VMOVUPD	(%RDI,%RAX,1),%ZMM0

  (65) 0x417da2 VSUBPD	(%RCX,%RAX,1),%ZMM2,%ZMM8

  (65) 0x417da9 VSUBPD	(%RSI,%RAX,1),%ZMM0,%ZMM9

  (65) 0x417db0 VMULPD	(%R14,%RAX,1),%ZMM8,%ZMM10

  (65) 0x417db7 VFMADD231PD	(%RDX,%RAX,1),%ZMM9,%ZMM10

  (65) 0x417dbe MOV	0x338(%RSP),%RDX

  (65) 0x417dc6 VFNMADD213PD	(%R15,%RAX,1),%ZMM14,%ZMM10

  (65) 0x417dcd VMOVUPD	%ZMM10,(%R15,%RAX,1)

  (65) 0x417dd4 VMOVUPD	(%RSI,%RAX,1),%ZMM13

  (65) 0x417ddb VMOVUPD	(%RDI,%RAX,1),%ZMM11

  (65) 0x417de2 VSUBPD	(%RCX,%RAX,1),%ZMM13,%ZMM15

  (65) 0x417de9 VSUBPD	(%RDX,%RAX,1),%ZMM11,%ZMM12

  (65) 0x417df0 VMULPD	(%R8,%RAX,1),%ZMM15,%ZMM0

  (65) 0x417df7 VFMADD231PD	(%R9,%RAX,1),%ZMM12,%ZMM0

  (65) 0x417dfe VFNMADD213PD	(%RBX,%RAX,1),%ZMM0,%ZMM14

  (65) 0x417e05 VMOVUPD	%ZMM14,(%RBX,%RAX,1)

  (65) 0x417e0c ADD	$0x40,%RAX

  (65) 0x417e10 CMP	%RAX,0x2d0(%RSP)

  (65) 0x417e18 JNE	417c70

(63) 0x417e1e MOV	0x80(%RSP),%R13D

(63) 0x417e26 MOV	0x25c(%RSP),%R12D

(63) 0x417e2e MOV	%R13D,%EAX

(63) 0x417e31 AND	$-0x8,%EAX

(63) 0x417e34 AND	$0x7,%R13D

(63) 0x417e38 MOV	%RBX,0x338(%RSP)

(63) 0x417e40 LEA	(%RAX,%R12,1),%R14D

(63) 0x417e44 JE	418447

(63) 0x417e4a MOV	0x5c(%RSP),%R11D

(63) 0x417e4f SUB	%EAX,%R11D

(63) 0x417e52 LEA	0x2(%R11),%R10D

(63) 0x417e56 INC	%R11D

(63) 0x417e59 MOV	%R10D,0x300(%RSP)

(63) 0x417e61 CMP	$0x2,%R11D

(63) 0x417e65 JBE	4181a1

(63) 0x417e6b MOV	0x248(%RSP),%RBX

(63) 0x417e73 MOV	0x158(%RSP),%R15

(63) 0x417e7b MOV	0x250(%RSP),%R9

(63) 0x417e83 LEA	(%RBX,%R15,1),%RCX

(63) 0x417e87 MOV	0x148(%RSP),%R8

(63) 0x417e8f LEA	(%RCX,%RAX,1),%RDX

(63) 0x417e93 LEA	(%R9,%R8,1),%RDI

(63) 0x417e97 MOV	%RDX,0x120(%RSP)

(63) 0x417e9f MOV	0x240(%RSP),%RCX

(63) 0x417ea7 MOV	0x150(%RSP),%RDX

(63) 0x417eaf LEA	(%RDI,%RAX,1),%RSI

(63) 0x417eb3 MOV	0x1d0(%RSP),%R10

(63) 0x417ebb MOV	0x1e0(%RSP),%R13

(63) 0x417ec3 ADD	%RDX,%RCX

(63) 0x417ec6 MOV	%RSI,0x128(%RSP)

(63) 0x417ece MOV	0x280(%RSP),%RSI

(63) 0x417ed6 LEA	(%RAX,%R10,1),%R9

(63) 0x417eda ADD	%RAX,%RCX

(63) 0x417edd LEA	(%RAX,%R13,1),%R12

(63) 0x417ee1 LEA	(%RSI,%R9,8),%RDI

(63) 0x417ee5 LEA	(%RSI,%RCX,8),%R13

(63) 0x417ee9 MOV	0x160(%RSP),%R10

(63) 0x417ef1 MOV	0x238(%RSP),%RSI

(63) 0x417ef9 MOV	0x1c8(%RSP),%RBX

(63) 0x417f01 ADD	%R10,%RSI

(63) 0x417f04 MOV	0x1d8(%RSP),%R11

(63) 0x417f0c MOV	0x270(%RSP),%R15

(63) 0x417f14 ADD	%RAX,%RBX

(63) 0x417f17 ADD	%RAX,%RSI

(63) 0x417f1a ADD	%RAX,%R11

(63) 0x417f1d SAL	$0x3,%RBX

(63) 0x417f21 SAL	$0x3,%RSI

(63) 0x417f25 MOV	%R13,0x2f0(%RSP)

(63) 0x417f2d MOV	0x1b8(%RSP),%RDX

(63) 0x417f35 MOV	0x1b0(%RSP),%R13

(63) 0x417f3d LEA	-0x8(%R15,%RBX,1),%R9

(63) 0x417f42 MOV	%R11,0x118(%RSP)

(63) 0x417f4a MOV	%RDI,0x2f8(%RSP)

(63) 0x417f52 LEA	(%R15,%RBX,1),%R11

(63) 0x417f56 LEA	-0x8(%R15,%RSI,1),%RDI

(63) 0x417f5b MOV	0x1c0(%RSP),%RBX

(63) 0x417f63 LEA	(%R15,%RSI,1),%R10

(63) 0x417f67 ADD	%RAX,%RDX

(63) 0x417f6a MOV	0x140(%RSP),%R15

(63) 0x417f72 LEA	(%RAX,%R13,1),%RSI

(63) 0x417f76 MOV	%RDI,0x2e8(%RSP)

(63) 0x417f7e MOV	0x260(%RSP),%RDI

(63) 0x417f86 ADD	%RAX,%RBX

(63) 0x417f89 SAL	$0x3,%RSI

(63) 0x417f8d MOV	%RDX,0x110(%RSP)

(63) 0x417f95 MOV	0x1a8(%RSP),%RDX

(63) 0x417f9d LEA	(%R15,%RBX,8),%RCX

(63) 0x417fa1 MOV	0x138(%RSP),%R13

(63) 0x417fa9 LEA	(%RDI,%RSI,1),%R15

(63) 0x417fad LEA	-0x8(%RDI,%RSI,1),%RBX

(63) 0x417fb2 MOV	0x1a0(%RSP),%RDI

(63) 0x417fba LEA	(%RAX,%RDX,1),%RSI

(63) 0x417fbe LEA	(%R13,%RSI,8),%RDX

(63) 0x417fc3 MOV	%RBX,0x2e0(%RSP)

(63) 0x417fcb MOV	0x2c8(%RSP),%RSI

(63) 0x417fd3 LEA	(%RAX,%RDI,1),%RBX

(63) 0x417fd7 SAL	$0x3,%RBX

(63) 0x417fdb LEA	-0x8(%RSI,%RBX,1),%R13

(63) 0x417fe0 LEA	(%RSI,%RBX,1),%RDI

(63) 0x417fe4 MOV	0x1e8(%RSP),%R8

(63) 0x417fec MOV	%R13,0x2d8(%RSP)

(63) 0x417ff4 MOV	0x168(%RSP),%RBX

(63) 0x417ffc MOV	0x230(%RSP),%RSI

(63) 0x418004 ADD	%RAX,%R8

(63) 0x418007 ADD	%RBX,%RSI

(63) 0x41800a ADD	%RSI,%RAX

(63) 0x41800d MOV	0x2c8(%RSP),%RSI

(63) 0x418015 MOV	%R8,0x308(%RSP)

(63) 0x41801d MOV	0x278(%RSP),%RBX

(63) 0x418025 SAL	$0x3,%RAX

(63) 0x418029 MOV	%RSI,%R13

(63) 0x41802c ADD	%RAX,%R13

(63) 0x41802f LEA	-0x8(%RSI,%RAX,1),%RAX

(63) 0x418034 VMOVUPD	(%RBX,%R12,8),%YMM4

(63) 0x41803a VMOVUPD	-0x8(%RBX,%R12,8),%YMM9

(63) 0x418041 MOV	%RAX,0x130(%RSP)

(63) 0x418049 MOV	0x308(%RSP),%R12

(63) 0x418051 MOV	0x288(%RSP),%RAX

(63) 0x418059 MOV	0x128(%RSP),%RSI

(63) 0x418061 VMULPD	(%RAX,%R8,8),%YMM4,%YMM3

(63) 0x418067 VMULPD	-0x8(%RAX,%R12,8),%YMM9,%YMM2

(63) 0x41806e VMOVUPD	(%RAX,%RSI,8),%YMM14

(63) 0x418073 VMOVUPD	-0x8(%RAX,%RSI,8),%YMM8

(63) 0x418079 MOV	0x120(%RSP),%R8

(63) 0x418081 VMOVUPD	(%R10),%YMM0

(63) 0x418086 VFMADD231PD	(%RBX,%R8,8),%YMM14,%YMM3

(63) 0x41808c VFMADD231PD	-0x8(%RBX,%R8,8),%YMM8,%YMM2

(63) 0x418093 MOV	0x2e8(%RSP),%RBX

(63) 0x41809b MOV	0x2f0(%RSP),%RSI

(63) 0x4180a3 VSUBPD	(%RBX),%YMM0,%YMM4

(63) 0x4180a7 VMOVUPD	(%R11),%YMM13

(63) 0x4180ac VADDPD	%YMM2,%YMM3,%YMM10

(63) 0x4180b0 VMULPD	(%RSI),%YMM4,%YMM3

(63) 0x4180b4 VSUBPD	(%R9),%YMM13,%YMM15

(63) 0x4180b9 VMULPD	%YMM6,%YMM10,%YMM11

(63) 0x4180bd MOV	0x2f8(%RSP),%RAX

(63) 0x4180c5 MOV	0x90(%RSP),%R12

(63) 0x4180cd VFMADD132PD	(%RAX),%YMM3,%YMM15

(63) 0x4180d2 MOV	0x118(%RSP),%R8

(63) 0x4180da VDIVPD	%YMM11,%YMM7,%YMM12

(63) 0x4180df VFNMADD213PD	(%R12,%R8,8),%YMM12,%YMM15

(63) 0x4180e5 VMOVUPD	%YMM15,(%RCX)

(63) 0x4180e9 VMOVUPD	(%R11),%YMM14

(63) 0x4180ee VSUBPD	(%R10),%YMM14,%YMM9

(63) 0x4180f3 VMOVUPD	(%R9),%YMM2

(63) 0x4180f8 MOV	0x2e0(%RSP),%R11

(63) 0x418100 VSUBPD	(%RBX),%YMM2,%YMM8

(63) 0x418104 MOV	0x88(%RSP),%R10

(63) 0x41810c MOV	0x110(%RSP),%R9

(63) 0x418114 VMULPD	(%R11),%YMM8,%YMM10

(63) 0x418119 MOV	0x130(%RSP),%R8

(63) 0x418121 MOV	0x2d8(%RSP),%R12

(63) 0x418129 VFMADD132PD	(%R15),%YMM10,%YMM9

(63) 0x41812e VFNMADD213PD	(%R10,%R9,8),%YMM12,%YMM9

(63) 0x418134 VMOVUPD	%YMM9,(%RDX)

(63) 0x418138 VMOVUPD	(%R13),%YMM15

(63) 0x41813e VMOVUPD	(%RDI),%YMM11

(63) 0x418142 VSUBPD	(%R8),%YMM15,%YMM0

(63) 0x418147 VSUBPD	(%R12),%YMM11,%YMM13

(63) 0x41814d VMULPD	(%RSI),%YMM0,%YMM4

(63) 0x418151 VFMADD132PD	(%RAX),%YMM4,%YMM13

(63) 0x418156 VFNMADD213PD	(%RCX),%YMM12,%YMM13

(63) 0x41815b VMOVUPD	%YMM13,(%RCX)

(63) 0x41815f VMOVUPD	(%R12),%YMM9

(63) 0x418165 VMOVUPD	(%RDI),%YMM3

(63) 0x418169 VSUBPD	(%R8),%YMM9,%YMM2

(63) 0x41816e VSUBPD	(%R13),%YMM3,%YMM14

(63) 0x418174 MOV	0x300(%RSP),%ECX

(63) 0x41817b VMULPD	(%R11),%YMM2,%YMM8

(63) 0x418180 VFMADD132PD	(%R15),%YMM8,%YMM14

(63) 0x418185 MOV	%ECX,%R15D

(63) 0x418188 AND	$-0x4,%R15D

(63) 0x41818c ADD	%R15D,%R14D

(63) 0x41818f AND	$0x3,%ECX

(63) 0x418192 VFNMADD213PD	(%RDX),%YMM14,%YMM12

(63) 0x418197 VMOVUPD	%YMM12,(%RDX)

(63) 0x41819b JE	418447

(63) 0x4181a1 MOVSXD	%R14D,%RAX

(63) 0x4181a4 MOV	0x178(%RSP),%R13

(63) 0x4181ac MOV	0x188(%RSP),%R14

(63) 0x4181b4 MOV	0x140(%RSP),%RDI

(63) 0x4181bc MOV	0x138(%RSP),%RSI

(63) 0x4181c4 MOV	0x40(%RSP),%R12

(63) 0x4181c9 MOV	0x238(%RSP),%R15

(63) 0x4181d1 LEA	(%RAX,%R14,1),%RDX

(63) 0x4181d5 LEA	(%RAX,%R13,1),%RBX

(63) 0x4181d9 MOV	0x190(%RSP),%R10

(63) 0x4181e1 MOV	0x180(%RSP),%R14

(63) 0x4181e9 LEA	(%RSI,%RBX,8),%R11

(63) 0x4181ed ADD	%R12,%R15

(63) 0x4181f0 MOV	0x270(%RSP),%RBX

(63) 0x4181f8 LEA	(%RDI,%RDX,8),%RCX

(63) 0x4181fc MOV	0x260(%RSP),%RDX

(63) 0x418204 LEA	(%R15,%RAX,1),%R8

(63) 0x418208 LEA	(%RAX,%R10,1),%R9

(63) 0x41820c ADD	%RAX,%R14

(63) 0x41820f MOV	0x48(%RSP),%RSI

(63) 0x418214 LEA	(%RBX,%R9,8),%R10

(63) 0x418218 LEA	(%RBX,%R8,8),%R9

(63) 0x41821c LEA	(%RDX,%R14,8),%R8

(63) 0x418220 MOV	0x230(%RSP),%R14

(63) 0x418228 MOV	0x2c8(%RSP),%R13

(63) 0x418230 ADD	%RSI,%R14

(63) 0x418233 MOV	%R11,0x2f0(%RSP)

(63) 0x41823b LEA	(%R14,%RAX,1),%R11

(63) 0x41823f MOV	0x70(%RSP),%R12

(63) 0x418244 LEA	(%R13,%R11,8),%RSI

(63) 0x418249 MOV	0x170(%RSP),%RDI

(63) 0x418251 MOV	0x250(%RSP),%R11

(63) 0x418259 MOV	0x288(%RSP),%RDX

(63) 0x418261 ADD	%R12,%R11

(63) 0x418264 ADD	%RAX,%RDI

(63) 0x418267 MOV	0x248(%RSP),%R12

(63) 0x41826f LEA	(%R13,%RDI,8),%RDI

(63) 0x418274 LEA	(%RDX,%R11,8),%R13

(63) 0x418278 MOV	0x50(%RSP),%R11

(63) 0x41827d LEA	(%RBX,%R15,8),%R15

(63) 0x418281 ADD	%R11,%R12

(63) 0x418284 MOV	%R12,%RDX

(63) 0x418287 MOV	0x278(%RSP),%R12

(63) 0x41828f MOV	0x38(%RSP),%R11

(63) 0x418294 LEA	(%R12,%RDX,8),%R12

(63) 0x418298 MOV	0x290(%RSP),%RDX

(63) 0x4182a0 MOV	0x2c8(%RSP),%RBX

(63) 0x4182a8 ADD	%RDX,%R11

(63) 0x4182ab MOV	%R11,0x308(%RSP)

(63) 0x4182b3 MOV	0x78(%RSP),%RDX

(63) 0x4182b8 MOV	0x240(%RSP),%R11

(63) 0x4182c0 LEA	(%RBX,%R14,8),%R14

(63) 0x4182c4 ADD	%RDX,%R11

(63) 0x4182c7 MOV	0x280(%RSP),%RDX

(63) 0x4182cf MOV	%R15,0x300(%RSP)

(63) 0x4182d7 MOV	%R14,0x2f8(%RSP)

(63) 0x4182df LEA	(%RDX,%R11,8),%R11

(63) 0x4182e3 MOV	0x198(%RSP),%RBX

(63) 0x4182eb MOV	0x2f0(%RSP),%RDX

  (64) 0x4182f3 VMOVSD	(%R13,%RAX,8),%XMM12

  (64) 0x4182fa VMOVSD	-0x8(%RBX,%RAX,8),%XMM13

  (64) 0x418300 MOV	0x308(%RSP),%R15

  (64) 0x418308 VMULSD	(%R12,%RAX,8),%XMM12,%XMM10

  (64) 0x41830e VMULSD	-0x8(%R15,%RAX,8),%XMM13,%XMM15

  (64) 0x418315 VMOVSD	-0x8(%R13,%RAX,8),%XMM11

  (64) 0x41831c VMOVSD	(%RBX,%RAX,8),%XMM0

  (64) 0x418321 MOV	0x2a8(%RSP),%R14

  (64) 0x418329 VFMADD231SD	-0x8(%R12,%RAX,8),%XMM11,%XMM10

  (64) 0x418330 VFMADD231SD	(%R15,%RAX,8),%XMM0,%XMM15

  (64) 0x418336 MOV	0x300(%RSP),%R15

  (64) 0x41833e VMOVSD	(%R14,%RAX,8),%XMM9

  (64) 0x418344 VMOVSD	(%R15,%RAX,8),%XMM8

  (64) 0x41834a VSUBSD	-0x8(%R10),%XMM9,%XMM2

  (64) 0x418350 VADDSD	%XMM15,%XMM10,%XMM4

  (64) 0x418355 VSUBSD	-0x8(%R9),%XMM8,%XMM12

  (64) 0x41835b MOV	0x2b0(%RSP),%R14

  (64) 0x418363 VMULSD	%XMM5,%XMM4,%XMM3

  (64) 0x418367 VMULSD	(%R11,%RAX,8),%XMM12,%XMM10

  (64) 0x41836d MOV	0x2b8(%RSP),%R15

  (64) 0x418375 ADD	$0x8,%RCX

  (64) 0x418379 ADD	$0x8,%RDX

  (64) 0x41837d VDIVSD	%XMM3,%XMM1,%XMM14

  (64) 0x418381 VFMADD132SD	(%R14,%RAX,8),%XMM10,%XMM2

  (64) 0x418387 ADD	$0x8,%R10

  (64) 0x41838b ADD	$0x8,%R9

  (64) 0x41838f ADD	$0x8,%R8

  (64) 0x418393 ADD	$0x8,%RDI

  (64) 0x418397 ADD	$0x8,%RSI

  (64) 0x41839b VFNMADD213SD	(%R15,%RAX,8),%XMM14,%XMM2

  (64) 0x4183a1 MOV	0x2a0(%RSP),%R15

  (64) 0x4183a9 VMOVSD	%XMM2,-0x8(%RCX)

  (64) 0x4183ae VMOVUPD	-0x10(%R10),%XMM11

  (64) 0x4183b4 VSUBPD	-0x10(%R9),%XMM11,%XMM13

  (64) 0x4183ba VMULPD	-0x10(%R8),%XMM13,%XMM15

  (64) 0x4183c0 VUNPCKHPD	%XMM15,%XMM15,%XMM0

  (64) 0x4183c5 VADDPD	%XMM15,%XMM0,%XMM4

  (64) 0x4183ca VFNMADD213SD	(%R15,%RAX,8),%XMM14,%XMM4

  (64) 0x4183d0 MOV	0x298(%RSP),%R15

  (64) 0x4183d8 VMOVSD	%XMM4,-0x8(%RDX)

  (64) 0x4183dd VMOVSD	(%R15,%RAX,8),%XMM3

  (64) 0x4183e3 MOV	0x2f8(%RSP),%R15

  (64) 0x4183eb VSUBSD	-0x10(%RDI),%XMM3,%XMM9

  (64) 0x4183f0 VMOVSD	(%R15,%RAX,8),%XMM2

  (64) 0x4183f6 VSUBSD	-0x10(%RSI),%XMM2,%XMM8

  (64) 0x4183fb VMULSD	(%R11,%RAX,8),%XMM8,%XMM12

  (64) 0x418401 VFMADD132SD	(%R14,%RAX,8),%XMM12,%XMM9

  (64) 0x418407 INC	%RAX

  (64) 0x41840a VFNMADD213SD	-0x8(%RCX),%XMM14,%XMM9

  (64) 0x418410 VMOVSD	%XMM9,-0x8(%RCX)

  (64) 0x418415 VMOVUPD	-0x10(%RDI),%XMM10

  (64) 0x41841a VSUBPD	-0x10(%RSI),%XMM10,%XMM11

  (64) 0x41841f VMULPD	-0x10(%R8),%XMM11,%XMM13

  (64) 0x418425 VUNPCKHPD	%XMM13,%XMM13,%XMM15

  (64) 0x41842a VADDPD	%XMM13,%XMM15,%XMM0

  (64) 0x41842f VFNMADD213SD	-0x8(%RDX),%XMM0,%XMM14

  (64) 0x418435 VMOVSD	%XMM14,-0x8(%RDX)

  (64) 0x41843a CMP	%EAX,0x2c0(%RSP)

  (64) 0x418441 JG	4182f3

(63) 0x418447 INCL	0x2c4(%RSP)

(63) 0x41844e MOV	0xc8(%RSP),%R10

(63) 0x418456 MOV	0xd8(%RSP),%R9

(63) 0x41845e MOV	0xe0(%RSP),%RCX

(63) 0x418466 MOV	0x100(%RSP),%RDI

(63) 0x41846e MOV	0x220(%RSP),%R13

(63) 0x418476 MOV	0xf0(%RSP),%R8

(63) 0x41847e MOV	0xc0(%RSP),%RSI

(63) 0x418486 ADD	%R10,0x310(%RSP)

(63) 0x41848e ADD	%R10,0x318(%RSP)

(63) 0x418496 ADD	%R9,0x320(%RSP)

(63) 0x41849e ADD	%RCX,0x328(%RSP)

(63) 0x4184a6 ADD	%R8,0x208(%RSP)

(63) 0x4184ae ADD	%RDI,0x330(%RSP)

(63) 0x4184b6 ADD	%RSI,0x338(%RSP)

(63) 0x4184be ADD	%R10,0x198(%RSP)

(63) 0x4184c6 ADD	%R9,0x2b8(%RSP)

(63) 0x4184ce ADD	%RCX,0x2b0(%RSP)

(63) 0x4184d6 ADD	%R13,0x190(%RSP)

(63) 0x4184de MOV	0x2c4(%RSP),%EAX

(63) 0x4184e5 MOV	0xb8(%RSP),%R12

(63) 0x4184ed MOV	0xe8(%RSP),%RBX

(63) 0x4184f5 MOV	0xb0(%RSP),%RDX

(63) 0x4184fd MOV	0x108(%RSP),%R14

(63) 0x418505 MOV	0x228(%RSP),%R9

(63) 0x41850d MOV	0x98(%RSP),%R10

(63) 0x418515 MOV	0x210(%RSP),%R11

(63) 0x41851d MOV	0x268(%RSP),%R15

(63) 0x418525 MOV	0xd0(%RSP),%RCX

(63) 0x41852d MOV	0x218(%RSP),%R8

(63) 0x418535 ADD	%RDI,0x2a0(%RSP)

(63) 0x41853d ADD	%R12,0x2a8(%RSP)

(63) 0x418545 ADD	%RBX,0x188(%RSP)

(63) 0x41854d ADD	%RDX,0x180(%RSP)

(63) 0x418555 ADD	%R14,0x178(%RSP)

(63) 0x41855d ADD	%R9,0x170(%RSP)

(63) 0x418565 ADD	%R10,0x298(%RSP)

(63) 0x41856d ADD	%R11,0x1e8(%RSP)

(63) 0x418575 ADD	%R15,0x1e0(%RSP)

(63) 0x41857d ADD	%RCX,0x1d8(%RSP)

(63) 0x418585 ADD	%R8,0x1d0(%RSP)

(63) 0x41858d ADD	%R13,0x1c8(%RSP)

(63) 0x418595 MOV	0xf8(%RSP),%RDI

(63) 0x41859d MOV	0xa8(%RSP),%RSI

(63) 0x4185a5 MOV	0xa0(%RSP),%R13

(63) 0x4185ad ADD	%RBX,0x1c0(%RSP)

(63) 0x4185b5 ADD	%RDI,0x1b8(%RSP)

(63) 0x4185bd ADD	%RDX,0x1b0(%RSP)

(63) 0x4185c5 ADD	%R14,0x1a8(%RSP)

(63) 0x4185cd ADD	%R9,0x1a0(%RSP)

(63) 0x4185d5 ADD	%RSI,0x290(%RSP)

(63) 0x4185dd ADD	%R12,0x1f0(%RSP)

(63) 0x4185e5 ADD	%R13,0x200(%RSP)

(63) 0x4185ed ADD	%R10,0x1f8(%RSP)

(63) 0x4185f5 CMP	%EAX,0x258(%RSP)

(63) 0x4185fc JG	417a88

0x418602 VZEROUPPER

0x418605 LEA	-0x28(%RBP),%RSP

0x418609 POP	%RBX

0x41860a POP	%R12

0x41860c POP	%R13

0x41860e POP	%R14

0x418610 POP	%R15

0x418612 POP	%RBP

0x418613 RET

0x418614 NOPL	(%RAX)

(63) 0x418618 MOV	0x25c(%RSP),%R14D

(63) 0x418620 XOR	%EAX,%EAX

(63) 0x418622 JMP	417e4a

0x418627 INC	%EAX

0x418629 XOR	%EDX,%EDX

0x41862b JMP	417509

Coverage (%)	Name	Source Location	Module
○97.59	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.40	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	accelerate_kernel.f90:57-76
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:57-61,67-76.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 46.33 to 3.17 cycles (14.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:76

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 480 bytes. The binary function is storing 640 bytes.

General properties

nb instructions	272
nb uops	278
loop length	1511
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	85

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	46.33 cycles
front end	46.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.10	15.00	23.33	23.33	46.00	10.00	9.90	46.00	46.00	46.00	10.00	23.33
cycles	10.10	21.47	23.33	23.33	46.00	10.00	9.90	46.00	46.00	46.00	10.00	23.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	46.33
Dispatch	46.00
DIV/SQRT	6.00
Overall L1	46.33

Vectorization ratios

INT

all	1%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.33 cycles. At this rate:

5% of peak load performance is reached (10.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.81 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4174c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x340,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 418627 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x1167>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 418605 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x1145>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xa0(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,0x258(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x8(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x88(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R12,%RDX,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV (%RAX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb0(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x228(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x220(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,0x308(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xc0(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x80(%RBX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RCX,0x218(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,0x210(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10D,0x2c4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,0x278(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x280(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x270(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,0x138(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %R10D,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (,%RDI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RSI,0xc8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %R12D,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R15,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R15,%RSI,1),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,0x148(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDI,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (,%R15,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12D,0x25c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,0x288(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R10,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x8(%R9,%R10,1),%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0xc8(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x260(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R10,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,0x1e8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0xd0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RDX,0x2c8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x318(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R15,%RSI,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RCX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R12,0x310(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%R10,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,0x1d8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R11,%R12,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%RSI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x280(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,0x150(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,0x320(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%R12,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x1d0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x328(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe0(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R12,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,0xe8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RAX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x140(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDX,%R12,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R8,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0x208(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x100(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0xf8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RCX,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x88(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RCX,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x1b8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R8,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x108(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x110(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R8,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,0x108(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RAX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R14,0x330(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RSI,%R9,1),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x138(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14,0x1a8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%R14,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R15,%R10,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x90(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x288(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14,0x338(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RDX,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R15,%R10,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x78(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x220(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%R11,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0x198(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x280(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R14,%R11,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x40(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,0x2b8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%R11,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,0x268(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x2b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x190(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x270(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R15,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R10,%RDX,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xe0(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe8(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x100(%RBX),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %R12,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R8,%R9,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x228(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x88(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,0x188(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RAX,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R14,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R9,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RCX,%R12,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,0x2a8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R10,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R9,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x50(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R12,1),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RSI,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0x178(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RSI,%R9,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RCX,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R11,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14,0x2a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%RCX,1),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x2c8(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x168(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x268(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0x1c8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R15,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RBX,%R14,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R13,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x1f0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%R12,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RSI,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0x170(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x298(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x1e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x1f8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x308(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x25c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x278(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R10D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x2(%RAX),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R9,1),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R12,%R8,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R9D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %EAX,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%R12,%R13,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x8(%RCX),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VMOVSD 0x89d42(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RCX,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,0x290(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EBX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,0x84(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x2d0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 417509 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x49>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	accelerate_kernel.f90:57-76
Module	exec

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
To reference allocatable arrays, use "allocatable" instead of "pointer" pointers or qualify them with the "contiguous" attribute (Fortran 2008)
For structures, limit to one indirection. For example, use a_b%c instead of a%b%c with a_b set to a%b before this function

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:76

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/accelerate_kernel.f90:59

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 480 bytes. The binary function is storing 640 bytes.

General properties

nb instructions	272
nb uops	278
loop length	1511
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	2
used zmm registers	0
nb stack references	85

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	46.33 cycles
front end	46.33 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	10.10	15.00	23.33	23.33	46.00	10.00	9.90	46.00	46.00	46.00	10.00	23.33
cycles	10.10	21.47	23.33	23.33	46.00	10.00	9.90	46.00	46.00	46.00	10.00	23.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	46.33
Dispatch	46.00
DIV/SQRT	6.00
Overall L1	46.33

Vectorization ratios

INT

all	1%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	16%

Vector efficiency ratios

INT

all	11%
load	NA (no load vectorizable/vectorized instructions)
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	11%
load	12%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 46.33 cycles. At this rate:

5% of peak load performance is reached (10.36 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
10% of peak store performance is reached (13.81 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4174c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
SUB $0x340,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD $0x2,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R13D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 418627 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x1167>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 418605 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x1145>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
ADD %R12D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xa0(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,0x258(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV 0x8(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x98(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x88(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R10,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R12,%RDX,1),%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV (%RAX),%EDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%R14),%R12D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xb0(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x90(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x20(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x228(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x220(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x30(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x70(%RBX),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EDX,0x308(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
ADD $0x2,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0xc0(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xa8(%RBX),%R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x78(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VMOVSD 0x80(%RBX),%XMM1	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RCX,0x218(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x50(%RBX),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDI,0x210(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10D,0x2c4(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EDX,0x2c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %RSI,0x278(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x280(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x58(%RBX),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RAX,0x270(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%RBX),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x88(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RAX,0x138(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %R10D,%RAX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
LEA (,%RDI,8),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RSI,0xc8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVSXD %R12D,%RSI	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	N/A
MOV %R15,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R15,%RSI,1),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,0x148(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RDI,%R15	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (,%R15,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x28(%RBX),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12D,0x25c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R9,0x288(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R10,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA -0x8(%R9,%R10,1),%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0xc8(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,0x140(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x260(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R10,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,0x1e8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0xd0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd0(%RBX),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%R10	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %RDX,0x2c8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x318(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R15,%RSI,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RCX,8),%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R12,0x310(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%R10,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,0x1d8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0x90(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R11,%R12,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R8,%RSI,1),%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x280(%RSP),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R12,0x150(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RCX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,0x320(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%R12,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0xd8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0xe0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x1d0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0x328(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe0(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R12,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R12,0xe8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RAX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x140(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RDX,%R12,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R9,%R8,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0x208(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0xf8(%RBX),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x100(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14,0xf0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RCX,0xf8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RCX,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %RAX,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV 0x88(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RSI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0x1c0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%RCX,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0x100(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x1b8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%R9,%R8,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x108(%RBX),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x110(%RBX),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R8,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,0x108(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %RAX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R14,0x330(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0xc0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RSI,%R9,1),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x138(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R8,%R14	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14,0x1a8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDX,%R14,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x70(%RSP),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%R15,%R10,1),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RDI,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x90(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x288(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R14,0x338(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%RDX,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R15,%R10,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x78(%RSP),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x220(%RSP),%R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDI,%R11,1),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0x198(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x280(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RAX,%RDI	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%R14,%R11,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x40(%RSP),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,0x2b8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RDI,%R11,1),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R13,0x268(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x2b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x190(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x270(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R15,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%R10,%RDX,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xe0(%RBX),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xe8(%RBX),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD 0x100(%RBX),%RCX	1	0.20	0.20	0.33	0.33	0	0.20	0.20	0	0	0	0.20	0.33	1	0.33	N/A
ADD %R12,%RDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%R8,%R9,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x228(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x88(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RDX,0x188(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
IMUL %RAX,%RDX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
IMUL %RAX,%R13	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
MOV %R14,0xb8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
IMUL %R9,%RAX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	N/A
LEA (%RCX,%R12,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15,0x2a8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x48(%RSP),%RCX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0xf0(%RBX),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (,%R10,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10,0xb0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%R9,8),%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x50(%RSP),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
LEA (%RDX,%R12,1),%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %RSI,%R11	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0x178(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RSI,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA (%RSI,%R9,1),%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (%RSI,%RCX,1),%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R11,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R14,0x2a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x180(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RAX,%RCX,1),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x2c8(%RSP),%RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %RSI,0x168(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
ADD %RAX,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x268(%RSP),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %RDX,%R12	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %RDI,0x1c8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
SAL $0x3,%RDI	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %R15,0xa0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x158(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (%RBX,%R14,8),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
ADD %R13,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R11,0x160(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x1f0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
LEA (,%RAX,8),%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%R12,8),%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA (,%RSI,8),%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0x170(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x98(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R15,0x298(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x1b0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R8,0x1e0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RSI,0x1a0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R11,0xa8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDI,0x200(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x1f8(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x308(%RSP),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x25c(%RSP),%R10D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x278(%RSP),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
SUB %R10D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x2(%RAX),%EBX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
LEA (%R13,%R9,1),%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA (%R12,%R8,8),%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SHR $0x3,%R9D	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
MOV %EAX,0x5c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA (%R12,%R13,8),%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA -0x8(%RCX),%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SAL $0x6,%R9	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	N/A
VMOVSD 0x89d42(%RIP),%XMM5	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV %RCX,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R14,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOVQ $0,0x290(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EBX,0x80(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %EAX,0x84(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R9,0x2d0(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM1,%YMM7	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
VBROADCASTSD %XMM5,%YMM6	1	0	0	0	0	0	1	0	0	0	0	0	0	3	1	scal (12.5%)
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 417509 <__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0+0x49>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A

Name	Coverage (%)	Time (s)
▼__accelerate_kernel_module_MOD_accelerate_kernel._omp_fn.0–	5.63	1.99
▼Loop 63 - accelerate_kernel.f90:67-76 - exec–	0.00	0.01
○Loop 65 - accelerate_kernel.f90:67-76 - exec	5.63	1.99
○Loop 64 - accelerate_kernel.f90:67-76 - exec	0.00	0.01

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Code clean check

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

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Complex instructions

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Conversion instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code