OV - exec - Function __revert_kernel_module_MOD_revert_kernel._omp

	Function: __revert_kernel_module_MOD_revert_kernel._omp_fn.0	Module: exec	Source: revert_kernel.f90:41-48	Coverage (incl. loops): 2.31% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90: 41 - 48

--------------------------------------------------------------------------------

41:     !$OMP PARALLEL

42:

43:     !$OMP DO

44:     DO k=y_min,y_max

45:     !$OMP SIMD

46:       DO j=x_min,x_max

47:         density1(j,k)=density0(j,k)

48:         energy1(j,k)=energy0(j,k)

0x43d150 PUSH	%RBP

0x43d151 MOV	%RSP,%RBP

0x43d154 PUSH	%R15

0x43d156 PUSH	%R14

0x43d158 MOV	%RDI,%R14

0x43d15b PUSH	%R13

0x43d15d PUSH	%R12

0x43d15f PUSH	%RBX

0x43d160 AND	$-0x40,%RSP

0x43d164 ADD	$-0x80,%RSP

0x43d168 MOV	0x10(%RDI),%RAX

0x43d16c MOV	(%RAX),%R13D

0x43d16f CALL	402370 <@plt_start@+0x350>

0x43d174 MOV	%EAX,%R12D

0x43d177 CALL	4022e0 <@plt_start@+0x2c0>

0x43d17c MOV	0x18(%R14),%RDX

0x43d180 MOV	%EAX,%ECX

0x43d182 MOV	(%RDX),%EAX

0x43d184 INC	%EAX

0x43d186 SUB	%R13D,%EAX

0x43d189 CLTD

0x43d18a IDIV	%R12D

0x43d18d CMP	%EDX,%ECX

0x43d18f JL	43d6bc

0x43d195 IMUL	%EAX,%ECX

0x43d198 ADD	%ECX,%EDX

0x43d19a ADD	%EDX,%EAX

0x43d19c CMP	%EAX,%EDX

0x43d19e JGE	43d697

0x43d1a4 MOV	0x20(%R14),%R8

0x43d1a8 ADD	%R13D,%EDX

0x43d1ab MOV	(%R14),%RSI

0x43d1ae MOV	0x8(%R14),%RDI

0x43d1b2 MOV	%R8,0x78(%RSP)

0x43d1b7 MOV	0x50(%R14),%R8

0x43d1bb MOVSXD	%EDX,%RCX

0x43d1be MOV	0x28(%R14),%R9

0x43d1c2 MOV	0x40(%R14),%R12

0x43d1c6 MOVSXD	(%RSI),%R10

0x43d1c9 ADD	%R13D,%EAX

0x43d1cc MOV	%R8,0x30(%RSP)

0x43d1d1 MOV	(%RDI),%R13D

0x43d1d4 IMUL	%RCX,%R8

0x43d1d8 MOV	0x58(%R14),%RDI

0x43d1dc MOV	%R9,0x70(%RSP)

0x43d1e1 MOV	%R12,0x38(%RSP)

0x43d1e6 MOV	0x60(%R14),%R9

0x43d1ea IMUL	%RCX,%R12

0x43d1ee MOV	0x48(%R14),%RSI

0x43d1f2 ADD	%R10,%RDI

0x43d1f5 ADD	%R10,%RSI

0x43d1f8 ADD	%R8,%RDI

0x43d1fb MOV	%R9,0x40(%RSP)

0x43d200 MOV	0x68(%R14),%R8

0x43d204 IMUL	%RCX,%R9

0x43d208 ADD	%R12,%RSI

0x43d20b MOV	0x70(%R14),%R12

0x43d20f ADD	%R10,%R8

0x43d212 IMUL	%R12,%RCX

0x43d216 ADD	%R9,%R8

0x43d219 MOV	0x78(%R14),%R9

0x43d21d MOV	0x30(%R14),%R11

0x43d221 ADD	%R10,%R9

0x43d224 ADD	%RCX,%R9

0x43d227 MOV	%EAX,0x60(%RSP)

0x43d22b CMP	%R13D,%R10D

0x43d22e LEA	0x1(%R13),%EAX

0x43d232 MOV	%R10D,%ECX

0x43d235 MOV	%R11,0x58(%RSP)

0x43d23a MOV	%R10D,0x50(%RSP)

0x43d23f MOV	%R13D,0x54(%RSP)

0x43d244 MOV	%R12,0x48(%RSP)

0x43d249 MOV	0x38(%R14),%R11

0x43d24d CMOVLE	%EAX,%ECX

0x43d250 JG	43d6c5

0x43d256 SUB	%R10D,%R13D

0x43d259 LEA	0x1(%R13),%R15D

0x43d25d MOV	%R15D,%EBX

0x43d260 MOV	%R13D,0x64(%RSP)

0x43d265 SHR	$0x3,%EBX

0x43d268 MOV	%R15D,%R13D

0x43d26b SAL	$0x6,%RBX

0x43d26f AND	$-0x8,%R13D

0x43d273 AND	$0x7,%R15D

0x43d277 MOV	%RBX,0x68(%RSP)

0x43d27c MOV	%R13D,0x2c(%RSP)

0x43d281 MOV	%R15D,0x28(%RSP)

0x43d286 MOV	%ECX,0x1c(%RSP)

0x43d28a MOV	%R14,0x10(%RSP)

0x43d28f MOV	%R10,0x20(%RSP)

0x43d294 MOV	0x58(%RSP),%R10

0x43d299 NOPL	(%RAX)

(310) 0x43d2a0 CMPL	$0x6,0x64(%RSP)

(310) 0x43d2a5 JBE	43d6b0

(310) 0x43d2ab MOV	0x68(%RSP),%R15

(310) 0x43d2b0 MOV	0x78(%RSP),%RCX

(310) 0x43d2b5 LEA	-0x40(%R15),%R14

(310) 0x43d2b9 MOV	0x70(%RSP),%R12

(310) 0x43d2be SHR	$0x6,%R14

(310) 0x43d2c2 INC	%R14

(310) 0x43d2c5 LEA	(%RCX,%RSI,8),%R13

(310) 0x43d2c9 LEA	(%R12,%RDI,8),%R12

(310) 0x43d2cd LEA	(%R10,%R8,8),%RBX

(310) 0x43d2d1 LEA	(%R11,%R9,8),%RCX

(310) 0x43d2d5 XOR	%EAX,%EAX

(310) 0x43d2d7 AND	$0x7,%R14D

(310) 0x43d2db JE	43d401

(310) 0x43d2e1 CMP	$0x1,%R14

(310) 0x43d2e5 JE	43d3d5

(310) 0x43d2eb CMP	$0x2,%R14

(310) 0x43d2ef JE	43d3b4

(310) 0x43d2f5 CMP	$0x3,%R14

(310) 0x43d2f9 JE	43d393

(310) 0x43d2ff CMP	$0x4,%R14

(310) 0x43d303 JE	43d372

(310) 0x43d305 CMP	$0x5,%R14

(310) 0x43d309 JE	43d351

(310) 0x43d30b CMP	$0x6,%R14

(310) 0x43d30f JE	43d330

(310) 0x43d311 VMOVUPD	(%R13),%ZMM0

(310) 0x43d318 MOV	$0x40,%EAX

(310) 0x43d31d VMOVUPD	%ZMM0,(%R12)

(310) 0x43d324 VMOVUPD	(%RBX),%ZMM1

(310) 0x43d32a VMOVUPD	%ZMM1,(%RCX)

(310) 0x43d330 VMOVUPD	(%R13,%RAX,1),%ZMM2

(310) 0x43d338 VMOVUPD	%ZMM2,(%R12,%RAX,1)

(310) 0x43d33f VMOVUPD	(%RBX,%RAX,1),%ZMM3

(310) 0x43d346 VMOVUPD	%ZMM3,(%RCX,%RAX,1)

(310) 0x43d34d ADD	$0x40,%RAX

(310) 0x43d351 VMOVUPD	(%R13,%RAX,1),%ZMM4

(310) 0x43d359 VMOVUPD	%ZMM4,(%R12,%RAX,1)

(310) 0x43d360 VMOVUPD	(%RBX,%RAX,1),%ZMM5

(310) 0x43d367 VMOVUPD	%ZMM5,(%RCX,%RAX,1)

(310) 0x43d36e ADD	$0x40,%RAX

(310) 0x43d372 VMOVUPD	(%R13,%RAX,1),%ZMM6

(310) 0x43d37a VMOVUPD	%ZMM6,(%R12,%RAX,1)

(310) 0x43d381 VMOVUPD	(%RBX,%RAX,1),%ZMM7

(310) 0x43d388 VMOVUPD	%ZMM7,(%RCX,%RAX,1)

(310) 0x43d38f ADD	$0x40,%RAX

(310) 0x43d393 VMOVUPD	(%R13,%RAX,1),%ZMM8

(310) 0x43d39b VMOVUPD	%ZMM8,(%R12,%RAX,1)

(310) 0x43d3a2 VMOVUPD	(%RBX,%RAX,1),%ZMM9

(310) 0x43d3a9 VMOVUPD	%ZMM9,(%RCX,%RAX,1)

(310) 0x43d3b0 ADD	$0x40,%RAX

(310) 0x43d3b4 VMOVUPD	(%R13,%RAX,1),%ZMM10

(310) 0x43d3bc VMOVUPD	%ZMM10,(%R12,%RAX,1)

(310) 0x43d3c3 VMOVUPD	(%RBX,%RAX,1),%ZMM11

(310) 0x43d3ca VMOVUPD	%ZMM11,(%RCX,%RAX,1)

(310) 0x43d3d1 ADD	$0x40,%RAX

(310) 0x43d3d5 VMOVUPD	(%R13,%RAX,1),%ZMM12

(310) 0x43d3dd VMOVUPD	%ZMM12,(%R12,%RAX,1)

(310) 0x43d3e4 VMOVUPD	(%RBX,%RAX,1),%ZMM13

(310) 0x43d3eb VMOVUPD	%ZMM13,(%RCX,%RAX,1)

(310) 0x43d3f2 ADD	$0x40,%RAX

(310) 0x43d3f6 CMP	%RAX,0x68(%RSP)

(310) 0x43d3fb JE	43d50f

  (311) 0x43d401 VMOVUPD	(%R13,%RAX,1),%ZMM14

  (311) 0x43d409 VMOVUPD	%ZMM14,(%R12,%RAX,1)

  (311) 0x43d410 VMOVUPD	(%RBX,%RAX,1),%ZMM15

  (311) 0x43d417 VMOVUPD	%ZMM15,(%RCX,%RAX,1)

  (311) 0x43d41e VMOVUPD	0x40(%R13,%RAX,1),%ZMM0

  (311) 0x43d426 VMOVUPD	%ZMM0,0x40(%R12,%RAX,1)

  (311) 0x43d42e VMOVUPD	0x40(%RBX,%RAX,1),%ZMM1

  (311) 0x43d436 VMOVUPD	%ZMM1,0x40(%RCX,%RAX,1)

  (311) 0x43d43e VMOVUPD	0x80(%R13,%RAX,1),%ZMM2

  (311) 0x43d446 VMOVUPD	%ZMM2,0x80(%R12,%RAX,1)

  (311) 0x43d44e VMOVUPD	0x80(%RBX,%RAX,1),%ZMM3

  (311) 0x43d456 VMOVUPD	%ZMM3,0x80(%RCX,%RAX,1)

  (311) 0x43d45e VMOVUPD	0xc0(%R13,%RAX,1),%ZMM4

  (311) 0x43d466 VMOVUPD	%ZMM4,0xc0(%R12,%RAX,1)

  (311) 0x43d46e VMOVUPD	0xc0(%RBX,%RAX,1),%ZMM5

  (311) 0x43d476 VMOVUPD	%ZMM5,0xc0(%RCX,%RAX,1)

  (311) 0x43d47e VMOVUPD	0x100(%R13,%RAX,1),%ZMM6

  (311) 0x43d486 VMOVUPD	%ZMM6,0x100(%R12,%RAX,1)

  (311) 0x43d48e VMOVUPD	0x100(%RBX,%RAX,1),%ZMM7

  (311) 0x43d496 VMOVUPD	%ZMM7,0x100(%RCX,%RAX,1)

  (311) 0x43d49e VMOVUPD	0x140(%R13,%RAX,1),%ZMM8

  (311) 0x43d4a6 VMOVUPD	%ZMM8,0x140(%R12,%RAX,1)

  (311) 0x43d4ae VMOVUPD	0x140(%RBX,%RAX,1),%ZMM9

  (311) 0x43d4b6 VMOVUPD	%ZMM9,0x140(%RCX,%RAX,1)

  (311) 0x43d4be VMOVUPD	0x180(%R13,%RAX,1),%ZMM10

  (311) 0x43d4c6 VMOVUPD	%ZMM10,0x180(%R12,%RAX,1)

  (311) 0x43d4ce VMOVUPD	0x180(%RBX,%RAX,1),%ZMM11

  (311) 0x43d4d6 VMOVUPD	%ZMM11,0x180(%RCX,%RAX,1)

  (311) 0x43d4de VMOVUPD	0x1c0(%R13,%RAX,1),%ZMM12

  (311) 0x43d4e6 VMOVUPD	%ZMM12,0x1c0(%R12,%RAX,1)

  (311) 0x43d4ee VMOVUPD	0x1c0(%RBX,%RAX,1),%ZMM13

  (311) 0x43d4f6 VMOVUPD	%ZMM13,0x1c0(%RCX,%RAX,1)

  (311) 0x43d4fe ADD	$0x200,%RAX

  (311) 0x43d504 CMP	%RAX,0x68(%RSP)

  (311) 0x43d509 JNE	43d401

(310) 0x43d50f MOV	0x2c(%RSP),%EAX

(310) 0x43d513 MOV	0x50(%RSP),%R13D

(310) 0x43d518 MOV	0x28(%RSP),%R12D

(310) 0x43d51d MOV	%EAX,%R14D

(310) 0x43d520 ADD	%R13D,%EAX

(310) 0x43d523 TEST	%R12D,%R12D

(310) 0x43d526 JE	43d656

(310) 0x43d52c MOV	0x64(%RSP),%ECX

(310) 0x43d530 SUB	%R14D,%ECX

(310) 0x43d533 LEA	0x1(%RCX),%EBX

(310) 0x43d536 CMP	$0x2,%ECX

(310) 0x43d539 JBE	43d57f

(310) 0x43d53b MOV	0x78(%RSP),%R15

(310) 0x43d540 LEA	(%RSI,%R14,1),%R13

(310) 0x43d544 VMOVUPD	(%R15,%R13,8),%YMM14

(310) 0x43d54a MOV	0x70(%RSP),%RCX

(310) 0x43d54f LEA	(%RDI,%R14,1),%R12

(310) 0x43d553 VMOVUPD	%YMM14,(%RCX,%R12,8)

(310) 0x43d559 LEA	(%R8,%R14,1),%R13

(310) 0x43d55d VMOVUPD	(%R10,%R13,8),%YMM15

(310) 0x43d563 ADD	%R9,%R14

(310) 0x43d566 VMOVUPD	%YMM15,(%R11,%R14,8)

(310) 0x43d56c MOV	%EBX,%R14D

(310) 0x43d56f AND	$-0x4,%R14D

(310) 0x43d573 ADD	%R14D,%EAX

(310) 0x43d576 AND	$0x3,%EBX

(310) 0x43d579 JE	43d656

(310) 0x43d57f MOV	0x20(%RSP),%R15

(310) 0x43d584 MOV	%R9,%RBX

(310) 0x43d587 SUB	%R15,%RBX

(310) 0x43d58a MOV	%RSI,%R14

(310) 0x43d58d MOVSXD	%EAX,%RCX

(310) 0x43d590 MOV	%RBX,0x58(%RSP)

(310) 0x43d595 SUB	%R15,%R14

(310) 0x43d598 MOV	0x78(%RSP),%RBX

(310) 0x43d59d MOV	%RDI,%R13

(310) 0x43d5a0 MOV	%R8,%R12

(310) 0x43d5a3 SUB	%R15,%R13

(310) 0x43d5a6 SUB	%R15,%R12

(310) 0x43d5a9 LEA	(%R14,%RCX,1),%R15

(310) 0x43d5ad VMOVSD	(%RBX,%R15,8),%XMM0

(310) 0x43d5b3 MOV	0x70(%RSP),%RBX

(310) 0x43d5b8 LEA	(%RCX,%R13,1),%R15

(310) 0x43d5bc VMOVSD	%XMM0,(%RBX,%R15,8)

(310) 0x43d5c2 LEA	(%RCX,%R12,1),%R15

(310) 0x43d5c6 MOV	0x58(%RSP),%RBX

(310) 0x43d5cb VMOVSD	(%R10,%R15,8),%XMM1

(310) 0x43d5d1 ADD	%RBX,%RCX

(310) 0x43d5d4 VMOVSD	%XMM1,(%R11,%RCX,8)

(310) 0x43d5da LEA	0x1(%RAX),%ECX

(310) 0x43d5dd CMP	%ECX,0x54(%RSP)

(310) 0x43d5e1 JL	43d656

(310) 0x43d5e3 MOVSXD	%ECX,%RCX

(310) 0x43d5e6 MOV	0x78(%RSP),%RBX

(310) 0x43d5eb LEA	(%R14,%RCX,1),%R15

(310) 0x43d5ef VMOVSD	(%RBX,%R15,8),%XMM2

(310) 0x43d5f5 MOV	0x70(%RSP),%RBX

(310) 0x43d5fa LEA	(%R13,%RCX,1),%R15

(310) 0x43d5ff VMOVSD	%XMM2,(%RBX,%R15,8)

(310) 0x43d605 LEA	(%R12,%RCX,1),%R15

(310) 0x43d609 VMOVSD	(%R10,%R15,8),%XMM3

(310) 0x43d60f MOV	0x58(%RSP),%R15

(310) 0x43d614 ADD	$0x2,%EAX

(310) 0x43d617 ADD	%R15,%RCX

(310) 0x43d61a VMOVSD	%XMM3,(%R11,%RCX,8)

(310) 0x43d620 CMP	%EAX,0x54(%RSP)

(310) 0x43d624 JL	43d656

(310) 0x43d626 CLTQ

(310) 0x43d628 MOV	0x78(%RSP),%RCX

(310) 0x43d62d ADD	%RAX,%R14

(310) 0x43d630 VMOVSD	(%RCX,%R14,8),%XMM4

(310) 0x43d636 MOV	0x70(%RSP),%R14

(310) 0x43d63b ADD	%RAX,%R13

(310) 0x43d63e VMOVSD	%XMM4,(%R14,%R13,8)

(310) 0x43d644 ADD	%RAX,%R12

(310) 0x43d647 VMOVSD	(%R10,%R12,8),%XMM5

(310) 0x43d64d ADD	%RAX,%R15

(310) 0x43d650 VMOVSD	%XMM5,(%R11,%R15,8)

(310) 0x43d656 MOV	0x38(%RSP),%RAX

(310) 0x43d65b MOV	0x30(%RSP),%R13

(310) 0x43d660 MOV	0x40(%RSP),%R12

(310) 0x43d665 MOV	0x48(%RSP),%RBX

(310) 0x43d66a INC	%EDX

(310) 0x43d66c ADD	%RAX,%RSI

(310) 0x43d66f ADD	%R13,%RDI

(310) 0x43d672 ADD	%R12,%R8

(310) 0x43d675 ADD	%RBX,%R9

(310) 0x43d678 CMP	%EDX,0x60(%RSP)

(310) 0x43d67c JG	43d2a0

0x43d682 MOV	0x1c(%RSP),%ECX

0x43d686 MOV	0x10(%RSP),%R14

0x43d68b VZEROUPPER

0x43d68e MOV	%ECX,%EBX

0x43d690 MOV	%EBX,0x80(%R14)

0x43d697 LEA	-0x28(%RBP),%RSP

0x43d69b POP	%RBX

0x43d69c POP	%R12

0x43d69e POP	%R13

0x43d6a0 POP	%R14

0x43d6a2 POP	%R15

0x43d6a4 POP	%RBP

0x43d6a5 RET

0x43d6a6 NOPW	%CS:(%RAX,%RAX,1)

(310) 0x43d6b0 MOV	0x50(%RSP),%EAX

(310) 0x43d6b4 XOR	%R14D,%R14D

(310) 0x43d6b7 JMP	43d52c

0x43d6bc INC	%EAX

0x43d6be XOR	%EDX,%EDX

0x43d6c0 JMP	43d195

0x43d6c5 XOR	%R10D,%R10D

0x43d6c8 NOPL	(%RAX,%RAX,1)

(309) 0x43d6d0 INC	%EDX

(309) 0x43d6d2 CMP	%ECX,%EAX

(309) 0x43d6d4 JE	43d6f0

(309) 0x43d6d6 CMP	%EDX,0x60(%RSP)

(309) 0x43d6da JG	43d6d0

0x43d6dc TEST	%R10B,%R10B

0x43d6df JNE	43d690

0x43d6e1 LEA	-0x28(%RBP),%RSP

0x43d6e5 POP	%RBX

0x43d6e6 POP	%R12

0x43d6e8 POP	%R13

0x43d6ea POP	%R14

0x43d6ec POP	%R15

0x43d6ee POP	%RBP

0x43d6ef RET

(309) 0x43d6f0 CMP	%EDX,0x60(%RSP)

(309) 0x43d6f4 JLE	43d68e

(309) 0x43d6f6 MOV	%EAX,%EBX

(309) 0x43d6f8 MOV	$0x1,%R10D

(309) 0x43d6fe JMP	43d6d0

Coverage (%)	Name	Source Location	Module
○97.60	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○2.39	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	revert_kernel.f90:41-48
Module	exec

The function is defined in /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:41-48.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 21.17 to 1.67 cycles (12.65x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:48

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 164 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	121
nb uops	127
loop length	422
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.17 cycles
front end	21.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.80	8.80	12.33	12.33	13.00	8.87	8.80	13.00	13.00	13.00	8.73	12.33
cycles	8.80	13.33	12.33	12.33	13.00	8.87	8.80	13.00	13.00	13.00	8.73	12.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	21.17
Dispatch	13.33
DIV/SQRT	6.00
Overall L1	21.17

Vectorization ratios

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

all	9%
load	11%
store	9%
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.17 cycles. At this rate:

4% of peak load performance is reached (7.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 21.17 to 13.33 cycles (1.59x speedup).

ASM code

In the binary file, the address of the function is: 43d150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%R14),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 43d6bc <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x56c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43d697 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x547>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R13D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV (%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %EDX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV 0x28(%R14),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD (%RSI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x58(%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%R14),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %RCX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x48(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R10,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R10,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %RCX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R12,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x70(%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
IMUL %R12,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x78(%R14),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R10,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %EAX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R13D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%R13),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R11,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10D,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R13D,0x54(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R12,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMOVLE %EAX,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
JG 43d6c5 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x575>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %R10D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%R13),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R15D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R13D,0x64(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SHR $0x3,%EBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND $-0x8,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
AND $0x7,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOV %RBX,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13D,0x2c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15D,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ECX,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R14,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1c(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x10(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EBX,0x80(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 43d195 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x45>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R10B,%R10B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 43d690 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x540>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_7

Source file and lines	revert_kernel.f90:41-48
Module	exec

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): do i a(i)%x = b(i)%x (slow, non stride 1) => do i a%x(i) = b%x(i) (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43
VZEROUPPER: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:48

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 1 occurrences►
- /home/eoseret/qaas_runs_GNR/173-814-3702/intel/CloverLeaf1.3-FC/build/CloverLeaf1.3-FC/CloverLeaf_ref/kernels/revert_kernel.f90:43

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 164 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	121
nb uops	127
loop length	422
used x86 registers	16
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.17 cycles
front end	21.17 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11
uops	8.80	8.80	12.33	12.33	13.00	8.87	8.80	13.00	13.00	13.00	8.73	12.33
cycles	8.80	13.33	12.33	12.33	13.00	8.87	8.80	13.00	13.00	13.00	8.73	12.33

Execution ports to units layout:

P0 (256 bits): VPU, BRU, ALU, DIV/SQRT
P1 (256 bits): ALU, VPU
P2 (512 bits): load
P3 (512 bits): load
P4 (512 bits): store data
P5 (512 bits): ALU, VPU
P6: ALU, BRU
P7: store address
P8: store address
P9 (512 bits): store data
P10: ALU
P11 (512 bits): load

Cycles executing div or sqrt instructions

6.00

Cycles summary

Front-end	21.17
Dispatch	13.33
DIV/SQRT	6.00
Overall L1	21.17

Vectorization ratios

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	6%

Vector efficiency ratios

all	9%
load	11%
store	9%
mul	11%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.17 cycles. At this rate:

4% of peak load performance is reached (7.75 out of 192.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (5.29 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 43d150

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R15	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R14	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH %R13	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %R12	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
PUSH %RBX	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	5-12	0.50	N/A
AND $-0x40,%RSP	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
ADD $-0x80,%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x10(%RDI),%RAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV (%RAX),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
CALL 402370 <@plt_start@+0x350>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CALL 4022e0 <@plt_start@+0x2c0>	2	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	0	1	N/A
MOV 0x18(%R14),%RDX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
SUB %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CLTD	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
IDIV %R12D	4	0	3	0	0	0	0	0	0	0	0	0	0	11-16	6	scal (6.3%)
CMP %EDX,%ECX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JL 43d6bc <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x56c>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
IMUL %EAX,%ECX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (6.3%)
ADD %ECX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %EDX,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
CMP %EAX,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
JGE 43d697 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x547>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
MOV 0x20(%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R13D,%EDX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV (%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV 0x8(%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R8,0x78(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x50(%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD %EDX,%RCX	1	0	0.33	0	0	0	0.33	0	0	0	0	0.33	0	1	0.33	scal (6.3%)
MOV 0x28(%R14),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x40(%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOVSXD (%RSI),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R13D,%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R8,0x30(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV (%RDI),%R13D	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
IMUL %RCX,%R8	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x58(%R14),%RDI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
MOV %R9,0x70(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R12,0x38(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x60(%R14),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %RCX,%R12	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
MOV 0x48(%R14),%RSI	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
ADD %R10,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R10,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
ADD %R8,%RDI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV %R9,0x40(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x68(%R14),%R8	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
IMUL %RCX,%R9	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R12,%RSI	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
MOV 0x70(%R14),%R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R10,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
IMUL %R12,%RCX	1	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (12.5%)
ADD %R9,%R8	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV 0x78(%R14),%R9	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
MOV 0x30(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
ADD %R10,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
ADD %RCX,%R9	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (12.5%)
MOV %EAX,0x60(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
CMP %R13D,%R10D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	scal (6.3%)
LEA 0x1(%R13),%EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R10D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R11,0x58(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10D,0x50(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R13D,0x54(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R12,0x48(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x38(%R14),%R11	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (12.5%)
CMOVLE %EAX,%ECX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	1	0.50	scal (6.3%)
JG 43d6c5 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x575>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
SUB %R10D,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
LEA 0x1(%R13),%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
MOV %R15D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R13D,0x64(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
SHR $0x3,%EBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (6.3%)
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SAL $0x6,%RBX	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0-2	0.50	scal (12.5%)
AND $-0x8,%R13D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	N/A
AND $0x7,%R15D	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1-2	0.20	scal (6.3%)
MOV %RBX,0x68(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R13D,0x2c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R15D,0x28(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %ECX,0x1c(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
MOV %R14,0x10(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV %R10,0x20(%RSP)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (12.5%)
MOV 0x58(%RSP),%R10	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
NOPL (%RAX)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1c(%RSP),%ECX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	scal (6.3%)
MOV 0x10(%RSP),%R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1	0.33	N/A
VZEROUPPER	2	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EBX,0x80(%R14)	1	0	0	0	0	0.50	0	0	0.50	0.50	0.50	0	0	1	0.50	scal (6.3%)
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A
NOPW %CS:(%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
INC %EAX	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	1	0.20	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JMP 43d195 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x45>	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2.08	N/A
XOR %R10D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPL (%RAX,%RAX,1)	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
TEST %R10B,%R10B	1	0.20	0.20	0	0	0	0.20	0.20	0	0	0	0.20	0	2	0.20	N/A
JNE 43d690 <__revert_kernel_module_MOD_revert_kernel._omp_fn.0+0x540>	1	0.50	0	0	0	0	0	0.50	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
POP %RBX	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R12	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R13	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R14	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %R15	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
POP %RBP	1	0	0	0.33	0.33	0	0	0	0	0	0	0	0.33	1-6	0.33	N/A
RET	1	0.50	0	0.33	0.33	0	0	0.50	0	0	0	0	0.33	0	2.13	N/A

Name	Coverage (%)	Time (s)
▼__revert_kernel_module_MOD_revert_kernel._omp_fn.0–	2.31	0.82
▼Loop 310 - revert_kernel.f90:45-48 - exec–	0.00	0.01
○Loop 311 - revert_kernel.f90:47-48 - exec	2.31	0.82
○Loop 309 - revert_kernel.f90:41-45 - exec	0.00	0.00

Report Configuration

Vectorization

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Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code