	*************************************************
	*                                               *
	*          ONE-View report generation           *
	*                                               *
	*************************************************

[MAQAO] Info: Experiment configuration summary is available adding -dbg=1 in command line

* [MAQAO] Warning: Experiment directory /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_6/oneview_results_1786624126 already exists and is reused.
           It can be replaced using --replace in the command line.
[MAQAO] Info: 
[MAQAO] Info: START THE APPLICATION PROFILING
[MAQAO] Info: -> RUNNING THE PROFILER...
[MAQAO] Info:   LPROF has already been run
[MAQAO] Info: STOP THE APPLICATION PROFILING
[MAQAO] Info: 
[MAQAO] Info: START FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: -> OPEN THE MAIN APPLICATION BINARY ...
[MAQAO] Info: ---> ALL LOOPS HAVE BEEN ANALYZED
[MAQAO] Info: ---> ALL FUNCTIONS HAVE BEEN ANALYZED
[MAQAO] Info: STOP FUNCTIONS AND LOOPS ANALYSIS ...
[MAQAO] Info: 
[MAQAO] Info: START THE REPORT GENERATION
[MAQAO] Info: -> ONE-VIEW EXPERIMENT DIRECTORY: /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_6/oneview_results_1786624126


+====================================================================================================================+
+                                                    1  -  GLOBAL                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             1.1  -  Experiment Summary                                             +
+--------------------------------------------------------------------------------------------------------------------+

  Application:			/beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/run/binaries/gcc_6/exec
  Timestamp:			2026-08-13 14:28:46
  Universal Timestamp:		1786624126
  Experiment Type:		MPI; Throughput; 
  Machine:			gmz17.benchmarkcenter.megware.com
  Architecture:			x86_64
  Micro Architecture:		ZEN_V5
  Model Name:			AMD EPYC 9655 96-Core Processor
  Cache Size:			1024 KB
  Number of Cores:		96
  OS Version:			Linux 5.14.0-687.29.1.el9_8.x86_64 #1 SMP PREEMPT_DYNAMIC Thu Jul 23 16:18:48 EDT 2026
  Compilation Options:		
		exec: GNU C++17 15.1.0 -march=znver5 -g -O2 -std=c++17 -funroll-loops -ffast-math -fno-omit-frame-pointer -fcf-protection=none -fopenmp 
  Number of processes observed:	8
  Number of threads observed:	8
  MAQAO version:		2026.1.0
  MAQAO build:			6d1be1d51c1e63266254997eb301734a7264775d::20260810-150026




+--------------------------------------------------------------------------------------------------------------------+
+                                               1.2  -  Global Metrics                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Total Time:				112.00 s
  Max (Thread Active Time):		111.84 s
  Average Active Time:			111.83 s
  Activity Ratio:			99.8 %
  Average number of active threads:	7.987
  Affinity Stability:			99.8 %
  Time spent in analyzed loops:		98.6 %
  Time spent in analyzed innermost loops: 98.5 %
  Time spent in user code:		98.7 %
  Compilation Options Score:		87.5
  Array Access Efficiency:		85.7 %

   Potential Speedups
  ----------------------------------------------------
  Perfect Flow Complexity:		1.23
  Perfect OpenMP/MPI/Pthread/TBB:	1.01
  Perfect OpenMP/MPI/Pthread/TBB + Load Distribution:	1.01
  If No Scalar Integer:
      Potential Speedup:		1.02
      Nb Loops to get 80%:		3
  If FP Vectorized:
      Potential Speedup:		1.21
      Nb Loops to get 80%:		3
  If Fully Vectorized:
      Potential Speedup:		1.38
      Nb Loops to get 80%:		5
  If Only FP Arithmetic:
      Potential Speedup:		1.34
      Nb Loops to get 80%:		9




+--------------------------------------------------------------------------------------------------------------------+
+                                             1.3  -  Potential Speedups                                             +
+--------------------------------------------------------------------------------------------------------------------+

  If No Scalar Integer:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0063 | 1.0170 | 1.0170 | 1.0170 | 1.0170 | 
  Top 5 loops:
    exec - 204:	1.0063
    exec - 230:	1.0103
    exec - 232:	1.0142
    exec - 258:	1.0167
    exec - 294:	1.0168

  If FP Vectorized:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.1194 | 1.2132 | 1.2132 | 1.2132 | 1.2132 | 
  Top 5 loops:
    exec - 625:	1.1194
    exec - 230:	1.1677
    exec - 232:	1.2102
    exec - 258:	1.2132
    exec - 202:	1.2132

  If Fully Vectorized:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.1207 | 1.3820 | 1.3823 | 1.3823 | 1.3823 | 
  Top 5 loops:
    exec - 625:	1.1207
    exec - 230:	1.181
    exec - 232:	1.2343
    exec - 249:	1.2826
    exec - 204:	1.3246

  If Only FP Arithmetic:
      Number of loops   | 1      | 10     | 20     | 29     | 40     | 
      Cumulated Speedup | 1.0654 | 1.2935 | 1.3384 | 1.3388 | 1.3388 | 
  Top 5 loops:
    exec - 249:	1.0654
    exec - 207:	1.1194
    exec - 204:	1.1701
    exec - 321:	1.1916
    exec - 318:	1.2139



+====================================================================================================================+
+                                                   2  -  SUMMARY                                                    +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                             2.1  -  EXPERIMENT QUALITY                                             +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Application profile is long enough (111.84 s)
To have good quality measurements, it is advised that the application profiling time is greater than 10 seconds.

  [3 / 3] Most of time spent in analyzed modules comes from functions with source/debug info
-g option gives access to debugging informations, such are source locations.

  [2.9993369377272 / 3] Most of time spent in analyzed modules (99.98%) comes from functions compiled with architecture specialization option
-march=znver5


  [3 / 3] Most of time spent in analyzed modules comes from functions with compilation options informations and
-fno-omit-frame-pointer is present
-fno-omit-frame-pointer improves the accuracy of callchains found during the application profiling.

  [3 / 3] Optimization level option is correctly used


  [3 / 3] Host configuration allows retrieval of all necessary metrics.


  [2 / 2] Application is correctly profiled ("Others" category represents 0.01 % of the execution time)
To have a representative profiling, it is advised that the category "Others" represents less than 20% of the execution
time in order to analyze as much as possible of the user code

  [1 / 1] Lstopo present. The Topology lstopo report will be generated.



+--------------------------------------------------------------------------------------------------------------------+
+                                                2.2  -  CODE QUALITY                                                +
+--------------------------------------------------------------------------------------------------------------------+

  [4 / 4] Enough time of the experiment time spent in analyzed loops (98.56%)
If the time spent in analyzed loops is less than 30%, standard loop optimizations will have a limited impact on
application performances.

  [4 / 4] Threads activity is good
On average, more than 99.84% of observed threads are actually active 

  [4 / 4] CPU activity is good
CPU cores are active 99.81% of time

  [4 / 4] Loop profile is not flat
At least one loop coverage is greater than 4% (12.49%), representing an hotspot for the application

  [4 / 4] Enough time of the experiment time spent in analyzed innermost loops (98.47%)
If the time spent in analyzed innermost loops is less than 15%, standard innermost loop optimizations such as
vectorisation will have a limited impact on application performances.

  [4 / 4] Affinity is good (99.81%)
Threads are not migrating to CPU cores: probably successfully pinned

  [3 / 3] Less than 10% (0.00%) is spend in BLAS1 operations
It could be more efficient to inline by hand BLAS1 operations

  [3 / 3] Functions mostly use all threads
Functions running on a reduced number of threads (typically sequential code) cover less than 10% of application
walltime (0.00%)

  [3 / 3] Cumulative Outermost/In between loops coverage (0.09%) lower than cumulative innermost loop coverage (98.47%)
Having cumulative Outermost/In between loops coverage greater than cumulative innermost loop coverage will make loop
optimization more complex

  [2 / 2] Less than 10% (0.00%) is spend in BLAS2 operations
BLAS2 calls usually could make a poor cache usage and could benefit from inlining.

  [2 / 2] Less than 10% (0.00%) is spend in Libm/SVML (special functions)



+--------------------------------------------------------------------------------------------------------------------+
+                                               2.3  -  LOOPS OVERVIEW                                               +
+--------------------------------------------------------------------------------------------------------------------+

  Top 5 loops:
   + exec - 625 :
     analysis: Execution Time: 12 % - Vectorization Ratio: 13.79 % - Vector Length Use: 14.22 %
     Loop Computation Issues: 36
        [36] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 9
            issues (= instructions) costing 4 points each.
     Control Flow Issues: 9
        [9] [SA] Too many paths (5 paths) - Simplify control structure. There are 5 issues ( = paths) costing 1 point
            each with a malus of 4 points.
     Data Access Issues: 3
        [3] [SA] Presence of special instructions executing on a single port (BLEND/MERGE) - Simplify data access and
            try to get stride 1 access. There are 3 issues (= instructions) costing 1 point each.
     Vectorization Roadblocks: 9
        [9] [SA] Too many paths (5 paths) - Simplify control structure. There are 5 issues ( = paths) costing 1 point
            each with a malus of 4 points.
     Inefficient Vectorization: 3
        [3] [SA] Presence of special instructions executing on a single port (BLEND/MERGE) - Simplify data access and
            try to get stride 1 access. There are 3 issues (= instructions) costing 1 point each.

   + exec - 249 :
     analysis: Execution Time: 9 % - Vectorization Ratio: 47.39 % - Vector Length Use: 37.46 %
     Loop Computation Issues: 56
        [56] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 14
            issues (= instructions) costing 4 points each.
     Data Access Issues: 1026
        [544] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 272 issues ( = data accesses) costing 2
            point each.
        [482] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST,
            Other_packing) - Simplify data access and try to get stride 1 access. There are 482 issues (=
            instructions) costing 1 point each.
     Vectorization Roadblocks: 544
        [544] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 272 issues ( = data accesses) costing 2
            point each.
     Inefficient Vectorization: 484
        [482] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST,
            Other_packing) - Simplify data access and try to get stride 1 access. There are 482 issues (=
            instructions) costing 1 point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.

   + exec - 207 :
     analysis: Execution Time: 6 % - Vectorization Ratio: 47.76 % - Vector Length Use: 38.29 %
     Loop Computation Issues: 24
        [24] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 6
            issues (= instructions) costing 4 points each.
     Data Access Issues: 343
        [58] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 29 issues ( = data accesses) costing 2
            point each.
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each
        [267] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST,
            Other_packing) - Simplify data access and try to get stride 1 access. There are 267 issues (=
            instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 74
        [58] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 29 issues ( = data accesses) costing 2
            point each.
        [16] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 4 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 269
        [267] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE, BROADCAST,
            Other_packing) - Simplify data access and try to get stride 1 access. There are 267 issues (=
            instructions) costing 1 point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.

   + exec - 312 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 70.37 % - Vector Length Use: 74.07 %
     Loop Computation Issues: 12
        [12] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 3
            issues (= instructions) costing 4 points each.
     Data Access Issues: 0
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each

   + exec - 204 :
     analysis: Execution Time: 5 % - Vectorization Ratio: 46.57 % - Vector Length Use: 38.12 %
     Loop Computation Issues: 26
        [24] [SA] Presence of expensive FP instructions - Perform hoisting, change algorithm, use SVML or proper
            numerical library or perform value profiling (count the number of distinct input values). There are 6
            issues (= instructions) costing 4 points each.
        [2] [SA] Presence of a large number of scalar integer instructions - Simplify loop structure, perform loop
            splitting or perform unroll and jam. This issue costs 2 points.
     Data Access Issues: 314
        [72] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 36 issues ( = data accesses) costing 2
            point each.
        [36] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 9 issues ( = indirect data accesses) costing 4 point each.
        [0] [SA] Inefficient vectorization: more than 10% of the vector loads instructions are unaligned - When
            allocating arrays, don’t forget to align them. There are 0 issues ( = arrays) costing 2 points each
        [204] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE,
            Other_packing) - Simplify data access and try to get stride 1 access. There are 204 issues (=
            instructions) costing 1 point each.
        [2] [SA] More than 20% of the loads are accessing the stack - Perform loop splitting to decrease pressure on
            registers. This issue costs 2 points.
     Vectorization Roadblocks: 108
        [72] [SA] Presence of constant non unit stride data access - Use array restructuring, perform loop interchange
            or use gather instructions to lower a bit the cost. There are 36 issues ( = data accesses) costing 2
            point each.
        [36] [SA] Presence of indirect accesses - Use array restructuring or gather instructions to lower the cost.
            There are 9 issues ( = indirect data accesses) costing 4 point each.
     Inefficient Vectorization: 206
        [204] [SA] Presence of special instructions executing on a single port (INSERT/EXTRACT, BLEND/MERGE,
            Other_packing) - Simplify data access and try to get stride 1 access. There are 204 issues (=
            instructions) costing 1 point each.
        [2] [SA] Inefficient vectorization: use of masked instructions - Simplify control structure. The issue costs 2
            points.



+====================================================================================================================+
+                                                 3  -  APPLICATION                                                  +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                               3.1  -  Categorization                                               +
+--------------------------------------------------------------------------------------------------------------------+

   Category | IO     | Exe    | System  | Others  | Memory | String | MPI   | TBB   | OMP   | Pthread | Math  |
  ----------+--------+--------+---------+---------+--------+--------+-------+-------+-------+---------+-------+
   Time (%) | 0.00   | 98.68  | 0.33    | 0.01    | 0.01   | 0.10   | 0.86  | 0.00  | 0.01  | 0.00    | 0.00  |




+--------------------------------------------------------------------------------------------------------------------+
+                                          3.2  -  Function Based Profiling                                          +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Functions              | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 2                         | 22.36                     | 22.36                     |
   4% to 8%                   | 7                         | 35.89                     | 58.25                     |
   2% to 4%                   | 9                         | 23.86                     | 82.11                     |
   1% to 2%                   | 7                         | 11.28                     | 93.39                     |
   0.5% to 1%                 | 7                         | 5.62                      | 99.01                     |
   0.25% to 0.5%              | 1                         | 0.33                      | 99.34                     |
   0.125% to 0.25%            | 1                         | 0.15                      | 99.49                     |
   < 0.125%                   | 17                        | 0.41                      | 99.90                     |




+--------------------------------------------------------------------------------------------------------------------+
+                                            3.3  -  Loop Based Profiling                                            +
+--------------------------------------------------------------------------------------------------------------------+

   Buckets                    | Nb Loops                  | Coverage                  | Cumulated Coverage        |
  ----------------------------+---------------------------+---------------------------+---------------------------+
   > 8%                       | 2                         | 22.35                     | 22.35                     |
   4% to 8%                   | 7                         | 35.83                     | 58.18                     |
   2% to 4%                   | 9                         | 23.84                     | 82.02                     |
   1% to 2%                   | 7                         | 11.27                     | 93.29                     |
   0.5% to 1%                 | 6                         | 5.09                      | 98.38                     |
   0.25% to 0.5%              | 0                         | 0.00                      | 98.38                     |
   0.125% to 0.25%            | 0                         | 0.00                      | 98.38                     |
   < 0.125%                   | 6                         | 0.09                      | 98.47                     |


+====================================================================================================================+
+                                                  4  -  FUNCTIONS                                                   +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                              4.1  -  Top 10 Functions                                              +
+--------------------------------------------------------------------------------------------------------------------+

   Function                                               | Module              | Coverage (%)   | Time (s)       |
  --------------------------------------------------------+---------------------+----------------+----------------+
   viscosity_kernel(int, int, int, int, clover::Buffer... | exec                | 12.49          | 13.97          |
   calc_dt_kernel(int, int, int, int, double, double, ... | exec                | 9.87           | 11.03          |
   advec_cell_kernel(int, int, int, int, int, int, clo... | exec                | 6.07           | 6.78           |
   PdV_kernel(bool, int, int, int, int, double, clover... | exec                | 5.66           | 6.33           |
   advec_cell_kernel(int, int, int, int, int, int, clo... | exec                | 5.38           | 6.01           |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 5.16           | 5.77           |
   PdV_kernel(bool, int, int, int, int, double, clover... | exec                | 4.84           | 5.42           |
   accelerate_kernel(int, int, int, int, double, clove... | exec                | 4.60           | 5.14           |
   advec_mom_kernel(int, int, int, int, clover::Buffer... | exec                | 4.19           | 4.68           |
   ideal_gas_kernel(int, int, int, int, clover::Buffer... | exec                | 3.53           | 3.95           |


+====================================================================================================================+
+                                                    5  -  LOOPS                                                     +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                5.1  -  Top 10 Loops                                                +
+--------------------------------------------------------------------------------------------------------------------+

   Loop Id        | Module              | Source Location                                        | Coverage (%)   |
  ----------------+---------------------+--------------------------------------------------------+----------------+
   625            | exec                | context.h:69-69,viscosity.cpp:39-64                    | 12.49          |
   249            | exec                | context.h:46-46,context.h:69-69,calc_dt.cpp:52-75      | 9.86           |
   207            | exec                | context.h:69-69,advec_cell.cpp:163-163,advec_cell.c... | 6.06           |
   312            | exec                | PdV.cpp:72-83                                          | 5.66           |
   204            | exec                | context.h:69-69,advec_cell.cpp:71-72,advec_cell.cpp... | 5.36           |
   230            | exec                | context.h:69-69,advec_mom.cpp:114-139                  | 5.15           |
   309            | exec                | PdV.cpp:51-63                                          | 4.84           |
   187            | exec                | accelerate.cpp:43-53                                   | 4.59           |
   232            | exec                | context.h:69-69,advec_mom.cpp:186-211                  | 4.18           |
   274            | exec                | ideal_gas.cpp:40-45                                    | 3.53           |





+====================================================================================================================+
+                                                     6  -  CQA                                                      +
+====================================================================================================================+


+--------------------------------------------------------------------------------------------------------------------+
+                                                   6.1  -  Loops                                                    +
+--------------------------------------------------------------------------------------------------------------------+





      6.1.1  -  Loop 625 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:39-64


The related source loop is not unrolled or unrolled with no peel/tail loop.
Warnings:
 - Ignoring paths for analysis
 - Too many paths. Rerun with max-paths=5
 - RecMII not computed since number of paths is unknown or > max_paths
 - Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 5 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.1.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

2% of peak computational performance is used (1.37 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.1.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 14% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 39.50 to 5.44 cycles (7.26x speedup).

Details
13% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 20% of SSE/AVX loads are used in vector version.
 - 0% of SSE/AVX stores are used in vector version.
 - 5% of SSE/AVX addition or subtraction instructions are used in vector version.
 - 6% of SSE/AVX multiply instructions are used in vector version.
 - 0% of SSE/AVX fused multiply-add instructions are used in vector version.
 - 11% of SSE/AVX divide and square root instructions are used in vector version.
 - 37% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.1.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 39.50 to 15.75 cycles (2.51x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.1.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 39.50 to 18.00 cycles (2.19x speedup).


      6.1.1.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 4 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.1.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 4 occurrences<<list_path_1_complex_1>>



      6.1.1.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

52 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).
3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).



      6.1.1.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 54 FP arithmetical operations:
 - 24: addition or subtraction (4 inside FMA instructions)
 - 20: multiply (4 inside FMA instructions)
 - 9: divide
 - 1: square root
The binary loop is loading 272 bytes (34 double precision FP elements).
The binary loop is storing 16 bytes (2 double precision FP elements).


      6.1.1.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.







      6.1.2  -  Loop 249 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:52-75


It is main loop of related source loop which is unrolled by 12 (including vectorization).

      6.1.2.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

5% of peak computational performance is used (2.59 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.2.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 37% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 167.00 to 115.25 cycles (1.45x speedup).

Details
47% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 11% of SSE/AVX loads are used in vector version.
 - 55% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.2.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - execution of FP add operations (the FP add unit is a bottleneck)
 - execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 167.00 to 145.00 cycles (1.15x speedup).


Workaround
 - Reduce the number of FP add instructions
 - Reduce the number of FP multiply/FMA instructions





      6.1.2.1.3  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.2.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 16 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.02x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.2.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCMPPD: 2 occurrences<<list_path_1_complex_1>>
 - VMOVAPD: 9 occurrences<<list_path_1_complex_2>>
 - VPEXTRQ: 68 occurrences<<list_path_1_complex_3>>



      6.1.2.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 272 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.2.1.7  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 102 suboptimal vector unaligned load/store instructions.


Details
 - VINSERTF64X2: 68 occurrences<<list_path_1_vec_align_1>>
 - VINSERTF64X4: 34 occurrences<<list_path_1_vec_align_2>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.2.1.8  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

76 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.2.1.9  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 432 FP arithmetical operations:
 - 144: addition or subtraction (16 inside FMA instructions)
 - 176: multiply (16 inside FMA instructions)
 - 96: divide
 - 16: square root
The binary loop is loading 4576 bytes (572 double precision FP elements).
The binary loop is storing 576 bytes (72 double precision FP elements).


      6.1.2.1.10  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.







      6.1.3  -  Loop 207 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163,174-202


It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.3.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

10% of peak computational performance is used (5.22 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.3.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 38% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 95.00 to 57.00 cycles (1.67x speedup).

Details
47% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 8% of SSE/AVX loads are used in vector version.
 - 18% of SSE/AVX stores are used in vector version.
 - 60% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.3.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - execution of FP add operations (the FP add unit is a bottleneck)
 - execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 95.00 to 87.88 cycles (1.08x speedup).


Workaround
 - Reduce the number of FP add instructions
 - Reduce the number of FP multiply/FMA instructions





      6.1.3.1.3  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.3.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 64 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.04x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.3.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVAPD: 3 occurrences<<list_path_1_complex_1>>
 - VMOVUPD: 4 occurrences<<list_path_1_complex_2>>
 - VPEXTRQ: 32 occurrences<<list_path_1_complex_3>>



      6.1.3.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 29 occurrence(s)
 - Irregular (variable stride) or indirect: 4 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.3.1.7  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 60 suboptimal vector unaligned load/store instructions.


Details
 - VINSERTF64X2: 40 occurrences<<list_path_1_vec_align_1>>
 - VINSERTF64X4: 20 occurrences<<list_path_1_vec_align_2>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.3.1.8  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

72 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.3.1.9  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 496 FP arithmetical operations:
 - 192: addition or subtraction (64 inside FMA instructions)
 - 256: multiply (64 inside FMA instructions)
 - 48: divide
The binary loop is loading 2640 bytes (330 double precision FP elements).
The binary loop is storing 688 bytes (86 double precision FP elements).


      6.1.3.1.10  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.







      6.1.4  -  Loop 312 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:72-83.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.4.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

40% of peak computational performance is used (19.33 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.4.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 74% of vector register length is used (average across all SSE/AVX instructions).


Details
70% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.



      6.1.4.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.00 cycles (1.20x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.4.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.00 cycles (1.20x speedup).


      6.1.4.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 24 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.4.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPD: 2 occurrences<<list_path_1_complex_1>>



      6.1.4.1.6  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 12 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 12 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.4.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

26 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.4.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 232 FP arithmetical operations:
 - 144: addition or subtraction (24 inside FMA instructions)
 - 64: multiply (24 inside FMA instructions)
 - 24: divide
The binary loop is loading 1664 bytes (208 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.4.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.







      6.1.5  -  Loop 204 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:71-72,79-110
 - /cluster/comp/gcc/15.1.0/include/c++/15.1.0/bits/stl_algobase.h:239


It is main loop of related source loop which is unrolled by 16 (including vectorization).

      6.1.5.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

11% of peak computational performance is used (5.75 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.5.1.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 86.25 to 76.25 cycles (1.13x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.5.1.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is poorly vectorized.
Only 38% of vector register length is used (average across all SSE/AVX instructions).
By fully vectorizing your loop, you can lower the cost of an iteration from 86.25 to 46.52 cycles (1.85x speedup).

Details
46% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 3% of SSE/AVX loads are used in vector version.
 - 6% of SSE/AVX stores are used in vector version.
 - 80% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.
Since your execution units are vector units, only a fully vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.5.1.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by:
 - reading data from caches/RAM (load units are a bottleneck)
 - writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 86.25 to 80.38 cycles (1.07x speedup).


Workaround
 - Read less array elements
 - Write less array elements
 - Provide more information to your compiler:
  * hardcode the bounds of the corresponding 'for' loop





      6.1.5.1.4  -  Masked instructions
  ----------------------------------------------------------------------------------------------------------

Detected masked instructions.

Details
Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround
If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.


      6.1.5.1.5  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 64 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.5.1.6  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPD: 4 occurrences<<list_path_1_complex_1>>
 - VPEXTRQ: 16 occurrences<<list_path_1_complex_2>>



      6.1.5.1.7  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 36 occurrence(s)
 - Irregular (variable stride) or indirect: 9 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.5.1.8  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 60 suboptimal vector unaligned load/store instructions.


Details
 - VINSERTF64X2: 40 occurrences<<list_path_1_vec_align_1>>
 - VINSERTF64X4: 20 occurrences<<list_path_1_vec_align_2>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.5.1.9  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

72 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.5.1.10  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 496 FP arithmetical operations:
 - 192: addition or subtraction (64 inside FMA instructions)
 - 256: multiply (64 inside FMA instructions)
 - 48: divide
The binary loop is loading 2600 bytes (325 double precision FP elements).
The binary loop is storing 720 bytes (90 double precision FP elements).


      6.1.5.1.11  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.







      6.1.6  -  Loop 230 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:114-139


The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.6.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.50 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is probably not vectorized.
Only 13% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Details
Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.6.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 6.63 cycles (1.81x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.6.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.00 cycles (1.71x speedup).


      6.1.6.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.6.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 2 occurrences<<list_path_1_complex_1>>



      6.1.6.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

22 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.6.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 18 FP arithmetical operations:
 - 7: addition or subtraction (1 inside FMA instructions)
 - 8: multiply (1 inside FMA instructions)
 - 3: divide
The binary loop is loading 104 bytes (13 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.6.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.




      6.1.6.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

2% of peak computational performance is used (1.10 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.2.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 3.63 to 2.38 cycles (1.53x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.6.2.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 11% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 3.63 to 0.31 cycles (11.68x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.6.2.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.6.2.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.04x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.6.2.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 2 occurrences<<list_path_2_complex_1>>



      6.1.6.2.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.6.2.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 4 FP arithmetical operations:
 - 2: addition or subtraction
 - 2: multiply
The binary loop is loading 32 bytes (4 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.6.2.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.


      6.1.6.2.9  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N




      6.1.6.3  -  Path 3
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.50 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.3.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is probably not vectorized.
Only 13% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Details
Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.6.3.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 6.50 cycles (1.85x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.6.3.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.00 cycles (1.71x speedup).


      6.1.6.3.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.6.3.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 2 occurrences<<list_path_3_complex_1>>



      6.1.6.3.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

22 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.6.3.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 18 FP arithmetical operations:
 - 7: addition or subtraction (1 inside FMA instructions)
 - 8: multiply (1 inside FMA instructions)
 - 3: divide
The binary loop is loading 104 bytes (13 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.6.3.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.




      6.1.6.4  -  Path 4
  ----------------------------------------------------------------------------------------------------------

2% of peak computational performance is used (1.19 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.6.4.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 3.38 to 2.25 cycles (1.50x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.6.4.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
Only 11% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 3.38 to 0.30 cycles (11.43x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.6.4.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.6.4.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.04x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.6.4.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 2 occurrences<<list_path_4_complex_1>>



      6.1.6.4.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.6.4.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 4 FP arithmetical operations:
 - 2: addition or subtraction
 - 2: multiply
The binary loop is loading 32 bytes (4 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.6.4.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.


      6.1.6.4.9  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N







      6.1.7  -  Loop 309 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:51-63.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.7.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

34% of peak computational performance is used (16.67 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.7.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
83% of vector register length is used (average across all SSE/AVX instructions).


Details
80% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.



      6.1.7.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 6.00 cycles (2.00x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.7.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.00 cycles (1.71x speedup).


      6.1.7.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 24 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.7.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPD: 2 occurrences<<list_path_1_complex_1>>



      6.1.7.1.6  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 12 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 12 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.7.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

22 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.7.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 200 FP arithmetical operations:
 - 112: addition or subtraction (24 inside FMA instructions)
 - 64: multiply (24 inside FMA instructions)
 - 24: divide
The binary loop is loading 1152 bytes (144 double precision FP elements).
The binary loop is storing 128 bytes (16 double precision FP elements).


      6.1.7.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.







      6.1.8  -  Loop 187 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:43-53.

It is main loop of related source loop which is unrolled by 8 (including vectorization).

      6.1.8.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

54% of peak computational performance is used (26.18 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.8.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is partially vectorized.
Only 78% of vector register length is used (average across all SSE/AVX instructions).


Details
75% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):
 - 0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.



      6.1.8.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.8.1.3  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 80 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.8.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPD: 4 occurrences<<list_path_1_complex_1>>



      6.1.8.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 16 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 16 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.8.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

26 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.8.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 288 FP arithmetical operations:
 - 152: addition or subtraction (80 inside FMA instructions)
 - 128: multiply (80 inside FMA instructions)
 - 8: divide
The binary loop is loading 2328 bytes (291 double precision FP elements).
The binary loop is storing 256 bytes (32 double precision FP elements).


      6.1.8.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.







      6.1.9  -  Loop 232 from exec
  ==========================================================================================================

The loop is defined in:
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
 - /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:186-211


The related source loop is not unrolled or unrolled with no peel/tail loop.
This loop has 4 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):
 - hoisting them (moving them outside the loop)
 - turning them into conditional moves, MIN or MAX


Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)


      6.1.9.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.50 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is probably not vectorized.
Only 13% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Details
Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.9.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 7.13 cycles (1.68x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.9.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.13 cycles (1.68x speedup).


      6.1.9.1.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.1.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 2 occurrences<<list_path_1_complex_1>>



      6.1.9.1.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 2 occurrence(s)
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.9.1.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

22 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.9.1.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 18 FP arithmetical operations:
 - 7: addition or subtraction (1 inside FMA instructions)
 - 8: multiply (1 inside FMA instructions)
 - 3: divide
The binary loop is loading 120 bytes (15 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.9.1.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.




      6.1.9.2  -  Path 2
  ----------------------------------------------------------------------------------------------------------

2% of peak computational performance is used (1.03 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.2.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 3.88 to 2.38 cycles (1.63x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.2.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
<<image_1x64_512>>By vectorizing your loop, you can lower the cost of an iteration from 3.88 to 0.48 cycles (8.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.9.2.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.9.2.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.03x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.2.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 2 occurrences<<list_path_2_complex_1>>



      6.1.9.2.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.2.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.9.2.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 4 FP arithmetical operations:
 - 2: addition or subtraction
 - 2: multiply
The binary loop is loading 48 bytes (6 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.9.2.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.07 FP operations per loaded or stored byte.


      6.1.9.2.10  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N




      6.1.9.3  -  Path 3
  ----------------------------------------------------------------------------------------------------------

3% of peak computational performance is used (1.50 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.3.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is probably not vectorized.
Only 13% of vector register length is used (average across all SSE/AVX instructions).
By vectorizing your loop, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Details
Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.9.3.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 7.00 cycles (1.71x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.9.3.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.00 cycles (1.71x speedup).


      6.1.9.3.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Detected 1 FMA (fused multiply-add) operations.
Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.3.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 2 occurrences<<list_path_3_complex_1>>



      6.1.9.3.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 2 occurrence(s)
 - Irregular (variable stride) or indirect: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)
 - Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.



      6.1.9.3.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

22 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.9.3.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 18 FP arithmetical operations:
 - 7: addition or subtraction (1 inside FMA instructions)
 - 8: multiply (1 inside FMA instructions)
 - 3: divide
The binary loop is loading 112 bytes (14 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.9.3.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.15 FP operations per loaded or stored byte.




      6.1.9.4  -  Path 4
  ----------------------------------------------------------------------------------------------------------

2% of peak computational performance is used (1.07 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.9.4.1  -  Code clean check
  ----------------------------------------------------------------------------------------------------------

Detected a slowdown caused by scalar integer instructions (typically used for address computation).
By removing them, you can lower the cost of an iteration from 3.75 to 2.38 cycles (1.58x speedup).

Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.4.2  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is not vectorized.
8 data elements could be processed at once in vector registers.
<<image_1x64_512>>By vectorizing your loop, you can lower the cost of an iteration from 3.75 to 0.47 cycles (8.00x speedup).

Details
All SSE/AVX instructions are used in scalar version (process only one data element in vector registers).
Since your execution units are vector units, only a vectorized loop can use their full power.


Workaround
 - Try another compiler or update/tune your current one:
  * recompile with ftree-vectorize (included in O3) to enable loop vectorization (including FP reductions).
 - Remove inter-iterations dependences from your loop and make it unit-stride:
  * If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly:
C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)<<image_row_maj>>
  * If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA):
for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)



      6.1.9.4.3  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Found no such bottlenecks but see expert reports for more complex bottlenecks.




      6.1.9.4.4  -  FMA
  ----------------------------------------------------------------------------------------------------------

Presence of both ADD/SUB and MUL operations.

Workaround
Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible.
Estimated speedup by perfect pairing: 1.03x.
For instance a + b*c is a valid FMA (MUL then ADD).
However (a+b)* c cannot be translated into an FMA (ADD then MUL).




      6.1.9.4.5  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VCOMISD: 2 occurrences<<list_path_4_complex_1>>



      6.1.9.4.6  -  Slow data structures access
  ----------------------------------------------------------------------------------------------------------

Detected data structures (typically arrays) that cannot be efficiently read/written

Details
 - Constant unknown stride: 1 occurrence(s)
Non-unit stride (uncontiguous) accesses are not efficiently using data caches


Workaround
 - Try to reorganize arrays of structures to structures of arrays
 - Consider to permute loops (see vectorization gain report)



      6.1.9.4.7  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

6 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).



      6.1.9.4.8  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 4 FP arithmetical operations:
 - 2: addition or subtraction
 - 2: multiply
The binary loop is loading 40 bytes (5 double precision FP elements).
The binary loop is storing 8 bytes (1 double precision FP elements).


      6.1.9.4.9  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.08 FP operations per loaded or stored byte.


      6.1.9.4.10  -  Unroll opportunity
  ----------------------------------------------------------------------------------------------------------

Loop is potentially data access bound.

Workaround
Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N







      6.1.10  -  Loop 274 from exec
  ==========================================================================================================

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:40-45.

The related source loop is not unrolled or unrolled with no peel/tail loop.

      6.1.10.1  -  Path 1
  ----------------------------------------------------------------------------------------------------------

11% of peak computational performance is used (5.57 out of 48.00 FLOP per cycle (GFLOPS @ 1GHz))

      6.1.10.1.1  -  Vectorization
  ----------------------------------------------------------------------------------------------------------

Your loop is fully vectorized, using full register length.


Details
All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).



      6.1.10.1.2  -  Execution units bottlenecks
  ----------------------------------------------------------------------------------------------------------

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck).

By removing all these bottlenecks, you can lower the cost of an iteration from 46.00 to 16.00 cycles (2.88x speedup).


Workaround
 - Reduce the number of division or square root instructions:
  * If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
 - Check whether you really need double precision. If not, switch to single precision to speedup execution





      6.1.10.1.3  -  Expensive FP math instructions/calls
  ----------------------------------------------------------------------------------------------------------

Detected performance impact from expensive FP math instructions/calls.
By removing/reexpressing them, you can lower the cost of an iteration from 46.00 to 12.00 cycles (3.83x speedup).




      6.1.10.1.4  -  Complex instructions
  ----------------------------------------------------------------------------------------------------------

Detected COMPLEX INSTRUCTIONS.


Details
These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.
 - VMOVUPD: 8 occurrences<<list_path_1_complex_1>>



      6.1.10.1.5  -  Vector unaligned load/store instructions
  ----------------------------------------------------------------------------------------------------------

Detected 12 optimal vector unaligned load/store instructions.


Details
 - VMOVUPD: 12 occurrences<<list_path_1_vec_align_1>>


Workaround
Use vector aligned instructions:
 1) align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
 2) inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.
<<image_vec_align>>


      6.1.10.1.6  -  Type of elements and instruction set
  ----------------------------------------------------------------------------------------------------------

32 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).



      6.1.10.1.7  -  Matching between your loop (in the source code) and the binary loop
  ----------------------------------------------------------------------------------------------------------

The binary loop is composed of 256 FP arithmetical operations:
 - 192: multiply
 - 32: divide
 - 32: square root
The binary loop is loading 768 bytes (96 double precision FP elements).
The binary loop is storing 512 bytes (64 double precision FP elements).


      6.1.10.1.8  -  Arithmetic intensity
  ----------------------------------------------------------------------------------------------------------

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.





[MAQAO] Info: STOP THE REPORT GENERATION
[MAQAO] Info: 
[MAQAO] Info: If your application produces files, they can be found in directory "/beegfs/hackathon/users/eoseret/qaas_runs_test/178-661-4132/intel/CloverLeaf2.0-CXX/run/oneview_runs/multicore/gcc_6/oneview_run_1786624126"
[MAQAO] Info: 
