OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:62-66 [...]	Coverage (incl. loops): 2.62% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 62 - 66

--------------------------------------------------------------------------------

62: #pragma omp parallel for simd collapse(2)

63:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

64:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

65:         post_vol(i, j) = volume(i, j);

66:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

0x431900 PUSH	%RBP

0x431901 MOV	%RSP,%RBP

0x431904 PUSH	%R15

0x431906 PUSH	%R14

0x431908 PUSH	%R13

0x43190a PUSH	%R12

0x43190c PUSH	%RBX

0x43190d MOV	%RDI,%R15

0x431910 AND	$-0x40,%RSP

0x431914 SUB	$0x40,%RSP

0x431918 MOV	0x28(%RDI),%EAX

0x43191b MOV	0x2c(%RDI),%EDX

0x43191e MOV	0x20(%RDI),%ESI

0x431921 MOV	0x24(%R15),%ECX

0x431925 ADD	$0x4,%EDX

0x431928 LEA	-0x1(%RSI),%EDI

0x43192b LEA	-0x1(%RAX),%EBX

0x43192e MOV	%EDX,0x14(%RSP)

0x431932 MOV	%EDI,0x10(%RSP)

0x431936 CMP	%EDX,%EBX

0x431938 JGE	431f23

0x43193e MOV	%EDX,%R12D

0x431941 LEA	0x4(%RCX),%R14D

0x431945 SUB	%EBX,%R12D

0x431948 CMP	%R14D,%EDI

0x43194b JGE	431f23

0x431951 MOV	%R14D,%R8D

0x431954 SUB	%EDI,%R8D

0x431957 MOV	%R8D,0x38(%RSP)

0x43195c CALL	404630 <omp_get_num_threads@plt>

0x431961 MOV	%EAX,%R13D

0x431964 CALL	404520 <omp_get_thread_num@plt>

0x431969 MOV	0x38(%RSP),%R10D

0x43196e XOR	%EDX,%EDX

0x431970 MOV	%EAX,%R9D

0x431973 IMUL	%R10D,%R12D

0x431977 MOV	%R12D,%EAX

0x43197a DIV	%R13D

0x43197d MOV	%EAX,%R12D

0x431980 CMP	%EDX,%R9D

0x431983 JB	431f5d

0x431989 IMUL	%R12D,%R9D

0x43198d LEA	(%R9,%RDX,1),%EDI

0x431991 LEA	(%R12,%RDI,1),%R11D

0x431995 MOV	%R11D,0xc(%RSP)

0x43199a CMP	%R11D,%EDI

0x43199d JAE	431f23

0x4319a3 MOV	%EDI,%EAX

0x4319a5 XOR	%EDX,%EDX

0x4319a7 MOV	0x10(%RSP),%ESI

0x4319ab VMOVQ	0x8(%R15),%XMM13

0x4319b1 DIVL	0x38(%RSP)

0x4319b5 VMOVQ	0x18(%R15),%XMM12

0x4319bb VMOVQ	(%R15),%XMM3

0x4319c0 VMOVQ	0x10(%R15),%XMM1

0x4319c6 ADD	%EDX,%ESI

0x4319c8 LEA	(%RAX,%RBX,1),%R15D

0x4319cc SUB	%ESI,%R14D

0x4319cf MOV	%ESI,0x3c(%RSP)

0x4319d3 MOVSXD	%R15D,%RSI

0x4319d6 NOPW	%CS:(%RAX,%RAX,1)

(216) 0x4319e0 CMP	%R14D,%R12D

(216) 0x4319e3 MOV	%R14D,%EDX

(216) 0x4319e6 CMOVBE	%R12D,%EDX

(216) 0x4319ea LEA	(%RDI,%RDX,1),%R12D

(216) 0x4319ee CMP	%R12D,%EDI

(216) 0x4319f1 JAE	431f40

(216) 0x4319f7 VMOVQ	%XMM3,%R9

(216) 0x4319fc VMOVQ	%XMM13,%RBX

(216) 0x431a01 LEA	0x1(%RSI),%R10

(216) 0x431a05 LEA	-0x1(%RDX),%R15D

(216) 0x431a09 MOV	(%R9),%R11

(216) 0x431a0c VMOVQ	%XMM12,%R8

(216) 0x431a11 MOV	(%RBX),%RCX

(216) 0x431a14 MOV	%R10,0x18(%RSP)

(216) 0x431a19 MOV	(%R8),%R13

(216) 0x431a1c VMOVQ	0x10(%RBX),%XMM7

(216) 0x431a21 VMOVQ	%XMM1,%RAX

(216) 0x431a26 VMOVQ	0x10(%R8),%XMM5

(216) 0x431a2c VMOVQ	0x10(%RAX),%XMM4

(216) 0x431a31 MOV	0x10(%R9),%R14

(216) 0x431a35 IMUL	%R11,%R10

(216) 0x431a39 IMUL	%RSI,%RCX

(216) 0x431a3d IMUL	%RSI,%R13

(216) 0x431a41 IMUL	(%RAX),%RSI

(216) 0x431a45 MOV	%R10,%RBX

(216) 0x431a48 SUB	%R11,%RBX

(216) 0x431a4b MOV	%RCX,0x20(%RSP)

(216) 0x431a50 MOV	%R13,0x28(%RSP)

(216) 0x431a55 MOV	%RBX,0x30(%RSP)

(216) 0x431a5a CMP	$0x6,%R15D

(216) 0x431a5e JBE	431f50

(216) 0x431a64 MOVSXD	0x3c(%RSP),%R9

(216) 0x431a69 VMOVQ	%XMM5,%R8

(216) 0x431a6e LEA	(%RCX,%R9,1),%R11

(216) 0x431a72 VMOVQ	%XMM7,%RCX

(216) 0x431a77 LEA	(%R13,%R9,1),%RAX

(216) 0x431a7c LEA	(%RBX,%R9,1),%RBX

(216) 0x431a80 LEA	(%RCX,%R11,8),%R15

(216) 0x431a84 LEA	(%R10,%R9,1),%R11

(216) 0x431a88 VMOVQ	%XMM4,%RCX

(216) 0x431a8d ADD	%RSI,%R9

(216) 0x431a90 LEA	(%RCX,%R9,8),%RCX

(216) 0x431a94 MOV	%EDX,%R9D

(216) 0x431a97 LEA	(%R8,%RAX,8),%R13

(216) 0x431a9b XOR	%EAX,%EAX

(216) 0x431a9d SHR	$0x3,%R9D

(216) 0x431aa1 SAL	$0x6,%R9

(216) 0x431aa5 LEA	-0x40(%R9),%R8

(216) 0x431aa9 LEA	(%R14,%R11,8),%R11

(216) 0x431aad LEA	(%R14,%RBX,8),%RBX

(216) 0x431ab1 SHR	$0x6,%R8

(216) 0x431ab5 INC	%R8

(216) 0x431ab8 AND	$0x7,%R8D

(216) 0x431abc JE	431c13

(216) 0x431ac2 CMP	$0x1,%R8

(216) 0x431ac6 JE	431be2

(216) 0x431acc CMP	$0x2,%R8

(216) 0x431ad0 JE	431bba

(216) 0x431ad6 CMP	$0x3,%R8

(216) 0x431ada JE	431b92

(216) 0x431ae0 CMP	$0x4,%R8

(216) 0x431ae4 JE	431b6a

(216) 0x431aea CMP	$0x5,%R8

(216) 0x431aee JE	431b42

(216) 0x431af0 CMP	$0x6,%R8

(216) 0x431af4 JE	431b1a

(216) 0x431af6 VMOVUPD	(%R15),%ZMM6

(216) 0x431afc MOV	$0x40,%EAX

(216) 0x431b01 VMOVUPD	%ZMM6,(%R13)

(216) 0x431b08 VADDPD	(%R11),%ZMM6,%ZMM0

(216) 0x431b0e VSUBPD	(%RBX),%ZMM0,%ZMM2

(216) 0x431b14 VMOVUPD	%ZMM2,(%RCX)

(216) 0x431b1a VMOVUPD	(%R15,%RAX,1),%ZMM8

(216) 0x431b21 VMOVUPD	%ZMM8,(%R13,%RAX,1)

(216) 0x431b29 VADDPD	(%R11,%RAX,1),%ZMM8,%ZMM9

(216) 0x431b30 VSUBPD	(%RBX,%RAX,1),%ZMM9,%ZMM10

(216) 0x431b37 VMOVUPD	%ZMM10,(%RCX,%RAX,1)

(216) 0x431b3e ADD	$0x40,%RAX

(216) 0x431b42 VMOVUPD	(%R15,%RAX,1),%ZMM11

(216) 0x431b49 VMOVUPD	%ZMM11,(%R13,%RAX,1)

(216) 0x431b51 VADDPD	(%R11,%RAX,1),%ZMM11,%ZMM14

(216) 0x431b58 VSUBPD	(%RBX,%RAX,1),%ZMM14,%ZMM15

(216) 0x431b5f VMOVUPD	%ZMM15,(%RCX,%RAX,1)

(216) 0x431b66 ADD	$0x40,%RAX

(216) 0x431b6a VMOVUPD	(%R15,%RAX,1),%ZMM6

(216) 0x431b71 VMOVUPD	%ZMM6,(%R13,%RAX,1)

(216) 0x431b79 VADDPD	(%R11,%RAX,1),%ZMM6,%ZMM0

(216) 0x431b80 VSUBPD	(%RBX,%RAX,1),%ZMM0,%ZMM2

(216) 0x431b87 VMOVUPD	%ZMM2,(%RCX,%RAX,1)

(216) 0x431b8e ADD	$0x40,%RAX

(216) 0x431b92 VMOVUPD	(%R15,%RAX,1),%ZMM8

(216) 0x431b99 VMOVUPD	%ZMM8,(%R13,%RAX,1)

(216) 0x431ba1 VADDPD	(%R11,%RAX,1),%ZMM8,%ZMM9

(216) 0x431ba8 VSUBPD	(%RBX,%RAX,1),%ZMM9,%ZMM10

(216) 0x431baf VMOVUPD	%ZMM10,(%RCX,%RAX,1)

(216) 0x431bb6 ADD	$0x40,%RAX

(216) 0x431bba VMOVUPD	(%R15,%RAX,1),%ZMM11

(216) 0x431bc1 VMOVUPD	%ZMM11,(%R13,%RAX,1)

(216) 0x431bc9 VADDPD	(%R11,%RAX,1),%ZMM11,%ZMM14

(216) 0x431bd0 VSUBPD	(%RBX,%RAX,1),%ZMM14,%ZMM15

(216) 0x431bd7 VMOVUPD	%ZMM15,(%RCX,%RAX,1)

(216) 0x431bde ADD	$0x40,%RAX

(216) 0x431be2 VMOVUPD	(%R15,%RAX,1),%ZMM6

(216) 0x431be9 VMOVUPD	%ZMM6,(%R13,%RAX,1)

(216) 0x431bf1 VADDPD	(%R11,%RAX,1),%ZMM6,%ZMM0

(216) 0x431bf8 VSUBPD	(%RBX,%RAX,1),%ZMM0,%ZMM2

(216) 0x431bff VMOVUPD	%ZMM2,(%RCX,%RAX,1)

(216) 0x431c06 ADD	$0x40,%RAX

(216) 0x431c0a CMP	%R9,%RAX

(216) 0x431c0d JE	431d5e

  (217) 0x431c13 VMOVUPD	(%R15,%RAX,1),%ZMM8

  (217) 0x431c1a VMOVUPD	%ZMM8,(%R13,%RAX,1)

  (217) 0x431c22 VADDPD	(%R11,%RAX,1),%ZMM8,%ZMM9

  (217) 0x431c29 VSUBPD	(%RBX,%RAX,1),%ZMM9,%ZMM10

  (217) 0x431c30 VMOVUPD	%ZMM10,(%RCX,%RAX,1)

  (217) 0x431c37 VMOVUPD	0x40(%R15,%RAX,1),%ZMM11

  (217) 0x431c3f VMOVUPD	%ZMM11,0x40(%R13,%RAX,1)

  (217) 0x431c47 VADDPD	0x40(%R11,%RAX,1),%ZMM11,%ZMM14

  (217) 0x431c4f VSUBPD	0x40(%RBX,%RAX,1),%ZMM14,%ZMM15

  (217) 0x431c57 VMOVUPD	%ZMM15,0x40(%RCX,%RAX,1)

  (217) 0x431c5f VMOVUPD	0x80(%R15,%RAX,1),%ZMM6

  (217) 0x431c67 VMOVUPD	%ZMM6,0x80(%R13,%RAX,1)

  (217) 0x431c6f VADDPD	0x80(%R11,%RAX,1),%ZMM6,%ZMM0

  (217) 0x431c77 VSUBPD	0x80(%RBX,%RAX,1),%ZMM0,%ZMM2

  (217) 0x431c7f VMOVUPD	%ZMM2,0x80(%RCX,%RAX,1)

  (217) 0x431c87 VMOVUPD	0xc0(%R15,%RAX,1),%ZMM8

  (217) 0x431c8f VMOVUPD	%ZMM8,0xc0(%R13,%RAX,1)

  (217) 0x431c97 VADDPD	0xc0(%R11,%RAX,1),%ZMM8,%ZMM9

  (217) 0x431c9f VSUBPD	0xc0(%RBX,%RAX,1),%ZMM9,%ZMM10

  (217) 0x431ca7 VMOVUPD	%ZMM10,0xc0(%RCX,%RAX,1)

  (217) 0x431caf VMOVUPD	0x100(%R15,%RAX,1),%ZMM11

  (217) 0x431cb7 VMOVUPD	%ZMM11,0x100(%R13,%RAX,1)

  (217) 0x431cbf VADDPD	0x100(%R11,%RAX,1),%ZMM11,%ZMM14

  (217) 0x431cc7 VSUBPD	0x100(%RBX,%RAX,1),%ZMM14,%ZMM15

  (217) 0x431ccf VMOVUPD	%ZMM15,0x100(%RCX,%RAX,1)

  (217) 0x431cd7 VMOVUPD	0x140(%R15,%RAX,1),%ZMM6

  (217) 0x431cdf VMOVUPD	%ZMM6,0x140(%R13,%RAX,1)

  (217) 0x431ce7 VADDPD	0x140(%R11,%RAX,1),%ZMM6,%ZMM0

  (217) 0x431cef VSUBPD	0x140(%RBX,%RAX,1),%ZMM0,%ZMM2

  (217) 0x431cf7 VMOVUPD	%ZMM2,0x140(%RCX,%RAX,1)

  (217) 0x431cff VMOVUPD	0x180(%R15,%RAX,1),%ZMM8

  (217) 0x431d07 VMOVUPD	%ZMM8,0x180(%R13,%RAX,1)

  (217) 0x431d0f VADDPD	0x180(%R11,%RAX,1),%ZMM8,%ZMM9

  (217) 0x431d17 VSUBPD	0x180(%RBX,%RAX,1),%ZMM9,%ZMM10

  (217) 0x431d1f VMOVUPD	%ZMM10,0x180(%RCX,%RAX,1)

  (217) 0x431d27 VMOVUPD	0x1c0(%R15,%RAX,1),%ZMM11

  (217) 0x431d2f VMOVUPD	%ZMM11,0x1c0(%R13,%RAX,1)

  (217) 0x431d37 VADDPD	0x1c0(%R11,%RAX,1),%ZMM11,%ZMM14

  (217) 0x431d3f VSUBPD	0x1c0(%RBX,%RAX,1),%ZMM14,%ZMM15

  (217) 0x431d47 VMOVUPD	%ZMM15,0x1c0(%RCX,%RAX,1)

  (217) 0x431d4f ADD	$0x200,%RAX

  (217) 0x431d55 CMP	%R9,%RAX

  (217) 0x431d58 JNE	431c13

(216) 0x431d5e MOV	0x3c(%RSP),%R15D

(216) 0x431d63 MOV	%EDX,%R13D

(216) 0x431d66 AND	$-0x8,%R13D

(216) 0x431d6a ADD	%R13D,%EDI

(216) 0x431d6d LEA	(%R13,%R15,1),%R8D

(216) 0x431d72 TEST	$0x7,%DL

(216) 0x431d75 JE	431ee8

(216) 0x431d7b SUB	%R13D,%EDX

(216) 0x431d7e LEA	-0x1(%RDX),%R11D

(216) 0x431d82 CMP	$0x2,%R11D

(216) 0x431d86 JBE	431dff

(216) 0x431d88 MOVSXD	0x3c(%RSP),%RCX

(216) 0x431d8d MOV	0x20(%RSP),%RBX

(216) 0x431d92 MOV	0x28(%RSP),%R15

(216) 0x431d97 VMOVQ	%XMM7,%RAX

(216) 0x431d9c LEA	(%RBX,%RCX,1),%R9

(216) 0x431da0 LEA	(%R15,%RCX,1),%R11

(216) 0x431da4 VMOVQ	%XMM5,%RBX

(216) 0x431da9 ADD	%R13,%R9

(216) 0x431dac ADD	%R13,%R11

(216) 0x431daf VMOVUPD	(%RAX,%R9,8),%YMM6

(216) 0x431db5 MOV	0x30(%RSP),%RAX

(216) 0x431dba LEA	(%R10,%RCX,1),%R9

(216) 0x431dbe ADD	%R13,%R9

(216) 0x431dc1 LEA	(%RAX,%RCX,1),%R15

(216) 0x431dc5 ADD	%RSI,%RCX

(216) 0x431dc8 VMOVUPD	%YMM6,(%RBX,%R11,8)

(216) 0x431dce ADD	%R13,%R15

(216) 0x431dd1 VADDPD	(%R14,%R9,8),%YMM6,%YMM0

(216) 0x431dd7 ADD	%R13,%RCX

(216) 0x431dda VSUBPD	(%R14,%R15,8),%YMM0,%YMM2

(216) 0x431de0 VMOVQ	%XMM4,%R13

(216) 0x431de5 VMOVUPD	%YMM2,(%R13,%RCX,8)

(216) 0x431dec MOV	%EDX,%ECX

(216) 0x431dee AND	$-0x4,%ECX

(216) 0x431df1 ADD	%ECX,%R8D

(216) 0x431df4 ADD	%ECX,%EDI

(216) 0x431df6 AND	$0x3,%EDX

(216) 0x431df9 JE	431ee8

(216) 0x431dff MOV	0x20(%RSP),%RBX

(216) 0x431e04 MOVSXD	%R8D,%R9

(216) 0x431e07 VMOVQ	%XMM7,%R11

(216) 0x431e0c MOV	0x28(%RSP),%R15

(216) 0x431e11 LEA	(%R10,%R9,1),%RCX

(216) 0x431e15 VMOVQ	%XMM5,%R13

(216) 0x431e1a LEA	(%RBX,%R9,1),%RDX

(216) 0x431e1e LEA	(%R15,%R9,1),%RAX

(216) 0x431e22 VMOVSD	(%R11,%RDX,8),%XMM8

(216) 0x431e28 MOV	0x30(%RSP),%R11

(216) 0x431e2d LEA	(%RSI,%R9,1),%RDX

(216) 0x431e31 VMOVSD	%XMM8,(%R13,%RAX,8)

(216) 0x431e38 LEA	0x1(%RDI),%EAX

(216) 0x431e3b VADDSD	(%R14,%RCX,8),%XMM8,%XMM9

(216) 0x431e41 ADD	%R11,%R9

(216) 0x431e44 VSUBSD	(%R14,%R9,8),%XMM9,%XMM10

(216) 0x431e4a VMOVQ	%XMM4,%R9

(216) 0x431e4f VMOVSD	%XMM10,(%R9,%RDX,8)

(216) 0x431e55 CMP	%R12D,%EAX

(216) 0x431e58 JAE	431ee8

(216) 0x431e5e LEA	0x1(%R8),%EAX

(216) 0x431e62 VMOVQ	%XMM7,%RDX

(216) 0x431e67 VMOVQ	%XMM5,%RCX

(216) 0x431e6c ADD	$0x2,%EDI

(216) 0x431e6f CLTQ

(216) 0x431e71 LEA	(%RBX,%RAX,1),%R13

(216) 0x431e75 LEA	(%R15,%RAX,1),%R9

(216) 0x431e79 VMOVSD	(%RDX,%R13,8),%XMM11

(216) 0x431e7f LEA	(%RSI,%RAX,1),%R13

(216) 0x431e83 VMOVSD	%XMM11,(%RCX,%R9,8)

(216) 0x431e89 LEA	(%R10,%RAX,1),%RDX

(216) 0x431e8d MOV	%R11,%R9

(216) 0x431e90 ADD	%R11,%RAX

(216) 0x431e93 VMOVQ	%XMM4,%R11

(216) 0x431e98 VADDSD	(%R14,%RDX,8),%XMM11,%XMM14

(216) 0x431e9e VSUBSD	(%R14,%RAX,8),%XMM14,%XMM15

(216) 0x431ea4 VMOVSD	%XMM15,(%R11,%R13,8)

(216) 0x431eaa CMP	%R12D,%EDI

(216) 0x431ead JAE	431ee8

(216) 0x431eaf ADD	$0x2,%R8D

(216) 0x431eb3 MOVSXD	%R8D,%RDI

(216) 0x431eb6 VMOVQ	%XMM7,%R8

(216) 0x431ebb ADD	%RDI,%RBX

(216) 0x431ebe ADD	%RDI,%R15

(216) 0x431ec1 ADD	%RDI,%RSI

(216) 0x431ec4 ADD	%RDI,%R10

(216) 0x431ec7 ADD	%RDI,%R9

(216) 0x431eca VMOVSD	(%R8,%RBX,8),%XMM7

(216) 0x431ed0 VMOVSD	%XMM7,(%RCX,%R15,8)

(216) 0x431ed6 VADDSD	(%R14,%R10,8),%XMM7,%XMM5

(216) 0x431edc VSUBSD	(%R14,%R9,8),%XMM5,%XMM6

(216) 0x431ee2 VMOVSD	%XMM6,(%R11,%RSI,8)

(216) 0x431ee8 MOV	%R12D,%EDI

(216) 0x431eeb MOV	0x18(%RSP),%RSI

(216) 0x431ef0 CMP	%ESI,0x14(%RSP)

(216) 0x431ef4 JLE	431f20

(216) 0x431ef6 MOV	0xc(%RSP),%R12D

(216) 0x431efb MOV	0x10(%RSP),%R10D

(216) 0x431f00 MOV	0x38(%RSP),%R14D

(216) 0x431f05 SUB	%EDI,%R12D

(216) 0x431f08 MOV	%R10D,0x3c(%RSP)

(216) 0x431f0d JMP	4319e0

0x431f12 NOPW	%CS:(%RAX,%RAX,1)

0x431f1d NOPL	(%RAX)

0x431f20 VZEROUPPER

0x431f23 LEA	-0x28(%RBP),%RSP

0x431f27 POP	%RBX

0x431f28 POP	%R12

0x431f2a POP	%R13

0x431f2c POP	%R14

0x431f2e POP	%R15

0x431f30 POP	%RBP

0x431f31 RET

0x431f32 NOPW	%CS:(%RAX,%RAX,1)

0x431f3d NOPL	(%RAX)

(216) 0x431f40 LEA	0x1(%RSI),%R14

(216) 0x431f44 MOV	%R14,0x18(%RSP)

(216) 0x431f49 JMP	431eeb

0x431f4b NOPL	(%RAX,%RAX,1)

(216) 0x431f50 MOV	0x3c(%RSP),%R8D

(216) 0x431f55 XOR	%R13D,%R13D

(216) 0x431f58 JMP	431d7b

0x431f5d INC	%R12D

0x431f60 XOR	%EDX,%EDX

0x431f62 JMP	431989

0x431f67 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.81+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.13+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:80	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:239	exec
○	advection(global_variables&)	advection.cpp:99	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.11+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:80	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:101	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:62-66
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:62-66

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.88 cycles (6.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.25 cycles (1.30x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:65

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	79
nb uops	76
loop length	294
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.50
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (5.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 431900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%R15),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 431f23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 431f23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x38(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10D,%R12D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 431f5d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x65d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R12D,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R9,%RDX,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R12,%RDI,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R11D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R11D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 431f23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVQ 0x8(%R15),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x38(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x18(%R15),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ (%R15),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R15),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RBX,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %ESI,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %R15D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 431989 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x89>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:62-66
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:62-66

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.88 cycles (6.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.25 cycles (1.30x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:64
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:65

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	79
nb uops	76
loop length	294
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.50
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (5.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 431900

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%R15),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 431f23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 431f23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x38(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10D,%R12D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 431f5d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x65d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R12D,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R9,%RDX,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R12,%RDI,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R11D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R11D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 431f23 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVQ 0x8(%R15),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x38(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x18(%R15),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ (%R15),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R15),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RBX,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %ESI,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %R15D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 431989 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.2+0x89>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.62	0.96
▼Loop 216 - advec_mom.cpp:62-66 - exec–	0.00	0.01
○Loop 217 - advec_mom.cpp:65-66 - exec	2.62	0.96

Report Configuration

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Workaround

Expensive FP math instructions/calls

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code