OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:53-57 [...]	Coverage (incl. loops): 3.04% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 53 - 57

--------------------------------------------------------------------------------

53: #pragma omp parallel for simd collapse(2)

54:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

55:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

56:         post_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

57:         pre_vol(i, j) = post_vol(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

0x431280 PUSH	%RBP

0x431281 MOV	%RSP,%RBP

0x431284 PUSH	%R15

0x431286 PUSH	%R14

0x431288 PUSH	%R13

0x43128a PUSH	%R12

0x43128c PUSH	%RBX

0x43128d MOV	%RDI,%R14

0x431290 AND	$-0x40,%RSP

0x431294 ADD	$-0x80,%RSP

0x431298 MOV	0x30(%RDI),%EAX

0x43129b MOV	0x34(%RDI),%ECX

0x43129e MOV	0x28(%RDI),%EDI

0x4312a1 MOV	0x2c(%R14),%EDX

0x4312a5 ADD	$0x4,%ECX

0x4312a8 DEC	%EDI

0x4312aa LEA	-0x1(%RAX),%R15D

0x4312ae MOV	%ECX,0x38(%RSP)

0x4312b2 MOV	%EDI,0x34(%RSP)

0x4312b6 CMP	%ECX,%R15D

0x4312b9 JGE	4318b3

0x4312bf MOV	%ECX,%R12D

0x4312c2 LEA	0x4(%RDX),%R13D

0x4312c6 SUB	%R15D,%R12D

0x4312c9 CMP	%R13D,%EDI

0x4312cc JGE	4318b3

0x4312d2 MOV	%R13D,%EBX

0x4312d5 SUB	%EDI,%EBX

0x4312d7 MOV	%EBX,0x3c(%RSP)

0x4312db CALL	404630 <omp_get_num_threads@plt>

0x4312e0 MOV	%EAX,%EBX

0x4312e2 CALL	404520 <omp_get_thread_num@plt>

0x4312e7 MOV	0x3c(%RSP),%R8D

0x4312ec XOR	%EDX,%EDX

0x4312ee MOV	%EAX,%ESI

0x4312f0 IMUL	%R8D,%R12D

0x4312f4 MOV	%R12D,%EAX

0x4312f7 DIV	%EBX

0x4312f9 MOV	%EAX,%ECX

0x4312fb CMP	%EDX,%ESI

0x4312fd JB	4318ed

0x431303 IMUL	%ECX,%ESI

0x431306 LEA	(%RSI,%RDX,1),%EDI

0x431309 LEA	(%RCX,%RDI,1),%R9D

0x43130d MOV	%R9D,0x30(%RSP)

0x431312 CMP	%R9D,%EDI

0x431315 JAE	4318b3

0x43131b MOV	%EDI,%EAX

0x43131d XOR	%EDX,%EDX

0x43131f MOV	0x34(%RSP),%R10D

0x431324 VMOVQ	0x10(%R14),%XMM16

0x43132b DIVL	0x3c(%RSP)

0x43132f VMOVQ	(%R14),%XMM15

0x431334 VMOVQ	0x20(%R14),%XMM14

0x43133a VMOVQ	0x8(%R14),%XMM13

0x431340 VMOVQ	0x18(%R14),%XMM12

0x431346 ADD	%R10D,%EDX

0x431349 LEA	(%RAX,%R15,1),%R11D

0x43134d SUB	%EDX,%R13D

0x431350 MOVSXD	%R11D,%RSI

0x431353 MOV	%EDX,0x7c(%RSP)

0x431357 NOPW	(%RAX,%RAX,1)

(214) 0x431360 CMP	%R13D,%ECX

(214) 0x431363 MOV	%R13D,%EDX

(214) 0x431366 CMOVBE	%ECX,%EDX

(214) 0x431369 LEA	(%RDI,%RDX,1),%R13D

(214) 0x43136d MOV	%R13D,0x78(%RSP)

(214) 0x431372 CMP	%R13D,%EDI

(214) 0x431375 JAE	4318d0

(214) 0x43137b VMOVQ	%XMM16,%R15

(214) 0x431381 VMOVQ	%XMM14,%R12

(214) 0x431386 LEA	0x1(%RSI),%R11

(214) 0x43138a VMOVQ	%XMM15,%RCX

(214) 0x43138f MOV	(%R15),%RBX

(214) 0x431392 MOV	(%R12),%R13

(214) 0x431396 VMOVQ	%XMM13,%R8

(214) 0x43139b MOV	(%RCX),%R9

(214) 0x43139e MOV	(%R8),%RAX

(214) 0x4313a1 VMOVQ	%XMM12,%R14

(214) 0x4313a6 MOV	%R11,0x40(%RSP)

(214) 0x4313ab VMOVQ	0x10(%R15),%XMM19

(214) 0x4313b2 VMOVQ	0x10(%R12),%XMM11

(214) 0x4313b9 MOV	0x10(%RCX),%R10

(214) 0x4313bd MOV	0x10(%R8),%R12

(214) 0x4313c1 VMOVQ	0x10(%R14),%XMM3

(214) 0x4313c7 IMUL	%RSI,%RBX

(214) 0x4313cb IMUL	%RSI,%R9

(214) 0x4313cf IMUL	%RSI,%R13

(214) 0x4313d3 IMUL	(%R14),%RSI

(214) 0x4313d7 MOV	%RBX,0x48(%RSP)

(214) 0x4313dc IMUL	%RAX,%R11

(214) 0x4313e0 MOV	%R9,0x50(%RSP)

(214) 0x4313e5 MOV	%R13,0x58(%RSP)

(214) 0x4313ea MOV	%R11,%R15

(214) 0x4313ed MOV	%R11,0x70(%RSP)

(214) 0x4313f2 SUB	%RAX,%R15

(214) 0x4313f5 MOV	%RSI,0x68(%RSP)

(214) 0x4313fa LEA	-0x1(%RDX),%ESI

(214) 0x4313fd MOV	%R15,0x60(%RSP)

(214) 0x431402 CMP	$0x6,%ESI

(214) 0x431405 JBE	4318e0

(214) 0x43140b MOVSXD	0x7c(%RSP),%RAX

(214) 0x431410 VMOVQ	%XMM11,%R14

(214) 0x431415 LEA	(%RBX,%RAX,1),%RCX

(214) 0x431419 VMOVQ	%XMM19,%RBX

(214) 0x43141f LEA	(%R13,%RAX,1),%R13

(214) 0x431424 LEA	(%R11,%RAX,1),%R11

(214) 0x431428 LEA	(%R15,%RAX,1),%R15

(214) 0x43142c LEA	(%RBX,%RCX,8),%R8

(214) 0x431430 MOV	0x68(%RSP),%RCX

(214) 0x431435 LEA	(%R14,%R13,8),%RBX

(214) 0x431439 LEA	(%R12,%R11,8),%R13

(214) 0x43143d LEA	(%R12,%R15,8),%R11

(214) 0x431441 MOV	%EDX,%R15D

(214) 0x431444 LEA	0x1(%R9,%RAX,1),%RSI

(214) 0x431449 SHR	$0x3,%R15D

(214) 0x43144d VMOVQ	%XMM3,%R14

(214) 0x431452 SAL	$0x6,%R15

(214) 0x431456 ADD	%RCX,%RAX

(214) 0x431459 LEA	(%R14,%RAX,8),%RCX

(214) 0x43145d LEA	-0x40(%R15),%R14

(214) 0x431461 XOR	%EAX,%EAX

(214) 0x431463 SHR	$0x6,%R14

(214) 0x431467 SAL	$0x3,%RSI

(214) 0x43146b INC	%R14

(214) 0x43146e LEA	(%R10,%RSI,1),%R9

(214) 0x431472 LEA	-0x8(%R10,%RSI,1),%RSI

(214) 0x431477 AND	$0x3,%R14D

(214) 0x43147b JE	431544

(214) 0x431481 CMP	$0x1,%R14

(214) 0x431485 JE	4314ff

(214) 0x431487 CMP	$0x2,%R14

(214) 0x43148b JE	4314c3

(214) 0x43148d VMOVUPD	(%R8),%ZMM17

(214) 0x431493 VADDPD	(%R9),%ZMM17,%ZMM18

(214) 0x431499 MOV	$0x40,%EAX

(214) 0x43149e VSUBPD	(%RSI),%ZMM18,%ZMM20

(214) 0x4314a4 VMOVUPD	%ZMM20,(%RBX)

(214) 0x4314aa VMOVUPD	(%R13),%ZMM21

(214) 0x4314b1 VSUBPD	(%R11),%ZMM21,%ZMM22

(214) 0x4314b7 VADDPD	%ZMM20,%ZMM22,%ZMM23

(214) 0x4314bd VMOVUPD	%ZMM23,(%RCX)

(214) 0x4314c3 VMOVUPD	(%R8,%RAX,1),%ZMM24

(214) 0x4314ca VADDPD	(%R9,%RAX,1),%ZMM24,%ZMM25

(214) 0x4314d1 VSUBPD	(%RSI,%RAX,1),%ZMM25,%ZMM26

(214) 0x4314d8 VMOVUPD	%ZMM26,(%RBX,%RAX,1)

(214) 0x4314df VMOVUPD	(%R13,%RAX,1),%ZMM27

(214) 0x4314e7 VSUBPD	(%R11,%RAX,1),%ZMM27,%ZMM28

(214) 0x4314ee VADDPD	%ZMM26,%ZMM28,%ZMM29

(214) 0x4314f4 VMOVUPD	%ZMM29,(%RCX,%RAX,1)

(214) 0x4314fb ADD	$0x40,%RAX

(214) 0x4314ff VMOVUPD	(%R8,%RAX,1),%ZMM30

(214) 0x431506 VADDPD	(%R9,%RAX,1),%ZMM30,%ZMM31

(214) 0x43150d VSUBPD	(%RSI,%RAX,1),%ZMM31,%ZMM17

(214) 0x431514 VMOVUPD	%ZMM17,(%RBX,%RAX,1)

(214) 0x43151b VMOVUPD	(%R13,%RAX,1),%ZMM18

(214) 0x431523 VSUBPD	(%R11,%RAX,1),%ZMM18,%ZMM20

(214) 0x43152a VADDPD	%ZMM17,%ZMM20,%ZMM21

(214) 0x431530 VMOVUPD	%ZMM21,(%RCX,%RAX,1)

(214) 0x431537 ADD	$0x40,%RAX

(214) 0x43153b CMP	%R15,%RAX

(214) 0x43153e JE	431645

  (215) 0x431544 VMOVUPD	(%R8,%RAX,1),%ZMM0

  (215) 0x43154b VADDPD	(%R9,%RAX,1),%ZMM0,%ZMM1

  (215) 0x431552 VSUBPD	(%RSI,%RAX,1),%ZMM1,%ZMM2

  (215) 0x431559 VMOVUPD	%ZMM2,(%RBX,%RAX,1)

  (215) 0x431560 VMOVUPD	(%R13,%RAX,1),%ZMM22

  (215) 0x431568 VSUBPD	(%R11,%RAX,1),%ZMM22,%ZMM23

  (215) 0x43156f VADDPD	%ZMM2,%ZMM23,%ZMM24

  (215) 0x431575 VMOVUPD	%ZMM24,(%RCX,%RAX,1)

  (215) 0x43157c VMOVUPD	0x40(%R8,%RAX,1),%ZMM4

  (215) 0x431584 VADDPD	0x40(%R9,%RAX,1),%ZMM4,%ZMM5

  (215) 0x43158c VSUBPD	0x40(%RSI,%RAX,1),%ZMM5,%ZMM6

  (215) 0x431594 VMOVUPD	%ZMM6,0x40(%RBX,%RAX,1)

  (215) 0x43159c VMOVUPD	0x40(%R13,%RAX,1),%ZMM25

  (215) 0x4315a4 VSUBPD	0x40(%R11,%RAX,1),%ZMM25,%ZMM26

  (215) 0x4315ac VADDPD	%ZMM6,%ZMM26,%ZMM27

  (215) 0x4315b2 VMOVUPD	%ZMM27,0x40(%RCX,%RAX,1)

  (215) 0x4315ba VMOVUPD	0x80(%R8,%RAX,1),%ZMM7

  (215) 0x4315c2 VADDPD	0x80(%R9,%RAX,1),%ZMM7,%ZMM8

  (215) 0x4315ca VSUBPD	0x80(%RSI,%RAX,1),%ZMM8,%ZMM9

  (215) 0x4315d2 VMOVUPD	%ZMM9,0x80(%RBX,%RAX,1)

  (215) 0x4315da VMOVUPD	0x80(%R13,%RAX,1),%ZMM28

  (215) 0x4315e2 VSUBPD	0x80(%R11,%RAX,1),%ZMM28,%ZMM29

  (215) 0x4315ea VADDPD	%ZMM9,%ZMM29,%ZMM30

  (215) 0x4315f0 VMOVUPD	%ZMM30,0x80(%RCX,%RAX,1)

  (215) 0x4315f8 VMOVUPD	0xc0(%R8,%RAX,1),%ZMM10

  (215) 0x431600 VADDPD	0xc0(%R9,%RAX,1),%ZMM10,%ZMM0

  (215) 0x431608 VSUBPD	0xc0(%RSI,%RAX,1),%ZMM0,%ZMM1

  (215) 0x431610 VMOVUPD	%ZMM1,0xc0(%RBX,%RAX,1)

  (215) 0x431618 VMOVUPD	0xc0(%R13,%RAX,1),%ZMM31

  (215) 0x431620 VSUBPD	0xc0(%R11,%RAX,1),%ZMM31,%ZMM17

  (215) 0x431628 VADDPD	%ZMM1,%ZMM17,%ZMM18

  (215) 0x43162e VMOVUPD	%ZMM18,0xc0(%RCX,%RAX,1)

  (215) 0x431636 ADD	$0x100,%RAX

  (215) 0x43163c CMP	%R15,%RAX

  (215) 0x43163f JNE	431544

(214) 0x431645 MOV	0x7c(%RSP),%R8D

(214) 0x43164a MOV	%EDX,%R9D

(214) 0x43164d AND	$-0x8,%R9D

(214) 0x431651 ADD	%R9D,%EDI

(214) 0x431654 LEA	(%R9,%R8,1),%R14D

(214) 0x431658 TEST	$0x7,%DL

(214) 0x43165b JE	431878

(214) 0x431661 SUB	%R9D,%EDX

(214) 0x431664 LEA	-0x1(%RDX),%ESI

(214) 0x431667 CMP	$0x2,%ESI

(214) 0x43166a JBE	431713

(214) 0x431670 MOVSXD	0x7c(%RSP),%R13

(214) 0x431675 MOV	0x50(%RSP),%RBX

(214) 0x43167a MOV	0x48(%RSP),%R15

(214) 0x43167f VMOVQ	%XMM19,%R8

(214) 0x431685 MOV	0x58(%RSP),%RSI

(214) 0x43168a LEA	(%RBX,%R13,1),%R11

(214) 0x43168e LEA	(%R15,%R13,1),%RAX

(214) 0x431692 VMOVQ	%XMM11,%RBX

(214) 0x431697 LEA	0x1(%R9,%R11,1),%RCX

(214) 0x43169c ADD	%R9,%RAX

(214) 0x43169f LEA	(%RSI,%R13,1),%R11

(214) 0x4316a3 MOV	0x68(%RSP),%RSI

(214) 0x4316a8 VMOVUPD	(%R10,%RCX,8),%YMM2

(214) 0x4316ae VSUBPD	-0x8(%R10,%RCX,8),%YMM2,%YMM4

(214) 0x4316b5 MOV	0x70(%RSP),%RCX

(214) 0x4316ba ADD	%R9,%R11

(214) 0x4316bd VADDPD	(%R8,%RAX,8),%YMM4,%YMM5

(214) 0x4316c3 MOV	0x60(%RSP),%RAX

(214) 0x4316c8 LEA	(%RCX,%R13,1),%R15

(214) 0x4316cc LEA	(%RAX,%R13,1),%R8

(214) 0x4316d0 ADD	%R9,%R15

(214) 0x4316d3 ADD	%RSI,%R13

(214) 0x4316d6 ADD	%R9,%R8

(214) 0x4316d9 ADD	%R9,%R13

(214) 0x4316dc VMOVQ	%XMM3,%R9

(214) 0x4316e1 VMOVUPD	%YMM5,(%RBX,%R11,8)

(214) 0x4316e7 VMOVUPD	(%R12,%R15,8),%YMM6

(214) 0x4316ed VSUBPD	(%R12,%R8,8),%YMM6,%YMM7

(214) 0x4316f3 VADDPD	%YMM5,%YMM7,%YMM8

(214) 0x4316f7 VMOVUPD	%YMM8,(%R9,%R13,8)

(214) 0x4316fd MOV	%EDX,%R13D

(214) 0x431700 AND	$-0x4,%R13D

(214) 0x431704 ADD	%R13D,%R14D

(214) 0x431707 ADD	%R13D,%EDI

(214) 0x43170a AND	$0x3,%EDX

(214) 0x43170d JE	431878

(214) 0x431713 MOV	0x50(%RSP),%RBX

(214) 0x431718 MOV	0x48(%RSP),%R8

(214) 0x43171d LEA	0x1(%R14),%EDX

(214) 0x431721 MOVSXD	%R14D,%RAX

(214) 0x431724 MOVSXD	%EDX,%RDX

(214) 0x431727 VMOVQ	%XMM19,%R9

(214) 0x43172d LEA	(%RBX,%RDX,1),%R11

(214) 0x431731 LEA	(%RBX,%RAX,1),%R15

(214) 0x431735 LEA	(%R8,%RAX,1),%RSI

(214) 0x431739 LEA	(%R10,%R11,8),%RCX

(214) 0x43173d VMOVQ	%XMM11,%R11

(214) 0x431742 VMOVSD	(%RCX),%XMM10

(214) 0x431746 VSUBSD	(%R10,%R15,8),%XMM10,%XMM0

(214) 0x43174c VADDSD	(%R9,%RSI,8),%XMM0,%XMM1

(214) 0x431752 MOV	0x58(%RSP),%R9

(214) 0x431757 VMOVQ	%RCX,%XMM9

(214) 0x43175c MOV	0x60(%RSP),%RCX

(214) 0x431761 LEA	(%R9,%RAX,1),%R13

(214) 0x431765 VMOVSD	%XMM1,(%R11,%R13,8)

(214) 0x43176b MOV	0x70(%RSP),%R11

(214) 0x431770 MOV	0x68(%RSP),%R13

(214) 0x431775 LEA	(%R11,%RAX,1),%RSI

(214) 0x431779 LEA	(%R13,%RAX,1),%R15

(214) 0x43177e ADD	%RCX,%RAX

(214) 0x431781 VMOVSD	(%R12,%RSI,8),%XMM2

(214) 0x431787 MOV	0x78(%RSP),%ESI

(214) 0x43178b VSUBSD	(%R12,%RAX,8),%XMM2,%XMM4

(214) 0x431791 VMOVQ	%XMM3,%RAX

(214) 0x431796 VADDSD	%XMM1,%XMM4,%XMM5

(214) 0x43179a VMOVSD	%XMM5,(%RAX,%R15,8)

(214) 0x4317a0 LEA	0x1(%RDI),%R15D

(214) 0x4317a4 CMP	%ESI,%R15D

(214) 0x4317a7 JAE	431878

(214) 0x4317ad LEA	0x2(%R14),%EAX

(214) 0x4317b1 LEA	(%RDX,%R8,1),%RSI

(214) 0x4317b5 ADD	$0x2,%EDI

(214) 0x4317b8 CLTQ

(214) 0x4317ba LEA	(%RBX,%RAX,1),%RCX

(214) 0x4317be LEA	(%R10,%RCX,8),%R15

(214) 0x4317c2 VMOVQ	%XMM19,%RCX

(214) 0x4317c8 VMOVSD	(%RCX,%RSI,8),%XMM6

(214) 0x4317cd VMOVQ	%XMM9,%RSI

(214) 0x4317d2 LEA	(%R9,%RDX,1),%RCX

(214) 0x4317d6 VADDSD	(%R15),%XMM6,%XMM7

(214) 0x4317db VSUBSD	(%RSI),%XMM7,%XMM8

(214) 0x4317df VMOVQ	%XMM11,%RSI

(214) 0x4317e4 VMOVSD	%XMM8,(%RSI,%RCX,8)

(214) 0x4317e9 LEA	(%R11,%RDX,1),%RSI

(214) 0x4317ed MOV	0x60(%RSP),%R11

(214) 0x4317f2 LEA	(%R13,%RDX,1),%RCX

(214) 0x4317f7 VMOVSD	(%R12,%RSI,8),%XMM9

(214) 0x4317fd ADD	%R11,%RDX

(214) 0x431800 VSUBSD	(%R12,%RDX,8),%XMM9,%XMM10

(214) 0x431806 VMOVQ	%XMM3,%RDX

(214) 0x43180b VADDSD	%XMM8,%XMM10,%XMM0

(214) 0x431810 VMOVSD	%XMM0,(%RDX,%RCX,8)

(214) 0x431815 MOV	0x78(%RSP),%ECX

(214) 0x431819 CMP	%ECX,%EDI

(214) 0x43181b JAE	431878

(214) 0x43181d ADD	$0x3,%R14D

(214) 0x431821 ADD	%RAX,%R8

(214) 0x431824 ADD	%RAX,%R9

(214) 0x431827 ADD	%RAX,%R13

(214) 0x43182a MOVSXD	%R14D,%RDI

(214) 0x43182d VMOVQ	%XMM11,%R14

(214) 0x431832 ADD	%RBX,%RDI

(214) 0x431835 MOV	0x70(%RSP),%RBX

(214) 0x43183a VMOVSD	(%R10,%RDI,8),%XMM1

(214) 0x431840 VMOVQ	%XMM19,%R10

(214) 0x431846 VADDSD	(%R10,%R8,8),%XMM1,%XMM2

(214) 0x43184c VSUBSD	(%R15),%XMM2,%XMM4

(214) 0x431851 MOV	0x60(%RSP),%R15

(214) 0x431856 VMOVSD	%XMM4,(%R14,%R9,8)

(214) 0x43185c ADD	%RAX,%RBX

(214) 0x43185f VMOVSD	(%R12,%RBX,8),%XMM11

(214) 0x431865 ADD	%RAX,%R15

(214) 0x431868 VSUBSD	(%R12,%R15,8),%XMM11,%XMM5

(214) 0x43186e VADDSD	%XMM4,%XMM5,%XMM6

(214) 0x431872 VMOVSD	%XMM6,(%RDX,%R13,8)

(214) 0x431878 MOV	0x78(%RSP),%EDI

(214) 0x43187c MOV	0x40(%RSP),%RSI

(214) 0x431881 CMP	%ESI,0x38(%RSP)

(214) 0x431885 JLE	4318b0

(214) 0x431887 MOV	0x30(%RSP),%ECX

(214) 0x43188b MOV	0x34(%RSP),%R11D

(214) 0x431890 MOV	0x3c(%RSP),%R13D

(214) 0x431895 SUB	%EDI,%ECX

(214) 0x431897 MOV	%R11D,0x7c(%RSP)

(214) 0x43189c JMP	431360

0x4318a1 NOPW	%CS:(%RAX,%RAX,1)

0x4318ac NOPL	(%RAX)

0x4318b0 VZEROUPPER

0x4318b3 LEA	-0x28(%RBP),%RSP

0x4318b7 POP	%RBX

0x4318b8 POP	%R12

0x4318ba POP	%R13

0x4318bc POP	%R14

0x4318be POP	%R15

0x4318c0 POP	%RBP

0x4318c1 RET

0x4318c2 NOPW	%CS:(%RAX,%RAX,1)

0x4318cd NOPL	(%RAX)

(214) 0x4318d0 LEA	0x1(%RSI),%R14

(214) 0x4318d4 MOV	%R14,0x40(%RSP)

(214) 0x4318d9 JMP	43187c

0x4318db NOPL	(%RAX,%RAX,1)

(214) 0x4318e0 MOV	0x7c(%RSP),%R14D

(214) 0x4318e5 XOR	%R9D,%R9D

(214) 0x4318e8 JMP	431661

0x4318ed INC	%ECX

0x4318ef XOR	%EDX,%EDX

0x4318f1 JMP	431303

0x4318f6 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.75+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.11+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:152	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:239	exec
○	advection(global_variables&)	advection.cpp:68	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.10+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:152	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:70	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53-57

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.88 cycles (6.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.63 cycles (1.25x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.38 cycles (1.28x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:56

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	80
nb uops	77
loop length	295
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.63
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 431280

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%R14),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
DEC %EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ECX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ECX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4318b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x633>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RDX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4318b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x633>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EBX,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x3c(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R8D,%R12D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 4318ed <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x66d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%ESI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RSI,%RDX,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RCX,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9D,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R9D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4318b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x633>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x34(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ 0x10(%R14),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x3c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ (%R14),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R14),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x8(%R14),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R14),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RAX,%R15,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EDX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %R11D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,0x7c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 431303 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:53-57
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:53-57

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.88 cycles (6.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.38 cycles (1.28x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:55
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:56

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	80
nb uops	77
loop length	295
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.63
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 431280

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%R14),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
DEC %EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ECX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ECX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4318b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x633>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RDX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4318b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x633>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EBX,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x3c(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R8D,%R12D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 4318ed <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x66d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%ESI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RSI,%RDX,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%RCX,%RDI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9D,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R9D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4318b3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x633>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x34(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ 0x10(%R14),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x3c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ (%R14),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R14),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x8(%R14),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R14),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RAX,%R15,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EDX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %R11D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,0x7c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 431303 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.1+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.04	1.12
▼Loop 214 - advec_mom.cpp:53-57 - exec–	0.01	0.01
○Loop 215 - advec_mom.cpp:56-57 - exec	3.04	1.11

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code