OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:44-48 [...]	Coverage (incl. loops): 3.11% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:         post_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

48:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

0x430c20 PUSH	%RBP

0x430c21 MOV	%RSP,%RBP

0x430c24 PUSH	%R15

0x430c26 PUSH	%R14

0x430c28 PUSH	%R13

0x430c2a PUSH	%R12

0x430c2c PUSH	%RBX

0x430c2d AND	$-0x40,%RSP

0x430c31 ADD	$-0x80,%RSP

0x430c35 MOV	0x30(%RDI),%EAX

0x430c38 MOV	0x34(%RDI),%EBX

0x430c3b MOV	0x28(%RDI),%ECX

0x430c3e MOV	0x2c(%RDI),%EDX

0x430c41 ADD	$0x4,%EBX

0x430c44 DEC	%ECX

0x430c46 LEA	-0x1(%RAX),%R15D

0x430c4a MOV	%EBX,0x38(%RSP)

0x430c4e MOV	%ECX,0x34(%RSP)

0x430c52 CMP	%EBX,%R15D

0x430c55 JGE	431233

0x430c5b MOV	%EBX,%R12D

0x430c5e LEA	0x4(%RDX),%R13D

0x430c62 SUB	%R15D,%R12D

0x430c65 CMP	%R13D,%ECX

0x430c68 JGE	431233

0x430c6e MOV	%R13D,%ESI

0x430c71 MOV	%RDI,%R14

0x430c74 SUB	%ECX,%ESI

0x430c76 MOV	%ESI,0x3c(%RSP)

0x430c7a CALL	404630 <omp_get_num_threads@plt>

0x430c7f MOV	%EAX,%EBX

0x430c81 CALL	404520 <omp_get_thread_num@plt>

0x430c86 MOV	0x3c(%RSP),%R8D

0x430c8b XOR	%EDX,%EDX

0x430c8d MOV	%EAX,%EDI

0x430c8f IMUL	%R8D,%R12D

0x430c93 MOV	%R12D,%EAX

0x430c96 DIV	%EBX

0x430c98 MOV	%EAX,%R9D

0x430c9b CMP	%EDX,%EDI

0x430c9d JB	43126c

0x430ca3 IMUL	%R9D,%EDI

0x430ca7 LEA	(%RDI,%RDX,1),%R11D

0x430cab LEA	(%R9,%R11,1),%R10D

0x430caf MOV	%R10D,0x30(%RSP)

0x430cb4 CMP	%R10D,%R11D

0x430cb7 JAE	431233

0x430cbd MOV	%R11D,%EAX

0x430cc0 XOR	%EDX,%EDX

0x430cc2 MOV	0x34(%RSP),%ECX

0x430cc6 VMOVQ	0x10(%R14),%XMM15

0x430ccc DIVL	0x3c(%RSP)

0x430cd0 VMOVQ	0x8(%R14),%XMM14

0x430cd6 VMOVQ	0x20(%R14),%XMM13

0x430cdc VMOVQ	(%R14),%XMM12

0x430ce1 VMOVQ	0x18(%R14),%XMM11

0x430ce7 ADD	%EDX,%ECX

0x430ce9 LEA	(%RAX,%R15,1),%R15D

0x430ced MOV	%R9D,%EAX

0x430cf0 SUB	%ECX,%R13D

0x430cf3 MOV	%ECX,0x74(%RSP)

0x430cf7 MOVSXD	%R15D,%RCX

0x430cfa NOPW	(%RAX,%RAX,1)

(212) 0x430d00 CMP	%R13D,%EAX

(212) 0x430d03 CMOVA	%R13D,%EAX

(212) 0x430d07 LEA	(%R11,%RAX,1),%R13D

(212) 0x430d0b MOV	%R13D,0x70(%RSP)

(212) 0x430d10 CMP	%R13D,%R11D

(212) 0x430d13 JAE	431250

(212) 0x430d19 VMOVQ	%XMM15,%R14

(212) 0x430d1e VMOVQ	%XMM13,%RDX

(212) 0x430d23 LEA	0x1(%RCX),%R9

(212) 0x430d27 VMOVQ	%XMM12,%R12

(212) 0x430d2c MOV	(%R14),%RDI

(212) 0x430d2f VMOVQ	0x10(%R14),%XMM3

(212) 0x430d35 MOV	(%RDX),%R15

(212) 0x430d38 MOV	(%R12),%R14

(212) 0x430d3c VMOVQ	%XMM14,%RSI

(212) 0x430d41 MOV	%R9,0x40(%RSP)

(212) 0x430d46 VMOVQ	0x10(%RDX),%XMM10

(212) 0x430d4b MOV	(%RSI),%R8

(212) 0x430d4e MOV	0x10(%RSI),%R10

(212) 0x430d52 VMOVQ	%XMM11,%RSI

(212) 0x430d57 MOV	0x10(%R12),%R13

(212) 0x430d5c VMOVQ	0x10(%RSI),%XMM9

(212) 0x430d61 IMUL	%RCX,%RDI

(212) 0x430d65 IMUL	%RCX,%R15

(212) 0x430d69 IMUL	%RCX,%R14

(212) 0x430d6d IMUL	(%RSI),%RCX

(212) 0x430d71 MOV	%RDI,0x48(%RSP)

(212) 0x430d76 IMUL	%R8,%R9

(212) 0x430d7a MOV	%R15,0x68(%RSP)

(212) 0x430d7f MOV	%R14,0x60(%RSP)

(212) 0x430d84 MOV	%R9,%RBX

(212) 0x430d87 MOV	%R9,0x50(%RSP)

(212) 0x430d8c SUB	%R8,%RBX

(212) 0x430d8f MOV	%RCX,0x78(%RSP)

(212) 0x430d94 LEA	-0x1(%RAX),%ECX

(212) 0x430d97 MOV	%RBX,0x58(%RSP)

(212) 0x430d9c CMP	$0x6,%ECX

(212) 0x430d9f JBE	431260

(212) 0x430da5 MOVSXD	0x74(%RSP),%RSI

(212) 0x430daa VMOVQ	%XMM3,%RDX

(212) 0x430daf VMOVQ	%XMM10,%R12

(212) 0x430db4 LEA	0x1(%R14,%RSI,1),%R14

(212) 0x430db9 ADD	%RSI,%RDI

(212) 0x430dbc LEA	(%RBX,%RSI,1),%RBX

(212) 0x430dc0 LEA	(%R15,%RSI,1),%R15

(212) 0x430dc4 SAL	$0x3,%R14

(212) 0x430dc8 LEA	(%RDX,%RDI,8),%R8

(212) 0x430dcc LEA	(%R10,%RBX,8),%RCX

(212) 0x430dd0 MOV	0x78(%RSP),%RDI

(212) 0x430dd5 LEA	(%R12,%R15,8),%RBX

(212) 0x430dd9 LEA	-0x8(%R13,%R14,1),%RDX

(212) 0x430dde LEA	(%R13,%R14,1),%R12

(212) 0x430de3 MOV	%EAX,%R14D

(212) 0x430de6 LEA	(%R9,%RSI,1),%R9

(212) 0x430dea SHR	$0x3,%R14D

(212) 0x430dee VMOVQ	%XMM9,%R15

(212) 0x430df3 SAL	$0x6,%R14

(212) 0x430df7 ADD	%RDI,%RSI

(212) 0x430dfa LEA	-0x40(%R14),%RDI

(212) 0x430dfe LEA	(%R10,%R9,8),%R9

(212) 0x430e02 SHR	$0x6,%RDI

(212) 0x430e06 INC	%RDI

(212) 0x430e09 LEA	(%R15,%RSI,8),%R15

(212) 0x430e0d XOR	%ESI,%ESI

(212) 0x430e0f AND	$0x3,%EDI

(212) 0x430e12 JE	430ed9

(212) 0x430e18 CMP	$0x1,%RDI

(212) 0x430e1c JE	430e95

(212) 0x430e1e CMP	$0x2,%RDI

(212) 0x430e22 JE	430e5a

(212) 0x430e24 VMOVUPD	(%R8),%ZMM16

(212) 0x430e2a VADDPD	(%R9),%ZMM16,%ZMM17

(212) 0x430e30 MOV	$0x40,%ESI

(212) 0x430e35 VSUBPD	(%RCX),%ZMM17,%ZMM18

(212) 0x430e3b VMOVUPD	%ZMM18,(%RBX)

(212) 0x430e41 VMOVUPD	(%R12),%ZMM19

(212) 0x430e48 VSUBPD	(%RDX),%ZMM19,%ZMM20

(212) 0x430e4e VADDPD	%ZMM18,%ZMM20,%ZMM21

(212) 0x430e54 VMOVUPD	%ZMM21,(%R15)

(212) 0x430e5a VMOVUPD	(%R8,%RSI,1),%ZMM22

(212) 0x430e61 VADDPD	(%R9,%RSI,1),%ZMM22,%ZMM23

(212) 0x430e68 VSUBPD	(%RCX,%RSI,1),%ZMM23,%ZMM24

(212) 0x430e6f VMOVUPD	%ZMM24,(%RBX,%RSI,1)

(212) 0x430e76 VMOVUPD	(%R12,%RSI,1),%ZMM25

(212) 0x430e7d VSUBPD	(%RDX,%RSI,1),%ZMM25,%ZMM26

(212) 0x430e84 VADDPD	%ZMM24,%ZMM26,%ZMM27

(212) 0x430e8a VMOVUPD	%ZMM27,(%R15,%RSI,1)

(212) 0x430e91 ADD	$0x40,%RSI

(212) 0x430e95 VMOVUPD	(%R8,%RSI,1),%ZMM28

(212) 0x430e9c VADDPD	(%R9,%RSI,1),%ZMM28,%ZMM29

(212) 0x430ea3 VSUBPD	(%RCX,%RSI,1),%ZMM29,%ZMM30

(212) 0x430eaa VMOVUPD	%ZMM30,(%RBX,%RSI,1)

(212) 0x430eb1 VMOVUPD	(%R12,%RSI,1),%ZMM31

(212) 0x430eb8 VSUBPD	(%RDX,%RSI,1),%ZMM31,%ZMM16

(212) 0x430ebf VADDPD	%ZMM30,%ZMM16,%ZMM17

(212) 0x430ec5 VMOVUPD	%ZMM17,(%R15,%RSI,1)

(212) 0x430ecc ADD	$0x40,%RSI

(212) 0x430ed0 CMP	%R14,%RSI

(212) 0x430ed3 JE	430fda

  (213) 0x430ed9 VMOVUPD	(%R8,%RSI,1),%ZMM0

  (213) 0x430ee0 VADDPD	(%R9,%RSI,1),%ZMM0,%ZMM1

  (213) 0x430ee7 VSUBPD	(%RCX,%RSI,1),%ZMM1,%ZMM2

  (213) 0x430eee VMOVUPD	%ZMM2,(%RBX,%RSI,1)

  (213) 0x430ef5 VMOVUPD	(%R12,%RSI,1),%ZMM18

  (213) 0x430efc VSUBPD	(%RDX,%RSI,1),%ZMM18,%ZMM19

  (213) 0x430f03 VADDPD	%ZMM2,%ZMM19,%ZMM20

  (213) 0x430f09 VMOVUPD	%ZMM20,(%R15,%RSI,1)

  (213) 0x430f10 VMOVUPD	0x40(%R8,%RSI,1),%ZMM4

  (213) 0x430f18 VADDPD	0x40(%R9,%RSI,1),%ZMM4,%ZMM5

  (213) 0x430f20 VSUBPD	0x40(%RCX,%RSI,1),%ZMM5,%ZMM6

  (213) 0x430f28 VMOVUPD	%ZMM6,0x40(%RBX,%RSI,1)

  (213) 0x430f30 VMOVUPD	0x40(%R12,%RSI,1),%ZMM21

  (213) 0x430f38 VSUBPD	0x40(%RDX,%RSI,1),%ZMM21,%ZMM22

  (213) 0x430f40 VADDPD	%ZMM6,%ZMM22,%ZMM23

  (213) 0x430f46 VMOVUPD	%ZMM23,0x40(%R15,%RSI,1)

  (213) 0x430f4e VMOVUPD	0x80(%R8,%RSI,1),%ZMM7

  (213) 0x430f56 VADDPD	0x80(%R9,%RSI,1),%ZMM7,%ZMM8

  (213) 0x430f5e VSUBPD	0x80(%RCX,%RSI,1),%ZMM8,%ZMM0

  (213) 0x430f66 VMOVUPD	%ZMM0,0x80(%RBX,%RSI,1)

  (213) 0x430f6e VMOVUPD	0x80(%R12,%RSI,1),%ZMM24

  (213) 0x430f76 VSUBPD	0x80(%RDX,%RSI,1),%ZMM24,%ZMM25

  (213) 0x430f7e VADDPD	%ZMM0,%ZMM25,%ZMM26

  (213) 0x430f84 VMOVUPD	%ZMM26,0x80(%R15,%RSI,1)

  (213) 0x430f8c VMOVUPD	0xc0(%R8,%RSI,1),%ZMM1

  (213) 0x430f94 VADDPD	0xc0(%R9,%RSI,1),%ZMM1,%ZMM2

  (213) 0x430f9c VSUBPD	0xc0(%RCX,%RSI,1),%ZMM2,%ZMM4

  (213) 0x430fa4 VMOVUPD	%ZMM4,0xc0(%RBX,%RSI,1)

  (213) 0x430fac VMOVUPD	0xc0(%R12,%RSI,1),%ZMM27

  (213) 0x430fb4 VSUBPD	0xc0(%RDX,%RSI,1),%ZMM27,%ZMM28

  (213) 0x430fbc VADDPD	%ZMM4,%ZMM28,%ZMM29

  (213) 0x430fc2 VMOVUPD	%ZMM29,0xc0(%R15,%RSI,1)

  (213) 0x430fca ADD	$0x100,%RSI

  (213) 0x430fd1 CMP	%R14,%RSI

  (213) 0x430fd4 JNE	430ed9

(212) 0x430fda MOV	0x74(%RSP),%R9D

(212) 0x430fdf MOV	%EAX,%R8D

(212) 0x430fe2 AND	$-0x8,%R8D

(212) 0x430fe6 ADD	%R8D,%R11D

(212) 0x430fe9 LEA	(%R8,%R9,1),%EDI

(212) 0x430fed TEST	$0x7,%AL

(212) 0x430fef JE	4311fd

(212) 0x430ff5 SUB	%R8D,%EAX

(212) 0x430ff8 LEA	-0x1(%RAX),%ECX

(212) 0x430ffb CMP	$0x2,%ECX

(212) 0x430ffe JBE	4310a6

(212) 0x431004 MOVSXD	0x74(%RSP),%R12

(212) 0x431009 MOV	0x60(%RSP),%RBX

(212) 0x43100e MOV	0x48(%RSP),%R15

(212) 0x431013 MOV	0x50(%RSP),%R9

(212) 0x431018 LEA	(%RBX,%R12,1),%RDX

(212) 0x43101c LEA	(%R15,%R12,1),%R14

(212) 0x431020 LEA	(%R9,%R12,1),%RCX

(212) 0x431024 VMOVQ	%XMM3,%RBX

(212) 0x431029 LEA	0x1(%R8,%RDX,1),%RSI

(212) 0x43102e MOV	0x58(%RSP),%RDX

(212) 0x431033 ADD	%R8,%R14

(212) 0x431036 ADD	%R8,%RCX

(212) 0x431039 VMOVUPD	(%R10,%RCX,8),%YMM5

(212) 0x43103f VADDPD	(%RBX,%R14,8),%YMM5,%YMM6

(212) 0x431045 MOV	0x68(%RSP),%R14

(212) 0x43104a VMOVQ	%XMM10,%RCX

(212) 0x43104f LEA	(%RDX,%R12,1),%R15

(212) 0x431053 ADD	%R8,%R15

(212) 0x431056 LEA	(%R14,%R12,1),%R9

(212) 0x43105a VSUBPD	(%R10,%R15,8),%YMM6,%YMM7

(212) 0x431060 ADD	%R8,%R9

(212) 0x431063 VMOVUPD	%YMM7,(%RCX,%R9,8)

(212) 0x431069 VMOVUPD	(%R13,%RSI,8),%YMM8

(212) 0x431070 VSUBPD	-0x8(%R13,%RSI,8),%YMM8,%YMM0

(212) 0x431077 MOV	0x78(%RSP),%RSI

(212) 0x43107c ADD	%RSI,%R12

(212) 0x43107f ADD	%R8,%R12

(212) 0x431082 VMOVQ	%XMM9,%R8

(212) 0x431087 VADDPD	%YMM7,%YMM0,%YMM1

(212) 0x43108b VMOVUPD	%YMM1,(%R8,%R12,8)

(212) 0x431091 MOV	%EAX,%R12D

(212) 0x431094 AND	$-0x4,%R12D

(212) 0x431098 ADD	%R12D,%EDI

(212) 0x43109b ADD	%R12D,%R11D

(212) 0x43109e TEST	$0x3,%AL

(212) 0x4310a0 JE	4311fd

(212) 0x4310a6 MOV	0x50(%RSP),%RBX

(212) 0x4310ab MOVSXD	%EDI,%RAX

(212) 0x4310ae MOV	0x48(%RSP),%R9

(212) 0x4310b3 MOV	0x68(%RSP),%R8

(212) 0x4310b8 VMOVQ	%XMM3,%R14

(212) 0x4310bd VMOVQ	%XMM10,%R12

(212) 0x4310c2 LEA	(%RBX,%RAX,1),%R15

(212) 0x4310c6 LEA	(%R9,%RAX,1),%RDX

(212) 0x4310ca LEA	(%R8,%RAX,1),%RSI

(212) 0x4310ce VMOVSD	(%R10,%R15,8),%XMM2

(212) 0x4310d4 MOV	0x58(%RSP),%R15

(212) 0x4310d9 VADDSD	(%R14,%RDX,8),%XMM2,%XMM4

(212) 0x4310df LEA	0x1(%RDI),%EDX

(212) 0x4310e2 MOVSXD	%EDX,%RDX

(212) 0x4310e5 LEA	(%R15,%RAX,1),%RCX

(212) 0x4310e9 VSUBSD	(%R10,%RCX,8),%XMM4,%XMM5

(212) 0x4310ef MOV	0x60(%RSP),%RCX

(212) 0x4310f4 VMOVSD	%XMM5,(%R12,%RSI,8)

(212) 0x4310fa MOV	0x78(%RSP),%R12

(212) 0x4310ff LEA	(%RCX,%RDX,1),%R14

(212) 0x431103 LEA	(%R13,%R14,8),%RSI

(212) 0x431108 LEA	(%R12,%RAX,1),%R14

(212) 0x43110c ADD	%RCX,%RAX

(212) 0x43110f VMOVSD	(%RSI),%XMM6

(212) 0x431113 VSUBSD	(%R13,%RAX,8),%XMM6,%XMM7

(212) 0x43111a VMOVQ	%XMM9,%RAX

(212) 0x43111f VADDSD	%XMM5,%XMM7,%XMM8

(212) 0x431123 VMOVSD	%XMM8,(%RAX,%R14,8)

(212) 0x431129 MOV	0x70(%RSP),%R14D

(212) 0x43112e LEA	0x1(%R11),%EAX

(212) 0x431132 CMP	%R14D,%EAX

(212) 0x431135 JAE	4311fd

(212) 0x43113b LEA	(%RDX,%RBX,1),%R14

(212) 0x43113f LEA	(%RDX,%R9,1),%RAX

(212) 0x431143 LEA	(%RDX,%R8,1),%R8

(212) 0x431147 ADD	$0x2,%R11D

(212) 0x43114b VMOVSD	(%R10,%R14,8),%XMM0

(212) 0x431151 VMOVQ	%XMM3,%R14

(212) 0x431156 VADDSD	(%R14,%RAX,8),%XMM0,%XMM1

(212) 0x43115c LEA	(%RDX,%R15,1),%RAX

(212) 0x431160 VMOVQ	%XMM10,%R14

(212) 0x431165 ADD	%R12,%RDX

(212) 0x431168 VSUBSD	(%R10,%RAX,8),%XMM1,%XMM4

(212) 0x43116e LEA	0x2(%RDI),%EAX

(212) 0x431171 VMOVSD	%XMM4,(%R14,%R8,8)

(212) 0x431177 CLTQ

(212) 0x431179 LEA	(%RCX,%RAX,1),%R8

(212) 0x43117d LEA	(%R13,%R8,8),%R14

(212) 0x431182 VMOVSD	(%R14),%XMM2

(212) 0x431187 VSUBSD	(%RSI),%XMM2,%XMM5

(212) 0x43118b VMOVQ	%XMM9,%RSI

(212) 0x431190 VADDSD	%XMM4,%XMM5,%XMM6

(212) 0x431194 VMOVSD	%XMM6,(%RSI,%RDX,8)

(212) 0x431199 MOV	0x70(%RSP),%EDX

(212) 0x43119d CMP	%EDX,%R11D

(212) 0x4311a0 JAE	4311fd

(212) 0x4311a2 ADD	%RAX,%RBX

(212) 0x4311a5 ADD	%RAX,%R9

(212) 0x4311a8 VMOVQ	%XMM3,%R11

(212) 0x4311ad ADD	%RAX,%R15

(212) 0x4311b0 VMOVSD	(%R10,%RBX,8),%XMM7

(212) 0x4311b6 MOV	0x78(%RSP),%R8

(212) 0x4311bb VADDSD	(%R11,%R9,8),%XMM7,%XMM3

(212) 0x4311c1 VSUBSD	(%R10,%R15,8),%XMM3,%XMM8

(212) 0x4311c7 MOV	0x68(%RSP),%R10

(212) 0x4311cc ADD	$0x3,%EDI

(212) 0x4311cf VMOVQ	%XMM10,%R12

(212) 0x4311d4 MOVSXD	%EDI,%RDI

(212) 0x4311d7 ADD	%RCX,%RDI

(212) 0x4311da ADD	%RAX,%R8

(212) 0x4311dd ADD	%RAX,%R10

(212) 0x4311e0 VMOVSD	%XMM8,(%R12,%R10,8)

(212) 0x4311e6 VMOVSD	(%R13,%RDI,8),%XMM10

(212) 0x4311ed VSUBSD	(%R14),%XMM10,%XMM0

(212) 0x4311f2 VADDSD	%XMM8,%XMM0,%XMM1

(212) 0x4311f7 VMOVSD	%XMM1,(%RSI,%R8,8)

(212) 0x4311fd MOV	0x70(%RSP),%R11D

(212) 0x431202 MOV	0x40(%RSP),%RCX

(212) 0x431207 CMP	%ECX,0x38(%RSP)

(212) 0x43120b JLE	431230

(212) 0x43120d MOV	0x30(%RSP),%EAX

(212) 0x431211 MOV	0x34(%RSP),%R14D

(212) 0x431216 MOV	0x3c(%RSP),%R13D

(212) 0x43121b SUB	%R11D,%EAX

(212) 0x43121e MOV	%R14D,0x74(%RSP)

(212) 0x431223 JMP	430d00

0x431228 NOPL	(%RAX,%RAX,1)

0x431230 VZEROUPPER

0x431233 LEA	-0x28(%RBP),%RSP

0x431237 POP	%RBX

0x431238 POP	%R12

0x43123a POP	%R13

0x43123c POP	%R14

0x43123e POP	%R15

0x431240 POP	%RBP

0x431241 RET

0x431242 NOPW	%CS:(%RAX,%RAX,1)

0x43124d NOPL	(%RAX)

(212) 0x431250 LEA	0x1(%RCX),%R12

(212) 0x431254 MOV	%R12,0x40(%RSP)

(212) 0x431259 JMP	431202

0x43125b NOPL	(%RAX,%RAX,1)

(212) 0x431260 MOV	0x74(%RSP),%EDI

(212) 0x431264 XOR	%R8D,%R8D

(212) 0x431267 JMP	430ff5

0x43126c INC	%R9D

0x43126f XOR	%EDX,%EDX

0x431271 JMP	430ca3

0x431276 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.80+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.14+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:80	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:239	exec
○	advection(global_variables&)	advection.cpp:68	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.11+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:80	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:70	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.75 cycles (1.23x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:47

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	80
nb uops	78
loop length	289
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

all	7%
load	9%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 430c20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x28(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
DEC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EBX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EBX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 431233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x613>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EBX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RDX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 431233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x613>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ECX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x3c(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R8D,%R12D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 43126c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x64c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%EDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDI,%RDX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R9,%R11,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R10D,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 431233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x613>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x34(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ 0x10(%R14),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x3c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%R14),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R14),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ (%R14),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R14),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA (%RAX,%R15,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %R15D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 430ca3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:47

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	80
nb uops	78
loop length	289
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

all	7%
load	9%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 430c20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x28(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
DEC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EBX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EBX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 431233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x613>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EBX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RDX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 431233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x613>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ECX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x3c(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R8D,%R12D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 43126c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x64c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%EDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDI,%RDX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R9,%R11,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R10D,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 431233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x613>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x34(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ 0x10(%R14),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x3c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%R14),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R14),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ (%R14),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R14),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA (%RAX,%R15,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %R15D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 430ca3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.0+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.11	1.14
▼Loop 212 - advec_mom.cpp:44-48 - exec–	0.01	0.01
○Loop 213 - advec_mom.cpp:47-48 - exec	3.11	1.14

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code