OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:208-216 [...]	Coverage (incl. loops): 3.55% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 208 - 216

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208: #pragma omp parallel for simd collapse(2)

209:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

210:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

211:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

212:         double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1);

213:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s;

214:         double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1);

215:         density1(i, j) = post_mass_s / advec_vol_s;

216:         energy1(i, j) = post_ener_s;

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42e160 PUSH	%RBP

0x42e161 MOV	%RSP,%RBP

0x42e164 PUSH	%R15

0x42e166 PUSH	%R14

0x42e168 PUSH	%R13

0x42e16a PUSH	%R12

0x42e16c PUSH	%RBX

0x42e16d MOV	%RDI,%R13

0x42e170 AND	$-0x40,%RSP

0x42e174 ADD	$-0x80,%RSP

0x42e178 MOV	0x38(%RDI),%EAX

0x42e17b MOV	0x3c(%RDI),%EDX

0x42e17e MOV	0x30(%RDI),%EBX

0x42e181 MOV	0x34(%R13),%ECX

0x42e185 ADD	$0x2,%EDX

0x42e188 LEA	0x1(%RBX),%EDI

0x42e18b LEA	0x1(%RAX),%R14D

0x42e18f MOV	%EDX,0x20(%RSP)

0x42e193 MOV	%EDI,0x1c(%RSP)

0x42e197 CMP	%EDX,%R14D

0x42e19a JGE	42e863

0x42e1a0 MOV	%EDX,%EBX

0x42e1a2 LEA	0x2(%RCX),%R15D

0x42e1a6 SUB	%R14D,%EBX

0x42e1a9 CMP	%R15D,%EDI

0x42e1ac JGE	42e863

0x42e1b2 MOV	%R15D,%ESI

0x42e1b5 SUB	%EDI,%ESI

0x42e1b7 MOV	%ESI,0x24(%RSP)

0x42e1bb CALL	404630 <omp_get_num_threads@plt>

0x42e1c0 MOV	%EAX,%R12D

0x42e1c3 CALL	404520 <omp_get_thread_num@plt>

0x42e1c8 XOR	%EDX,%EDX

0x42e1ca MOV	%EAX,%R8D

0x42e1cd MOV	0x24(%RSP),%EAX

0x42e1d1 IMUL	%EBX,%EAX

0x42e1d4 DIV	%R12D

0x42e1d7 MOV	%EAX,%R9D

0x42e1da CMP	%EDX,%R8D

0x42e1dd JB	42e88b

0x42e1e3 IMUL	%R9D,%R8D

0x42e1e7 LEA	(%R8,%RDX,1),%R10D

0x42e1eb LEA	(%R9,%R10,1),%R11D

0x42e1ef MOV	%R11D,0x18(%RSP)

0x42e1f4 CMP	%R11D,%R10D

0x42e1f7 JAE	42e863

0x42e1fd MOV	%R10D,%EAX

0x42e200 XOR	%EDX,%EDX

0x42e202 MOV	0x1c(%RSP),%EDI

0x42e206 VMOVQ	(%R13),%XMM21

0x42e20d DIVL	0x24(%RSP)

0x42e211 VMOVQ	0x20(%R13),%XMM20

0x42e218 VMOVQ	0x10(%R13),%XMM19

0x42e21f MOV	%R15D,%ECX

0x42e222 VMOVQ	0x8(%R13),%XMM18

0x42e229 VMOVQ	0x28(%R13),%XMM17

0x42e230 MOV	%R9D,%ESI

0x42e233 MOV	%R10D,0x7c(%RSP)

0x42e238 VMOVQ	0x18(%R13),%XMM16

0x42e23f ADD	%EDX,%EDI

0x42e241 ADD	%R14D,%EAX

0x42e244 SUB	%EDI,%ECX

0x42e246 MOVSXD	%EAX,%R14

0x42e249 MOV	%EDI,0x64(%RSP)

0x42e24d MOV	%ECX,%R8D

(204) 0x42e250 MOV	0x7c(%RSP),%R13D

(204) 0x42e255 CMP	%R8D,%ESI

(204) 0x42e258 CMOVBE	%ESI,%R8D

(204) 0x42e25c MOV	%R8D,0x78(%RSP)

(204) 0x42e261 LEA	(%R13,%R8,1),%R15D

(204) 0x42e266 MOV	%R15D,0x60(%RSP)

(204) 0x42e26b CMP	%R15D,%R13D

(204) 0x42e26e JAE	42e834

(204) 0x42e274 MOV	%R8D,%EBX

(204) 0x42e277 VMOVQ	%XMM19,%R8

(204) 0x42e27d VMOVQ	%XMM21,%RSI

(204) 0x42e283 MOV	(%R8),%R9

(204) 0x42e286 VMOVQ	%XMM17,%RDI

(204) 0x42e28c MOV	(%RSI),%R10

(204) 0x42e28f VMOVQ	0x10(%RSI),%XMM14

(204) 0x42e294 MOV	(%RDI),%RCX

(204) 0x42e297 VMOVQ	%XMM16,%RSI

(204) 0x42e29d VMOVQ	0x10(%RDI),%XMM5

(204) 0x42e2a2 VMOVQ	0x10(%R8),%XMM6

(204) 0x42e2a8 MOV	(%RSI),%RDI

(204) 0x42e2ab VMOVQ	%XMM20,%R12

(204) 0x42e2b1 VMOVQ	%XMM18,%R11

(204) 0x42e2b7 MOV	(%R12),%RDX

(204) 0x42e2bb MOV	(%R11),%R8

(204) 0x42e2be VMOVQ	0x10(%R12),%XMM13

(204) 0x42e2c5 VMOVQ	0x10(%R11),%XMM12

(204) 0x42e2cb MOV	%R9,%RAX

(204) 0x42e2ce MOV	0x10(%RSI),%R11

(204) 0x42e2d2 IMUL	%R14,%RAX

(204) 0x42e2d6 MOV	%RDI,%R12

(204) 0x42e2d9 IMUL	%R14,%R10

(204) 0x42e2dd IMUL	%R14,%R12

(204) 0x42e2e1 LEA	(%R9,%RAX,1),%R13

(204) 0x42e2e5 IMUL	%R14,%RDX

(204) 0x42e2e9 MOV	%RCX,%R9

(204) 0x42e2ec MOV	%RAX,0x38(%RSP)

(204) 0x42e2f1 IMUL	%R14,%R9

(204) 0x42e2f5 MOV	%R10,0x28(%RSP)

(204) 0x42e2fa MOV	%R13,0x40(%RSP)

(204) 0x42e2ff IMUL	%R14,%R8

(204) 0x42e303 ADD	%R12,%RDI

(204) 0x42e306 MOV	%R12,0x50(%RSP)

(204) 0x42e30b MOV	%RDX,0x30(%RSP)

(204) 0x42e310 MOV	%RDI,0x68(%RSP)

(204) 0x42e315 LEA	(%RCX,%R9,1),%R15

(204) 0x42e319 MOV	%R9,0x58(%RSP)

(204) 0x42e31e MOV	%R15,0x70(%RSP)

(204) 0x42e323 LEA	-0x1(%RBX),%R15D

(204) 0x42e327 MOV	%R8,0x48(%RSP)

(204) 0x42e32c CMP	$0x6,%R15D

(204) 0x42e330 JBE	42e880

(204) 0x42e336 MOVSXD	0x64(%RSP),%RCX

(204) 0x42e33b VMOVQ	%XMM14,%RDI

(204) 0x42e340 VMOVQ	%XMM13,%RSI

(204) 0x42e345 LEA	(%R10,%RCX,1),%R10

(204) 0x42e349 LEA	(%RDX,%RCX,1),%RDX

(204) 0x42e34d LEA	(%RAX,%RCX,1),%RAX

(204) 0x42e351 LEA	(%R13,%RCX,1),%R13

(204) 0x42e356 LEA	(%RDI,%R10,8),%R15

(204) 0x42e35a VMOVQ	%XMM6,%RDI

(204) 0x42e35f LEA	(%RSI,%RDX,8),%R10

(204) 0x42e363 LEA	(%R8,%RCX,1),%RSI

(204) 0x42e367 LEA	(%RDI,%RAX,8),%RDX

(204) 0x42e36b MOV	0x70(%RSP),%RAX

(204) 0x42e370 VMOVQ	%XMM12,%R8

(204) 0x42e375 LEA	(%RDI,%R13,8),%RDI

(204) 0x42e379 LEA	(%R8,%RSI,8),%R13

(204) 0x42e37d LEA	(%R12,%RCX,1),%R12

(204) 0x42e381 LEA	(%R9,%RCX,1),%R9

(204) 0x42e385 VMOVQ	%XMM5,%R8

(204) 0x42e38a LEA	(%R8,%R9,8),%R9

(204) 0x42e38e LEA	(%RAX,%RCX,1),%RSI

(204) 0x42e392 MOV	0x68(%RSP),%RAX

(204) 0x42e397 LEA	(%R8,%RSI,8),%R8

(204) 0x42e39b LEA	(%R11,%R12,8),%RSI

(204) 0x42e39f MOV	%EBX,%R12D

(204) 0x42e3a2 SHR	$0x3,%R12D

(204) 0x42e3a6 MOV	%R12,%RBX

(204) 0x42e3a9 ADD	%RAX,%RCX

(204) 0x42e3ac SAL	$0x6,%RBX

(204) 0x42e3b0 LEA	(%R11,%RCX,8),%RAX

(204) 0x42e3b4 XOR	%ECX,%ECX

(204) 0x42e3b6 AND	$0x1,%R12D

(204) 0x42e3ba JE	42e41a

(204) 0x42e3bc VMOVUPD	(%R10),%ZMM1

(204) 0x42e3c2 VMULPD	(%R15),%ZMM1,%ZMM22

(204) 0x42e3c8 VADDPD	(%RSI),%ZMM1,%ZMM0

(204) 0x42e3ce VMOVUPD	(%R9),%ZMM24

(204) 0x42e3d4 VSUBPD	(%RAX),%ZMM0,%ZMM2

(204) 0x42e3da VSUBPD	(%R8),%ZMM24,%ZMM26

(204) 0x42e3e0 MOV	$0x40,%ECX

(204) 0x42e3e5 VSUBPD	(%RDI),%ZMM22,%ZMM23

(204) 0x42e3eb VFMADD132PD	(%R13),%ZMM26,%ZMM22

(204) 0x42e3f2 VADDPD	(%RDX),%ZMM23,%ZMM25

(204) 0x42e3f8 VDIVPD	%ZMM2,%ZMM25,%ZMM3

(204) 0x42e3fe VDIVPD	%ZMM25,%ZMM22,%ZMM27

(204) 0x42e404 VMOVUPD	%ZMM3,(%R15)

(204) 0x42e40a VMOVUPD	%ZMM27,(%R13)

(204) 0x42e411 CMP	%RBX,%RCX

(204) 0x42e414 JE	42e4fa

(204) 0x42e41a MOV	%R14,0x10(%RSP)

(204) 0x42e41f MOV	0x7c(%RSP),%R14D

  (205) 0x42e424 VMOVUPD	(%R10,%RCX,1),%ZMM4

  (205) 0x42e42b VMULPD	(%R15,%RCX,1),%ZMM4,%ZMM7

  (205) 0x42e432 VADDPD	(%RSI,%RCX,1),%ZMM4,%ZMM8

  (205) 0x42e439 VMOVUPD	(%R9,%RCX,1),%ZMM30

  (205) 0x42e440 VSUBPD	(%RAX,%RCX,1),%ZMM8,%ZMM9

  (205) 0x42e447 VSUBPD	(%R8,%RCX,1),%ZMM30,%ZMM31

  (205) 0x42e44e VSUBPD	(%RDI,%RCX,1),%ZMM7,%ZMM28

  (205) 0x42e455 VFMADD132PD	(%R13,%RCX,1),%ZMM31,%ZMM7

  (205) 0x42e45d VADDPD	(%RDX,%RCX,1),%ZMM28,%ZMM29

  (205) 0x42e464 VDIVPD	%ZMM9,%ZMM29,%ZMM10

  (205) 0x42e46a VDIVPD	%ZMM29,%ZMM7,%ZMM11

  (205) 0x42e470 VMOVUPD	%ZMM10,(%R15,%RCX,1)

  (205) 0x42e477 VMOVUPD	%ZMM11,(%R13,%RCX,1)

  (205) 0x42e47f VMOVUPD	0x40(%R10,%RCX,1),%ZMM15

  (205) 0x42e487 VMULPD	0x40(%R15,%RCX,1),%ZMM15,%ZMM1

  (205) 0x42e48f VADDPD	0x40(%RSI,%RCX,1),%ZMM15,%ZMM0

  (205) 0x42e497 VSUBPD	0x40(%RAX,%RCX,1),%ZMM0,%ZMM2

  (205) 0x42e49f VMOVUPD	0x40(%R9,%RCX,1),%ZMM23

  (205) 0x42e4a7 VSUBPD	0x40(%R8,%RCX,1),%ZMM23,%ZMM24

  (205) 0x42e4af VSUBPD	0x40(%RDI,%RCX,1),%ZMM1,%ZMM22

  (205) 0x42e4b7 VFMADD132PD	0x40(%R13,%RCX,1),%ZMM24,%ZMM1

  (205) 0x42e4bf VADDPD	0x40(%RDX,%RCX,1),%ZMM22,%ZMM25

  (205) 0x42e4c7 VDIVPD	%ZMM2,%ZMM25,%ZMM3

  (205) 0x42e4cd VDIVPD	%ZMM25,%ZMM1,%ZMM4

  (205) 0x42e4d3 VMOVUPD	%ZMM3,0x40(%R15,%RCX,1)

  (205) 0x42e4db VMOVUPD	%ZMM4,0x40(%R13,%RCX,1)

  (205) 0x42e4e3 SUB	$-0x80,%RCX

  (205) 0x42e4e7 CMP	%RBX,%RCX

  (205) 0x42e4ea JNE	42e424

(204) 0x42e4f0 MOV	%R14D,0x7c(%RSP)

(204) 0x42e4f5 MOV	0x10(%RSP),%R14

(204) 0x42e4fa MOV	0x78(%RSP),%R15D

(204) 0x42e4ff MOV	0x64(%RSP),%R10D

(204) 0x42e504 MOV	%R15D,%EBX

(204) 0x42e507 AND	$-0x8,%EBX

(204) 0x42e50a ADD	%EBX,0x7c(%RSP)

(204) 0x42e50e LEA	(%RBX,%R10,1),%ESI

(204) 0x42e512 TEST	$0x7,%R15B

(204) 0x42e516 JE	42e82a

(204) 0x42e51c MOV	0x78(%RSP),%EDX

(204) 0x42e520 SUB	%EBX,%EDX

(204) 0x42e522 LEA	-0x1(%RDX),%EDI

(204) 0x42e525 CMP	$0x2,%EDI

(204) 0x42e528 JBE	42e61a

(204) 0x42e52e MOVSXD	0x64(%RSP),%RAX

(204) 0x42e533 MOV	0x48(%RSP),%R12

(204) 0x42e538 MOV	0x28(%RSP),%R13

(204) 0x42e53d VMOVQ	%XMM12,%R15

(204) 0x42e542 VMOVQ	%XMM14,%R8

(204) 0x42e547 MOV	0x50(%RSP),%R10

(204) 0x42e54c LEA	(%R12,%RAX,1),%RCX

(204) 0x42e550 LEA	(%R13,%RAX,1),%R9

(204) 0x42e555 ADD	%RBX,%RCX

(204) 0x42e558 ADD	%RBX,%R9

(204) 0x42e55b LEA	(%R10,%RAX,1),%R13

(204) 0x42e55f VMOVQ	%XMM13,%R10

(204) 0x42e564 LEA	(%R15,%RCX,8),%RDI

(204) 0x42e568 MOV	0x30(%RSP),%RCX

(204) 0x42e56d LEA	(%R8,%R9,8),%R8

(204) 0x42e571 MOV	0x68(%RSP),%R9

(204) 0x42e576 ADD	%RBX,%R13

(204) 0x42e579 LEA	(%RCX,%RAX,1),%R15

(204) 0x42e57d LEA	(%R9,%RAX,1),%R12

(204) 0x42e581 MOV	0x40(%RSP),%R9

(204) 0x42e586 ADD	%RBX,%R15

(204) 0x42e589 ADD	%RBX,%R12

(204) 0x42e58c VMOVUPD	(%R10,%R15,8),%YMM7

(204) 0x42e592 MOV	0x38(%RSP),%R10

(204) 0x42e597 VMULPD	(%R8),%YMM7,%YMM8

(204) 0x42e59c VMOVQ	%XMM6,%R15

(204) 0x42e5a1 VADDPD	(%R11,%R13,8),%YMM7,%YMM1

(204) 0x42e5a7 VSUBPD	(%R11,%R12,8),%YMM1,%YMM0

(204) 0x42e5ad LEA	(%R9,%RAX,1),%RCX

(204) 0x42e5b1 ADD	%RBX,%RCX

(204) 0x42e5b4 LEA	(%R10,%RAX,1),%R9

(204) 0x42e5b8 VSUBPD	(%R15,%RCX,8),%YMM8,%YMM9

(204) 0x42e5be MOV	0x70(%RSP),%RCX

(204) 0x42e5c3 VMOVQ	%XMM5,%R10

(204) 0x42e5c8 ADD	%RBX,%R9

(204) 0x42e5cb VADDPD	(%R15,%R9,8),%YMM9,%YMM10

(204) 0x42e5d1 MOV	0x58(%RSP),%R15

(204) 0x42e5d6 LEA	(%R15,%RAX,1),%R9

(204) 0x42e5da ADD	%RCX,%RAX

(204) 0x42e5dd ADD	%RBX,%RAX

(204) 0x42e5e0 ADD	%RBX,%R9

(204) 0x42e5e3 VMOVUPD	(%R10,%R9,8),%YMM11

(204) 0x42e5e9 VSUBPD	(%R10,%RAX,8),%YMM11,%YMM15

(204) 0x42e5ef MOV	%EDX,%EAX

(204) 0x42e5f1 VFMADD132PD	(%RDI),%YMM15,%YMM8

(204) 0x42e5f6 VDIVPD	%YMM0,%YMM10,%YMM2

(204) 0x42e5fa AND	$-0x4,%EAX

(204) 0x42e5fd ADD	%EAX,0x7c(%RSP)

(204) 0x42e601 ADD	%EAX,%ESI

(204) 0x42e603 AND	$0x3,%EDX

(204) 0x42e606 VDIVPD	%YMM10,%YMM8,%YMM3

(204) 0x42e60b VMOVUPD	%YMM2,(%R8)

(204) 0x42e610 VMOVUPD	%YMM3,(%RDI)

(204) 0x42e614 JE	42e82a

(204) 0x42e61a MOV	0x28(%RSP),%RDI

(204) 0x42e61f MOVSXD	%ESI,%RAX

(204) 0x42e622 VMOVQ	%XMM14,%R8

(204) 0x42e627 MOV	0x30(%RSP),%R10

(204) 0x42e62c VMOVQ	%XMM13,%R12

(204) 0x42e631 VMOVQ	%XMM6,%R9

(204) 0x42e636 LEA	(%RDI,%RAX,1),%RDX

(204) 0x42e63a LEA	(%R10,%RAX,1),%R13

(204) 0x42e63e LEA	(%R8,%RDX,8),%RCX

(204) 0x42e642 MOV	0x40(%RSP),%R8

(204) 0x42e647 VMOVSD	(%R12,%R13,8),%XMM4

(204) 0x42e64d VMOVQ	%XMM6,%RDX

(204) 0x42e652 VMULSD	(%RCX),%XMM4,%XMM7

(204) 0x42e656 VMOVQ	%XMM12,%R13

(204) 0x42e65b LEA	(%R8,%RAX,1),%R15

(204) 0x42e65f VSUBSD	(%R9,%R15,8),%XMM7,%XMM8

(204) 0x42e665 MOV	0x38(%RSP),%R9

(204) 0x42e66a MOV	0x48(%RSP),%R15

(204) 0x42e66f LEA	(%R9,%RAX,1),%RBX

(204) 0x42e673 LEA	(%R15,%RAX,1),%R12

(204) 0x42e677 VADDSD	(%RDX,%RBX,8),%XMM8,%XMM9

(204) 0x42e67c LEA	(%R13,%R12,8),%RDX

(204) 0x42e681 MOV	0x58(%RSP),%R13

(204) 0x42e686 MOV	0x70(%RSP),%R12

(204) 0x42e68b VMOVQ	%XMM5,%RBX

(204) 0x42e690 ADD	%RAX,%R13

(204) 0x42e693 ADD	%RAX,%R12

(204) 0x42e696 VMOVSD	(%RBX,%R13,8),%XMM10

(204) 0x42e69c MOV	0x50(%RSP),%R13

(204) 0x42e6a1 VSUBSD	(%RBX,%R12,8),%XMM10,%XMM11

(204) 0x42e6a7 MOV	0x68(%RSP),%RBX

(204) 0x42e6ac VFMADD132SD	(%RDX),%XMM11,%XMM7

(204) 0x42e6b1 VDIVSD	%XMM9,%XMM7,%XMM2

(204) 0x42e6b6 LEA	(%R13,%RAX,1),%R12

(204) 0x42e6bb ADD	%RBX,%RAX

(204) 0x42e6be VADDSD	(%R11,%R12,8),%XMM4,%XMM15

(204) 0x42e6c4 VSUBSD	(%R11,%RAX,8),%XMM15,%XMM1

(204) 0x42e6ca MOV	0x7c(%RSP),%EAX

(204) 0x42e6ce VDIVSD	%XMM1,%XMM9,%XMM0

(204) 0x42e6d2 VMOVSD	%XMM0,(%RCX)

(204) 0x42e6d6 VMOVSD	%XMM2,(%RDX)

(204) 0x42e6da MOV	0x60(%RSP),%EDX

(204) 0x42e6de LEA	0x1(%RAX),%ECX

(204) 0x42e6e1 CMP	%EDX,%ECX

(204) 0x42e6e3 JAE	42e82a

(204) 0x42e6e9 LEA	0x1(%RSI),%EAX

(204) 0x42e6ec VMOVQ	%XMM14,%R12

(204) 0x42e6f1 VMOVQ	%XMM13,%RBX

(204) 0x42e6f6 CLTQ

(204) 0x42e6f8 LEA	(%RDI,%RAX,1),%R13

(204) 0x42e6fc LEA	(%R10,%RAX,1),%RDX

(204) 0x42e700 LEA	(%R12,%R13,8),%RCX

(204) 0x42e704 LEA	(%R8,%RAX,1),%R13

(204) 0x42e708 VMOVQ	%XMM6,%R12

(204) 0x42e70d VMOVSD	(%RBX,%RDX,8),%XMM4

(204) 0x42e712 LEA	(%R9,%RAX,1),%RDX

(204) 0x42e716 VMULSD	(%RCX),%XMM4,%XMM7

(204) 0x42e71a VMOVQ	%XMM12,%RBX

(204) 0x42e71f VSUBSD	(%R12,%R13,8),%XMM7,%XMM3

(204) 0x42e725 LEA	(%R15,%RAX,1),%R13

(204) 0x42e729 VADDSD	(%R12,%RDX,8),%XMM3,%XMM8

(204) 0x42e72f MOV	0x70(%RSP),%R12

(204) 0x42e734 LEA	(%RBX,%R13,8),%RDX

(204) 0x42e738 MOV	0x58(%RSP),%R13

(204) 0x42e73d VMOVQ	%XMM5,%RBX

(204) 0x42e742 ADD	%RAX,%R12

(204) 0x42e745 ADD	%RAX,%R13

(204) 0x42e748 VMOVSD	(%RBX,%R13,8),%XMM9

(204) 0x42e74e MOV	0x50(%RSP),%R13

(204) 0x42e753 VSUBSD	(%RBX,%R12,8),%XMM9,%XMM10

(204) 0x42e759 VFMADD132SD	(%RDX),%XMM10,%XMM7

(204) 0x42e75e VDIVSD	%XMM8,%XMM7,%XMM0

(204) 0x42e763 LEA	(%R13,%RAX,1),%R12

(204) 0x42e768 VADDSD	(%R11,%R12,8),%XMM4,%XMM11

(204) 0x42e76e MOV	0x68(%RSP),%R12

(204) 0x42e773 ADD	%R12,%RAX

(204) 0x42e776 VSUBSD	(%R11,%RAX,8),%XMM11,%XMM15

(204) 0x42e77c MOV	0x7c(%RSP),%EAX

(204) 0x42e780 VDIVSD	%XMM15,%XMM8,%XMM1

(204) 0x42e785 VMOVSD	%XMM1,(%RCX)

(204) 0x42e789 MOV	0x60(%RSP),%ECX

(204) 0x42e78d VMOVSD	%XMM0,(%RDX)

(204) 0x42e791 ADD	$0x2,%EAX

(204) 0x42e794 CMP	%ECX,%EAX

(204) 0x42e796 JAE	42e82a

(204) 0x42e79c ADD	$0x2,%ESI

(204) 0x42e79f VMOVQ	%XMM14,%RDX

(204) 0x42e7a4 VMOVQ	%XMM13,%RBX

(204) 0x42e7a9 MOVSXD	%ESI,%RSI

(204) 0x42e7ac VMOVQ	%XMM6,%RAX

(204) 0x42e7b1 ADD	%RSI,%RDI

(204) 0x42e7b4 ADD	%RSI,%R10

(204) 0x42e7b7 ADD	%RSI,%R9

(204) 0x42e7ba ADD	%RSI,%R8

(204) 0x42e7bd VMOVSD	(%RBX,%R10,8),%XMM14

(204) 0x42e7c3 LEA	(%RDX,%RDI,8),%RCX

(204) 0x42e7c7 MOV	0x70(%RSP),%R10

(204) 0x42e7cc MOV	0x58(%RSP),%RDI

(204) 0x42e7d1 VMULSD	(%RCX),%XMM14,%XMM13

(204) 0x42e7d5 ADD	%RSI,%R15

(204) 0x42e7d8 VSUBSD	(%RAX,%R8,8),%XMM13,%XMM6

(204) 0x42e7de VADDSD	(%RAX,%R9,8),%XMM6,%XMM2

(204) 0x42e7e4 VMOVQ	%XMM12,%R9

(204) 0x42e7e9 VMOVQ	%XMM5,%RBX

(204) 0x42e7ee ADD	%RSI,%R13

(204) 0x42e7f1 ADD	%RSI,%R12

(204) 0x42e7f4 LEA	(%R9,%R15,8),%RDX

(204) 0x42e7f8 VADDSD	(%R11,%R13,8),%XMM14,%XMM4

(204) 0x42e7fe VSUBSD	(%R11,%R12,8),%XMM4,%XMM7

(204) 0x42e804 VDIVSD	%XMM7,%XMM2,%XMM3

(204) 0x42e808 ADD	%RSI,%RDI

(204) 0x42e80b ADD	%RSI,%R10

(204) 0x42e80e VMOVSD	(%RBX,%RDI,8),%XMM12

(204) 0x42e813 VSUBSD	(%RBX,%R10,8),%XMM12,%XMM5

(204) 0x42e819 VFMADD132SD	(%RDX),%XMM5,%XMM13

(204) 0x42e81e VMOVSD	%XMM3,(%RCX)

(204) 0x42e822 VDIVSD	%XMM2,%XMM13,%XMM8

(204) 0x42e826 VMOVSD	%XMM8,(%RDX)

(204) 0x42e82a MOV	0x60(%RSP),%R11D

(204) 0x42e82f MOV	%R11D,0x7c(%RSP)

(204) 0x42e834 INC	%R14

(204) 0x42e837 CMP	%R14D,0x20(%RSP)

(204) 0x42e83c JLE	42e860

(204) 0x42e83e MOV	0x18(%RSP),%ESI

(204) 0x42e842 MOV	0x7c(%RSP),%ECX

(204) 0x42e846 MOV	0x1c(%RSP),%EAX

(204) 0x42e84a MOV	0x24(%RSP),%R8D

(204) 0x42e84f SUB	%ECX,%ESI

(204) 0x42e851 MOV	%EAX,0x64(%RSP)

(204) 0x42e855 JMP	42e250

0x42e85a NOPW	(%RAX,%RAX,1)

0x42e860 VZEROUPPER

0x42e863 LEA	-0x28(%RBP),%RSP

0x42e867 POP	%RBX

0x42e868 POP	%R12

0x42e86a POP	%R13

0x42e86c POP	%R14

0x42e86e POP	%R15

0x42e870 POP	%RBP

0x42e871 RET

0x42e872 NOPW	%CS:(%RAX,%RAX,1)

0x42e87d NOPL	(%RAX)

(204) 0x42e880 MOV	0x64(%RSP),%ESI

(204) 0x42e884 XOR	%EBX,%EBX

(204) 0x42e886 JMP	42e51c

0x42e88b INC	%R9D

0x42e88e XOR	%EDX,%EDX

0x42e890 JMP	42e1e3

0x42e895 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.87+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.14+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:220	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:81	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.10+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:220	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.75 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.13 cycles (1.19x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:211

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	81
nb uops	81
loop length	299
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

all	8%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42e160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x3c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%R13),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x2,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RBX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42e863 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x2(%RCX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R15D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42e863 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x24(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42e88b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x72b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R9,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R11D,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R11D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42e863 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1c(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVQ (%R13),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x24(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x20(%R13),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ 0x8(%R13),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x28(%R13),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R9D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R10D,0x7c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
VMOVQ 0x18(%R13),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDI,0x64(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42e1e3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.75 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:210
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:211

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 24 bytes.

General properties

nb instructions	81
nb uops	81
loop length	299
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	5.25	5.25	5.25	5.25	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

all	8%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.00 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42e160

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x3c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%R13),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x2,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RBX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA 0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42e863 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x2(%RCX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R15D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42e863 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x24(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42e88b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x72b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R9,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R11D,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R11D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42e863 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x1c(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVQ (%R13),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x24(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x20(%R13),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ 0x8(%R13),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x28(%R13),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R9D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %R10D,0x7c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
VMOVQ 0x18(%R13),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDI,0x64(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42e1e3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.7+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.55	1.30
▼Loop 204 - advec_cell.cpp:210-216 - exec–	0.00	0.01
○Loop 205 - advec_cell.cpp:211-216 - exec	3.55	1.30

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code