OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:146-150 [...]	Coverage (incl. loops): 1.32% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 146 - 150

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

148:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

149:           pre_vol(i, j) = volume(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j);

150:           post_vol(i, j) = volume(i, j);

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42dc10 PUSH	%RBP

0x42dc11 MOV	%RSP,%RBP

0x42dc14 PUSH	%R15

0x42dc16 PUSH	%R14

0x42dc18 PUSH	%R13

0x42dc1a PUSH	%R12

0x42dc1c PUSH	%RBX

0x42dc1d MOV	%RDI,%R15

0x42dc20 AND	$-0x40,%RSP

0x42dc24 SUB	$0x40,%RSP

0x42dc28 MOV	0x28(%RDI),%EAX

0x42dc2b MOV	0x2c(%RDI),%EDX

0x42dc2e MOV	0x20(%RDI),%EDI

0x42dc31 MOV	0x24(%R15),%ECX

0x42dc35 ADD	$0x4,%EDX

0x42dc38 LEA	-0x1(%RDI),%ESI

0x42dc3b LEA	-0x1(%RAX),%EBX

0x42dc3e MOV	%EDX,0x14(%RSP)

0x42dc42 MOV	%ESI,0x10(%RSP)

0x42dc46 CMP	%EDX,%EBX

0x42dc48 JGE	42e113

0x42dc4e MOV	%EDX,%R13D

0x42dc51 LEA	0x4(%RCX),%R14D

0x42dc55 SUB	%EBX,%R13D

0x42dc58 CMP	%R14D,%ESI

0x42dc5b JGE	42e113

0x42dc61 MOV	%R14D,%R8D

0x42dc64 SUB	%ESI,%R8D

0x42dc67 MOV	%R8D,0x38(%RSP)

0x42dc6c CALL	404630 <omp_get_num_threads@plt>

0x42dc71 MOV	%EAX,%R12D

0x42dc74 CALL	404520 <omp_get_thread_num@plt>

0x42dc79 MOV	0x38(%RSP),%R10D

0x42dc7e XOR	%EDX,%EDX

0x42dc80 MOV	%EAX,%R9D

0x42dc83 IMUL	%R10D,%R13D

0x42dc87 MOV	%R13D,%EAX

0x42dc8a DIV	%R12D

0x42dc8d MOV	%EAX,%R12D

0x42dc90 CMP	%EDX,%R9D

0x42dc93 JB	42e14d

0x42dc99 IMUL	%R12D,%R9D

0x42dc9d LEA	(%R9,%RDX,1),%ESI

0x42dca1 LEA	(%R12,%RSI,1),%R11D

0x42dca5 MOV	%R11D,0xc(%RSP)

0x42dcaa CMP	%R11D,%ESI

0x42dcad JAE	42e113

0x42dcb3 MOV	%ESI,%EAX

0x42dcb5 XOR	%EDX,%EDX

0x42dcb7 MOV	0x10(%RSP),%EDI

0x42dcbb VMOVQ	(%R15),%XMM12

0x42dcc0 DIVL	0x38(%RSP)

0x42dcc4 VMOVQ	0x8(%R15),%XMM3

0x42dcca VMOVQ	0x10(%R15),%XMM10

0x42dcd0 VMOVQ	0x18(%R15),%XMM14

0x42dcd6 ADD	%EDX,%EDI

0x42dcd8 LEA	(%RAX,%RBX,1),%R15D

0x42dcdc SUB	%EDI,%R14D

0x42dcdf MOV	%EDI,0x3c(%RSP)

0x42dce3 MOVSXD	%R15D,%RDI

0x42dce6 NOPW	%CS:(%RAX,%RAX,1)

(202) 0x42dcf0 CMP	%R14D,%R12D

(202) 0x42dcf3 MOV	%R14D,%EDX

(202) 0x42dcf6 CMOVBE	%R12D,%EDX

(202) 0x42dcfa LEA	(%RSI,%RDX,1),%R12D

(202) 0x42dcfe CMP	%R12D,%ESI

(202) 0x42dd01 JAE	42e130

(202) 0x42dd07 VMOVQ	%XMM3,%R8

(202) 0x42dd0c VMOVQ	%XMM12,%RBX

(202) 0x42dd11 LEA	0x1(%RDI),%R9

(202) 0x42dd15 MOV	(%R8),%R10

(202) 0x42dd18 VMOVQ	%XMM10,%RAX

(202) 0x42dd1d MOV	(%RBX),%RCX

(202) 0x42dd20 MOV	%R9,0x18(%RSP)

(202) 0x42dd25 MOV	(%RAX),%R14

(202) 0x42dd28 VMOVQ	%XMM14,%R15

(202) 0x42dd2d VMOVQ	0x10(%RBX),%XMM6

(202) 0x42dd32 LEA	-0x1(%RDX),%EBX

(202) 0x42dd35 VMOVQ	0x10(%RAX),%XMM5

(202) 0x42dd3a VMOVQ	0x10(%R15),%XMM4

(202) 0x42dd40 MOV	0x10(%R8),%R13

(202) 0x42dd44 IMUL	%R10,%R9

(202) 0x42dd48 IMUL	%RDI,%RCX

(202) 0x42dd4c IMUL	%RDI,%R14

(202) 0x42dd50 IMUL	(%R15),%RDI

(202) 0x42dd54 MOV	%R9,%R11

(202) 0x42dd57 SUB	%R10,%R11

(202) 0x42dd5a MOV	%RCX,0x20(%RSP)

(202) 0x42dd5f MOV	%R11,0x28(%RSP)

(202) 0x42dd64 MOV	%R14,0x30(%RSP)

(202) 0x42dd69 CMP	$0x6,%EBX

(202) 0x42dd6c JBE	42e140

(202) 0x42dd72 MOVSXD	0x3c(%RSP),%RAX

(202) 0x42dd77 VMOVQ	%XMM5,%R8

(202) 0x42dd7c LEA	(%R11,%RAX,1),%RBX

(202) 0x42dd80 LEA	(%R14,%RAX,1),%R14

(202) 0x42dd84 LEA	(%RCX,%RAX,1),%R10

(202) 0x42dd88 VMOVQ	%XMM6,%RCX

(202) 0x42dd8d LEA	(%R13,%RBX,8),%R11

(202) 0x42dd92 LEA	(%R8,%R14,8),%RBX

(202) 0x42dd96 MOV	%EDX,%R14D

(202) 0x42dd99 LEA	(%R9,%RAX,1),%R15

(202) 0x42dd9d SHR	$0x3,%R14D

(202) 0x42dda1 SAL	$0x6,%R14

(202) 0x42dda5 LEA	-0x40(%R14),%R8

(202) 0x42dda9 ADD	%RDI,%RAX

(202) 0x42ddac LEA	(%RCX,%R10,8),%R10

(202) 0x42ddb0 VMOVQ	%XMM4,%RCX

(202) 0x42ddb5 SHR	$0x6,%R8

(202) 0x42ddb9 INC	%R8

(202) 0x42ddbc LEA	(%RCX,%RAX,8),%RCX

(202) 0x42ddc0 XOR	%EAX,%EAX

(202) 0x42ddc2 LEA	(%R13,%R15,8),%R15

(202) 0x42ddc7 AND	$0x3,%R8D

(202) 0x42ddcb JE	42de6b

(202) 0x42ddd1 CMP	$0x1,%R8

(202) 0x42ddd5 JE	42de34

(202) 0x42ddd7 CMP	$0x2,%R8

(202) 0x42dddb JE	42de06

(202) 0x42dddd VMOVUPD	(%R10),%ZMM13

(202) 0x42dde3 VADDPD	(%R15),%ZMM13,%ZMM0

(202) 0x42dde9 MOV	$0x40,%EAX

(202) 0x42ddee VSUBPD	(%R11),%ZMM0,%ZMM1

(202) 0x42ddf4 VMOVUPD	%ZMM1,(%RBX)

(202) 0x42ddfa VMOVUPD	(%R10),%ZMM2

(202) 0x42de00 VMOVUPD	%ZMM2,(%RCX)

(202) 0x42de06 VMOVUPD	(%R10,%RAX,1),%ZMM7

(202) 0x42de0d VADDPD	(%R15,%RAX,1),%ZMM7,%ZMM8

(202) 0x42de14 VSUBPD	(%R11,%RAX,1),%ZMM8,%ZMM9

(202) 0x42de1b VMOVUPD	%ZMM9,(%RBX,%RAX,1)

(202) 0x42de22 VMOVUPD	(%R10,%RAX,1),%ZMM11

(202) 0x42de29 VMOVUPD	%ZMM11,(%RCX,%RAX,1)

(202) 0x42de30 ADD	$0x40,%RAX

(202) 0x42de34 VMOVUPD	(%R10,%RAX,1),%ZMM15

(202) 0x42de3b VADDPD	(%R15,%RAX,1),%ZMM15,%ZMM13

(202) 0x42de42 VSUBPD	(%R11,%RAX,1),%ZMM13,%ZMM0

(202) 0x42de49 VMOVUPD	%ZMM0,(%RBX,%RAX,1)

(202) 0x42de50 VMOVUPD	(%R10,%RAX,1),%ZMM1

(202) 0x42de57 VMOVUPD	%ZMM1,(%RCX,%RAX,1)

(202) 0x42de5e ADD	$0x40,%RAX

(202) 0x42de62 CMP	%R14,%RAX

(202) 0x42de65 JE	42df34

  (203) 0x42de6b VMOVUPD	(%R10,%RAX,1),%ZMM2

  (203) 0x42de72 VADDPD	(%R15,%RAX,1),%ZMM2,%ZMM7

  (203) 0x42de79 VSUBPD	(%R11,%RAX,1),%ZMM7,%ZMM8

  (203) 0x42de80 VMOVUPD	%ZMM8,(%RBX,%RAX,1)

  (203) 0x42de87 VMOVUPD	(%R10,%RAX,1),%ZMM9

  (203) 0x42de8e VMOVUPD	%ZMM9,(%RCX,%RAX,1)

  (203) 0x42de95 VMOVUPD	0x40(%R10,%RAX,1),%ZMM11

  (203) 0x42de9d VADDPD	0x40(%R15,%RAX,1),%ZMM11,%ZMM15

  (203) 0x42dea5 VSUBPD	0x40(%R11,%RAX,1),%ZMM15,%ZMM13

  (203) 0x42dead VMOVUPD	%ZMM13,0x40(%RBX,%RAX,1)

  (203) 0x42deb5 VMOVUPD	0x40(%R10,%RAX,1),%ZMM0

  (203) 0x42debd VMOVUPD	%ZMM0,0x40(%RCX,%RAX,1)

  (203) 0x42dec5 VMOVUPD	0x80(%R10,%RAX,1),%ZMM1

  (203) 0x42decd VADDPD	0x80(%R15,%RAX,1),%ZMM1,%ZMM2

  (203) 0x42ded5 VSUBPD	0x80(%R11,%RAX,1),%ZMM2,%ZMM7

  (203) 0x42dedd VMOVUPD	%ZMM7,0x80(%RBX,%RAX,1)

  (203) 0x42dee5 VMOVUPD	0x80(%R10,%RAX,1),%ZMM8

  (203) 0x42deed VMOVUPD	%ZMM8,0x80(%RCX,%RAX,1)

  (203) 0x42def5 VMOVUPD	0xc0(%R10,%RAX,1),%ZMM9

  (203) 0x42defd VADDPD	0xc0(%R15,%RAX,1),%ZMM9,%ZMM11

  (203) 0x42df05 VSUBPD	0xc0(%R11,%RAX,1),%ZMM11,%ZMM15

  (203) 0x42df0d VMOVUPD	%ZMM15,0xc0(%RBX,%RAX,1)

  (203) 0x42df15 VMOVUPD	0xc0(%R10,%RAX,1),%ZMM13

  (203) 0x42df1d VMOVUPD	%ZMM13,0xc0(%RCX,%RAX,1)

  (203) 0x42df25 ADD	$0x100,%RAX

  (203) 0x42df2b CMP	%R14,%RAX

  (203) 0x42df2e JNE	42de6b

(202) 0x42df34 MOV	0x3c(%RSP),%R10D

(202) 0x42df39 MOV	%EDX,%R11D

(202) 0x42df3c AND	$-0x8,%R11D

(202) 0x42df40 ADD	%R11D,%ESI

(202) 0x42df43 LEA	(%R11,%R10,1),%R8D

(202) 0x42df47 TEST	$0x7,%DL

(202) 0x42df4a JE	42e0de

(202) 0x42df50 SUB	%R11D,%EDX

(202) 0x42df53 LEA	-0x1(%RDX),%R15D

(202) 0x42df57 CMP	$0x2,%R15D

(202) 0x42df5b JBE	42dfe1

(202) 0x42df61 MOVSXD	0x3c(%RSP),%RCX

(202) 0x42df66 MOV	0x20(%RSP),%RBX

(202) 0x42df6b VMOVQ	%XMM6,%RAX

(202) 0x42df70 LEA	(%RBX,%RCX,1),%R14

(202) 0x42df74 MOV	0x28(%RSP),%RBX

(202) 0x42df79 LEA	(%R9,%RCX,1),%R15

(202) 0x42df7d ADD	%R11,%R14

(202) 0x42df80 ADD	%R11,%R15

(202) 0x42df83 LEA	(%RAX,%R14,8),%R10

(202) 0x42df87 MOV	0x30(%RSP),%RAX

(202) 0x42df8c VMOVUPD	(%R10),%YMM0

(202) 0x42df91 VADDPD	(%R13,%R15,8),%YMM0,%YMM1

(202) 0x42df98 LEA	(%RBX,%RCX,1),%R14

(202) 0x42df9c VMOVQ	%XMM5,%RBX

(202) 0x42dfa1 ADD	%R11,%R14

(202) 0x42dfa4 VSUBPD	(%R13,%R14,8),%YMM1,%YMM2

(202) 0x42dfab LEA	(%RAX,%RCX,1),%R15

(202) 0x42dfaf ADD	%RDI,%RCX

(202) 0x42dfb2 ADD	%R11,%R15

(202) 0x42dfb5 ADD	%R11,%RCX

(202) 0x42dfb8 VMOVQ	%XMM4,%R11

(202) 0x42dfbd VMOVUPD	%YMM2,(%RBX,%R15,8)

(202) 0x42dfc3 VMOVUPD	(%R10),%YMM7

(202) 0x42dfc8 VMOVUPD	%YMM7,(%R11,%RCX,8)

(202) 0x42dfce MOV	%EDX,%ECX

(202) 0x42dfd0 AND	$-0x4,%ECX

(202) 0x42dfd3 ADD	%ECX,%R8D

(202) 0x42dfd6 ADD	%ECX,%ESI

(202) 0x42dfd8 AND	$0x3,%EDX

(202) 0x42dfdb JE	42e0de

(202) 0x42dfe1 MOV	0x20(%RSP),%RBX

(202) 0x42dfe6 MOV	0x28(%RSP),%R15

(202) 0x42dfeb MOV	0x30(%RSP),%R11

(202) 0x42dff0 MOVSXD	%R8D,%RAX

(202) 0x42dff3 VMOVQ	%XMM6,%R10

(202) 0x42dff8 LEA	(%R9,%RAX,1),%R14

(202) 0x42dffc VMOVSD	(%R13,%R14,8),%XMM8

(202) 0x42e003 LEA	(%RBX,%RAX,1),%RDX

(202) 0x42e007 LEA	(%R11,%RAX,1),%RCX

(202) 0x42e00b LEA	(%R10,%RDX,8),%RDX

(202) 0x42e00f LEA	(%R15,%RAX,1),%R10

(202) 0x42e013 ADD	%RDI,%RAX

(202) 0x42e016 VADDSD	(%RDX),%XMM8,%XMM9

(202) 0x42e01a VSUBSD	(%R13,%R10,8),%XMM9,%XMM11

(202) 0x42e021 VMOVQ	%XMM5,%R10

(202) 0x42e026 VMOVSD	%XMM11,(%R10,%RCX,8)

(202) 0x42e02c VMOVSD	(%RDX),%XMM15

(202) 0x42e030 VMOVQ	%XMM4,%RDX

(202) 0x42e035 VMOVSD	%XMM15,(%RDX,%RAX,8)

(202) 0x42e03a LEA	0x1(%RSI),%EAX

(202) 0x42e03d CMP	%R12D,%EAX

(202) 0x42e040 JAE	42e0de

(202) 0x42e046 LEA	0x1(%R8),%EAX

(202) 0x42e04a VMOVQ	%XMM6,%RCX

(202) 0x42e04f ADD	$0x2,%ESI

(202) 0x42e052 CLTQ

(202) 0x42e054 LEA	(%RBX,%RAX,1),%R14

(202) 0x42e058 LEA	(%RCX,%R14,8),%RDX

(202) 0x42e05c LEA	(%R9,%RAX,1),%R14

(202) 0x42e060 LEA	(%R11,%RAX,1),%RCX

(202) 0x42e064 VMOVSD	(%R13,%R14,8),%XMM13

(202) 0x42e06b LEA	(%R15,%RAX,1),%R14

(202) 0x42e06f VADDSD	(%RDX),%XMM13,%XMM0

(202) 0x42e073 ADD	%RDI,%RAX

(202) 0x42e076 VSUBSD	(%R13,%R14,8),%XMM0,%XMM1

(202) 0x42e07d VMOVSD	%XMM1,(%R10,%RCX,8)

(202) 0x42e083 VMOVQ	%XMM4,%R10

(202) 0x42e088 VMOVSD	(%RDX),%XMM2

(202) 0x42e08c VMOVSD	%XMM2,(%R10,%RAX,8)

(202) 0x42e092 CMP	%R12D,%ESI

(202) 0x42e095 JAE	42e0de

(202) 0x42e097 ADD	$0x2,%R8D

(202) 0x42e09b VMOVQ	%XMM6,%RSI

(202) 0x42e0a0 MOVSXD	%R8D,%R8

(202) 0x42e0a3 ADD	%R8,%RBX

(202) 0x42e0a6 ADD	%R8,%R9

(202) 0x42e0a9 ADD	%R8,%R15

(202) 0x42e0ac ADD	%R8,%R11

(202) 0x42e0af LEA	(%RSI,%RBX,8),%RBX

(202) 0x42e0b3 VMOVSD	(%R13,%R9,8),%XMM6

(202) 0x42e0ba ADD	%RDI,%R8

(202) 0x42e0bd VADDSD	(%RBX),%XMM6,%XMM7

(202) 0x42e0c1 VSUBSD	(%R13,%R15,8),%XMM7,%XMM8

(202) 0x42e0c8 VMOVQ	%XMM5,%R13

(202) 0x42e0cd VMOVSD	%XMM8,(%R13,%R11,8)

(202) 0x42e0d4 VMOVSD	(%RBX),%XMM5

(202) 0x42e0d8 VMOVSD	%XMM5,(%R10,%R8,8)

(202) 0x42e0de MOV	%R12D,%ESI

(202) 0x42e0e1 MOV	0x18(%RSP),%RDI

(202) 0x42e0e6 CMP	%EDI,0x14(%RSP)

(202) 0x42e0ea JLE	42e110

(202) 0x42e0ec MOV	0xc(%RSP),%R12D

(202) 0x42e0f1 MOV	0x10(%RSP),%R9D

(202) 0x42e0f6 MOV	0x38(%RSP),%R14D

(202) 0x42e0fb SUB	%ESI,%R12D

(202) 0x42e0fe MOV	%R9D,0x3c(%RSP)

(202) 0x42e103 JMP	42dcf0

0x42e108 NOPL	(%RAX,%RAX,1)

0x42e110 VZEROUPPER

0x42e113 LEA	-0x28(%RBP),%RSP

0x42e117 POP	%RBX

0x42e118 POP	%R12

0x42e11a POP	%R13

0x42e11c POP	%R14

0x42e11e POP	%R15

0x42e120 POP	%RBP

0x42e121 RET

0x42e122 NOPW	%CS:(%RAX,%RAX,1)

0x42e12d NOPL	(%RAX)

(202) 0x42e130 LEA	0x1(%RDI),%R14

(202) 0x42e134 MOV	%R14,0x18(%RSP)

(202) 0x42e139 JMP	42e0e1

0x42e13b NOPL	(%RAX,%RAX,1)

(202) 0x42e140 MOV	0x3c(%RSP),%R8D

(202) 0x42e145 XOR	%R11D,%R11D

(202) 0x42e148 JMP	42df50

0x42e14d INC	%R12D

0x42e150 XOR	%EDX,%EDX

0x42e152 JMP	42dc99

0x42e157 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.78+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.28+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:146	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:81	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:146-150
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:146-150
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.25 cycles (1.30x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:149

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	78
nb uops	76
loop length	288
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.50
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (5.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42dc10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%R15),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RDI),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ESI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42e113 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x503>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42e113 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x503>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ESI,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x38(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10D,%R13D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42e14d <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x53d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R12D,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R9,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R12,%RSI,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R11D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R11D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42e113 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x503>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVQ (%R15),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x38(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%R15),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R15),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R15),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RBX,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EDI,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %R15D,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42dc99 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x89>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:146-150
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:146-150
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.25 cycles (1.30x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:148
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:149

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	78
nb uops	76
loop length	288
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.50
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	14%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (5.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42dc10

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%R15),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RDI),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ESI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42e113 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x503>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42e113 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x503>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ESI,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x38(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R10D,%R13D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42e14d <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x53d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R12D,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R9,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R12,%RSI,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R11D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R11D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42e113 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x503>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVQ (%R15),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x38(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%R15),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R15),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R15),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RAX,%RBX,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EDI,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %R15D,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42dc99 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.5+0x89>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.32	0.48
▼Loop 202 - advec_cell.cpp:146-150 - exec–	0.00	0.01
○Loop 203 - advec_cell.cpp:149-150 - exec	1.32	0.48

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code