OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:136-140 [...]	Coverage (incl. loops): 1.53% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 136 - 140

--------------------------------------------------------------------------------

136: #pragma omp parallel for simd collapse(2)

137:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

138:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

139:           pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

140:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42d4a0 PUSH	%RBP

0x42d4a1 MOV	%RSP,%RBP

0x42d4a4 PUSH	%R15

0x42d4a6 PUSH	%R14

0x42d4a8 PUSH	%R13

0x42d4aa PUSH	%R12

0x42d4ac PUSH	%RBX

0x42d4ad MOV	%RDI,%R13

0x42d4b0 AND	$-0x40,%RSP

0x42d4b4 ADD	$-0x80,%RSP

0x42d4b8 MOV	0x30(%RDI),%EAX

0x42d4bb MOV	0x34(%RDI),%EDX

0x42d4be MOV	0x28(%RDI),%EBX

0x42d4c1 MOV	0x2c(%R13),%ECX

0x42d4c5 ADD	$0x4,%EDX

0x42d4c8 LEA	-0x1(%RBX),%EDI

0x42d4cb LEA	-0x1(%RAX),%R14D

0x42d4cf MOV	%EDX,0x34(%RSP)

0x42d4d3 MOV	%EDI,0x30(%RSP)

0x42d4d7 CMP	%EDX,%R14D

0x42d4da JGE	42dbc3

0x42d4e0 MOV	%EDX,%EBX

0x42d4e2 LEA	0x4(%RCX),%R15D

0x42d4e6 SUB	%R14D,%EBX

0x42d4e9 CMP	%R15D,%EDI

0x42d4ec JGE	42dbc3

0x42d4f2 MOV	%R15D,%ESI

0x42d4f5 SUB	%EDI,%ESI

0x42d4f7 MOV	%ESI,0x60(%RSP)

0x42d4fb CALL	404630 <omp_get_num_threads@plt>

0x42d500 MOV	%EAX,%R12D

0x42d503 CALL	404520 <omp_get_thread_num@plt>

0x42d508 XOR	%EDX,%EDX

0x42d50a MOV	%EAX,%R9D

0x42d50d MOV	0x60(%RSP),%EAX

0x42d511 IMUL	%EBX,%EAX

0x42d514 DIV	%R12D

0x42d517 MOV	%EAX,%R8D

0x42d51a CMP	%EDX,%R9D

0x42d51d JB	42dbfd

0x42d523 IMUL	%R8D,%R9D

0x42d527 LEA	(%R9,%RDX,1),%EDI

0x42d52b LEA	(%R8,%RDI,1),%R10D

0x42d52f MOV	%R10D,0x2c(%RSP)

0x42d534 CMP	%R10D,%EDI

0x42d537 JAE	42dbc3

0x42d53d MOV	%EDI,%EAX

0x42d53f XOR	%EDX,%EDX

0x42d541 MOV	0x30(%RSP),%R11D

0x42d546 VMOVQ	(%R13),%XMM16

0x42d54d DIVL	0x60(%RSP)

0x42d551 VMOVQ	0x10(%R13),%XMM15

0x42d557 VMOVQ	0x8(%R13),%XMM14

0x42d55d VMOVQ	0x18(%R13),%XMM13

0x42d563 VMOVQ	0x20(%R13),%XMM12

0x42d569 ADD	%EDX,%R11D

0x42d56c LEA	(%RAX,%R14,1),%R13D

0x42d570 MOV	%R15D,%EDX

0x42d573 SUB	%R11D,%EDX

0x42d576 MOVSXD	%R13D,%RSI

0x42d579 MOV	%R11D,0x70(%RSP)

0x42d57e XCHG	%AX,%AX

(200) 0x42d580 CMP	%EDX,%R8D

(200) 0x42d583 CMOVBE	%R8D,%EDX

(200) 0x42d587 LEA	(%RDI,%RDX,1),%R8D

(200) 0x42d58b MOV	%R8D,0x64(%RSP)

(200) 0x42d590 CMP	%R8D,%EDI

(200) 0x42d593 JAE	42dbe0

(200) 0x42d599 VMOVQ	%XMM16,%RCX

(200) 0x42d59f VMOVQ	%XMM15,%R15

(200) 0x42d5a4 LEA	0x1(%RSI),%R9

(200) 0x42d5a8 VMOVQ	%XMM14,%RAX

(200) 0x42d5ad VMOVQ	%XMM13,%R8

(200) 0x42d5b2 MOV	(%R15),%R12

(200) 0x42d5b5 MOV	(%RCX),%R11

(200) 0x42d5b8 VMOVQ	0x10(%RCX),%XMM19

(200) 0x42d5bf MOV	0x10(%R15),%RBX

(200) 0x42d5c3 MOV	(%RAX),%RCX

(200) 0x42d5c6 MOV	(%R8),%R15

(200) 0x42d5c9 VMOVQ	%XMM12,%R14

(200) 0x42d5ce MOV	%R9,0x38(%RSP)

(200) 0x42d5d3 VMOVQ	0x10(%R8),%XMM11

(200) 0x42d5d9 MOV	0x10(%RAX),%R10

(200) 0x42d5dd VMOVQ	0x10(%R14),%XMM3

(200) 0x42d5e3 IMUL	%RSI,%R11

(200) 0x42d5e7 IMUL	%RSI,%RCX

(200) 0x42d5eb IMUL	%RSI,%R15

(200) 0x42d5ef IMUL	(%R14),%RSI

(200) 0x42d5f3 MOV	%R11,0x68(%RSP)

(200) 0x42d5f8 IMUL	%R12,%R9

(200) 0x42d5fc MOV	%RCX,0x50(%RSP)

(200) 0x42d601 MOV	%R15,0x58(%RSP)

(200) 0x42d606 MOV	%R9,%R13

(200) 0x42d609 MOV	%R9,0x40(%RSP)

(200) 0x42d60e SUB	%R12,%R13

(200) 0x42d611 MOV	%RSI,0x78(%RSP)

(200) 0x42d616 LEA	-0x1(%RDX),%ESI

(200) 0x42d619 MOV	%R13,0x48(%RSP)

(200) 0x42d61e CMP	$0x6,%ESI

(200) 0x42d621 JBE	42dbf0

(200) 0x42d627 MOVSXD	0x70(%RSP),%RAX

(200) 0x42d62c VMOVQ	%XMM19,%R8

(200) 0x42d632 LEA	0x1(%RCX,%RAX,1),%RCX

(200) 0x42d637 LEA	(%R11,%RAX,1),%R11

(200) 0x42d63b LEA	(%R9,%RAX,1),%R9

(200) 0x42d63f LEA	(%R15,%RAX,1),%R14

(200) 0x42d643 SAL	$0x3,%RCX

(200) 0x42d647 VMOVQ	%XMM11,%R15

(200) 0x42d64c LEA	(%R8,%R11,8),%R8

(200) 0x42d650 LEA	-0x8(%R10,%RCX,1),%RSI

(200) 0x42d655 LEA	(%RBX,%R9,8),%R11

(200) 0x42d659 LEA	(%R10,%RCX,1),%R9

(200) 0x42d65d MOV	0x78(%RSP),%RCX

(200) 0x42d662 LEA	(%R15,%R14,8),%R12

(200) 0x42d666 MOV	%EDX,%R15D

(200) 0x42d669 LEA	(%R13,%RAX,1),%R13

(200) 0x42d66e VMOVQ	%XMM3,%R14

(200) 0x42d673 LEA	(%RBX,%R13,8),%R13

(200) 0x42d677 SHR	$0x3,%R15D

(200) 0x42d67b SAL	$0x6,%R15

(200) 0x42d67f ADD	%RCX,%RAX

(200) 0x42d682 LEA	(%R14,%RAX,8),%RCX

(200) 0x42d686 LEA	-0x40(%R15),%R14

(200) 0x42d68a XOR	%EAX,%EAX

(200) 0x42d68c SHR	$0x6,%R14

(200) 0x42d690 INC	%R14

(200) 0x42d693 AND	$0x3,%R14D

(200) 0x42d697 JE	42d7a2

(200) 0x42d69d CMP	$0x1,%R14

(200) 0x42d6a1 JE	42d748

(200) 0x42d6a7 CMP	$0x2,%R14

(200) 0x42d6ab JE	42d6f7

(200) 0x42d6ad VMOVUPD	(%R8),%ZMM17

(200) 0x42d6b3 VADDPD	(%R11),%ZMM17,%ZMM18

(200) 0x42d6b9 VMOVUPD	(%R13),%ZMM21

(200) 0x42d6c0 MOV	$0x40,%EAX

(200) 0x42d6c5 VADDPD	(%R9),%ZMM18,%ZMM20

(200) 0x42d6cb VADDPD	(%RSI),%ZMM21,%ZMM22

(200) 0x42d6d1 VSUBPD	%ZMM22,%ZMM20,%ZMM23

(200) 0x42d6d7 VMOVUPD	%ZMM23,(%R12)

(200) 0x42d6de VMOVUPD	(%R13),%ZMM24

(200) 0x42d6e5 VSUBPD	(%R11),%ZMM24,%ZMM25

(200) 0x42d6eb VADDPD	%ZMM23,%ZMM25,%ZMM26

(200) 0x42d6f1 VMOVUPD	%ZMM26,(%RCX)

(200) 0x42d6f7 VMOVUPD	(%R8,%RAX,1),%ZMM27

(200) 0x42d6fe VADDPD	(%R11,%RAX,1),%ZMM27,%ZMM28

(200) 0x42d705 VMOVUPD	(%R13,%RAX,1),%ZMM30

(200) 0x42d70d VADDPD	(%R9,%RAX,1),%ZMM28,%ZMM29

(200) 0x42d714 VADDPD	(%RSI,%RAX,1),%ZMM30,%ZMM31

(200) 0x42d71b VSUBPD	%ZMM31,%ZMM29,%ZMM17

(200) 0x42d721 VMOVUPD	%ZMM17,(%R12,%RAX,1)

(200) 0x42d728 VMOVUPD	(%R13,%RAX,1),%ZMM18

(200) 0x42d730 VSUBPD	(%R11,%RAX,1),%ZMM18,%ZMM20

(200) 0x42d737 VADDPD	%ZMM17,%ZMM20,%ZMM21

(200) 0x42d73d VMOVUPD	%ZMM21,(%RCX,%RAX,1)

(200) 0x42d744 ADD	$0x40,%RAX

(200) 0x42d748 VMOVUPD	(%R8,%RAX,1),%ZMM22

(200) 0x42d74f VADDPD	(%R11,%RAX,1),%ZMM22,%ZMM23

(200) 0x42d756 VMOVUPD	(%R13,%RAX,1),%ZMM25

(200) 0x42d75e VADDPD	(%R9,%RAX,1),%ZMM23,%ZMM24

(200) 0x42d765 VADDPD	(%RSI,%RAX,1),%ZMM25,%ZMM26

(200) 0x42d76c VSUBPD	%ZMM26,%ZMM24,%ZMM27

(200) 0x42d772 VMOVUPD	%ZMM27,(%R12,%RAX,1)

(200) 0x42d779 VMOVUPD	(%R13,%RAX,1),%ZMM28

(200) 0x42d781 VSUBPD	(%R11,%RAX,1),%ZMM28,%ZMM29

(200) 0x42d788 VADDPD	%ZMM27,%ZMM29,%ZMM30

(200) 0x42d78e VMOVUPD	%ZMM30,(%RCX,%RAX,1)

(200) 0x42d795 ADD	$0x40,%RAX

(200) 0x42d799 CMP	%R15,%RAX

(200) 0x42d79c JE	42d8fa

  (201) 0x42d7a2 VMOVUPD	(%R8,%RAX,1),%ZMM31

  (201) 0x42d7a9 VADDPD	(%R11,%RAX,1),%ZMM31,%ZMM17

  (201) 0x42d7b0 VMOVUPD	(%R13,%RAX,1),%ZMM18

  (201) 0x42d7b8 VADDPD	(%R9,%RAX,1),%ZMM17,%ZMM20

  (201) 0x42d7bf VADDPD	(%RSI,%RAX,1),%ZMM18,%ZMM21

  (201) 0x42d7c6 VSUBPD	%ZMM21,%ZMM20,%ZMM22

  (201) 0x42d7cc VMOVUPD	%ZMM22,(%R12,%RAX,1)

  (201) 0x42d7d3 VMOVUPD	(%R13,%RAX,1),%ZMM23

  (201) 0x42d7db VSUBPD	(%R11,%RAX,1),%ZMM23,%ZMM24

  (201) 0x42d7e2 VADDPD	%ZMM22,%ZMM24,%ZMM25

  (201) 0x42d7e8 VMOVUPD	%ZMM25,(%RCX,%RAX,1)

  (201) 0x42d7ef VMOVUPD	0x40(%R8,%RAX,1),%ZMM2

  (201) 0x42d7f7 VADDPD	0x40(%R11,%RAX,1),%ZMM2,%ZMM0

  (201) 0x42d7ff VMOVUPD	0x40(%R13,%RAX,1),%ZMM26

  (201) 0x42d807 VADDPD	0x40(%R9,%RAX,1),%ZMM0,%ZMM1

  (201) 0x42d80f VADDPD	0x40(%RSI,%RAX,1),%ZMM26,%ZMM27

  (201) 0x42d817 VSUBPD	%ZMM27,%ZMM1,%ZMM4

  (201) 0x42d81d VMOVUPD	%ZMM4,0x40(%R12,%RAX,1)

  (201) 0x42d825 VMOVUPD	0x40(%R13,%RAX,1),%ZMM28

  (201) 0x42d82d VSUBPD	0x40(%R11,%RAX,1),%ZMM28,%ZMM29

  (201) 0x42d835 VADDPD	%ZMM4,%ZMM29,%ZMM30

  (201) 0x42d83b VMOVUPD	%ZMM30,0x40(%RCX,%RAX,1)

  (201) 0x42d843 VMOVUPD	0x80(%R8,%RAX,1),%ZMM5

  (201) 0x42d84b VADDPD	0x80(%R11,%RAX,1),%ZMM5,%ZMM6

  (201) 0x42d853 VMOVUPD	0x80(%R13,%RAX,1),%ZMM31

  (201) 0x42d85b VADDPD	0x80(%R9,%RAX,1),%ZMM6,%ZMM7

  (201) 0x42d863 VADDPD	0x80(%RSI,%RAX,1),%ZMM31,%ZMM17

  (201) 0x42d86b VSUBPD	%ZMM17,%ZMM7,%ZMM8

  (201) 0x42d871 VMOVUPD	%ZMM8,0x80(%R12,%RAX,1)

  (201) 0x42d879 VMOVUPD	0x80(%R13,%RAX,1),%ZMM20

  (201) 0x42d881 VSUBPD	0x80(%R11,%RAX,1),%ZMM20,%ZMM18

  (201) 0x42d889 VADDPD	%ZMM8,%ZMM18,%ZMM21

  (201) 0x42d88f VMOVUPD	%ZMM21,0x80(%RCX,%RAX,1)

  (201) 0x42d897 VMOVUPD	0xc0(%R8,%RAX,1),%ZMM9

  (201) 0x42d89f VADDPD	0xc0(%R11,%RAX,1),%ZMM9,%ZMM10

  (201) 0x42d8a7 VMOVUPD	0xc0(%R13,%RAX,1),%ZMM22

  (201) 0x42d8af VADDPD	0xc0(%R9,%RAX,1),%ZMM10,%ZMM2

  (201) 0x42d8b7 VADDPD	0xc0(%RSI,%RAX,1),%ZMM22,%ZMM23

  (201) 0x42d8bf VSUBPD	%ZMM23,%ZMM2,%ZMM0

  (201) 0x42d8c5 VMOVUPD	%ZMM0,0xc0(%R12,%RAX,1)

  (201) 0x42d8cd VMOVUPD	0xc0(%R13,%RAX,1),%ZMM24

  (201) 0x42d8d5 VSUBPD	0xc0(%R11,%RAX,1),%ZMM24,%ZMM25

  (201) 0x42d8dd VADDPD	%ZMM0,%ZMM25,%ZMM26

  (201) 0x42d8e3 VMOVUPD	%ZMM26,0xc0(%RCX,%RAX,1)

  (201) 0x42d8eb ADD	$0x100,%RAX

  (201) 0x42d8f1 CMP	%R15,%RAX

  (201) 0x42d8f4 JNE	42d7a2

(200) 0x42d8fa MOV	0x70(%RSP),%R8D

(200) 0x42d8ff MOV	%EDX,%R12D

(200) 0x42d902 AND	$-0x8,%R12D

(200) 0x42d906 ADD	%R12D,%EDI

(200) 0x42d909 LEA	(%R12,%R8,1),%R14D

(200) 0x42d90d TEST	$0x7,%DL

(200) 0x42d910 JE	42db90

(200) 0x42d916 SUB	%R12D,%EDX

(200) 0x42d919 LEA	-0x1(%RDX),%R11D

(200) 0x42d91d CMP	$0x2,%R11D

(200) 0x42d921 JBE	42d9dd

(200) 0x42d927 MOVSXD	0x70(%RSP),%R13

(200) 0x42d92c MOV	0x48(%RSP),%R15

(200) 0x42d931 MOV	0x40(%RSP),%R9

(200) 0x42d936 MOV	0x50(%RSP),%R11

(200) 0x42d93b LEA	(%R15,%R13,1),%RAX

(200) 0x42d93f MOV	0x68(%RSP),%R15

(200) 0x42d944 LEA	(%R9,%R13,1),%RSI

(200) 0x42d948 LEA	(%R11,%R13,1),%R9

(200) 0x42d94c ADD	%R12,%RAX

(200) 0x42d94f ADD	%R12,%RSI

(200) 0x42d952 VMOVQ	%XMM19,%R11

(200) 0x42d958 LEA	(%RBX,%RAX,8),%R8

(200) 0x42d95c LEA	(%RBX,%RSI,8),%RCX

(200) 0x42d960 LEA	0x1(%R12,%R9,1),%RSI

(200) 0x42d965 MOV	0x58(%RSP),%R9

(200) 0x42d96a VMOVUPD	(%RCX),%YMM1

(200) 0x42d96e VMOVUPD	(%R10,%RSI,8),%YMM6

(200) 0x42d974 VSUBPD	(%R8),%YMM6,%YMM7

(200) 0x42d979 LEA	(%R15,%R13,1),%RAX

(200) 0x42d97d VMOVQ	%XMM11,%R15

(200) 0x42d982 ADD	%R12,%RAX

(200) 0x42d985 VADDPD	(%R11,%RAX,8),%YMM1,%YMM4

(200) 0x42d98b VSUBPD	-0x8(%R10,%RSI,8),%YMM4,%YMM5

(200) 0x42d992 LEA	(%R9,%R13,1),%RSI

(200) 0x42d996 ADD	%R12,%RSI

(200) 0x42d999 VADDPD	%YMM7,%YMM5,%YMM8

(200) 0x42d99d VMOVUPD	%YMM8,(%R15,%RSI,8)

(200) 0x42d9a3 VMOVUPD	(%R8),%YMM9

(200) 0x42d9a8 VSUBPD	(%RCX),%YMM9,%YMM10

(200) 0x42d9ac MOV	0x78(%RSP),%RCX

(200) 0x42d9b1 ADD	%RCX,%R13

(200) 0x42d9b4 ADD	%R12,%R13

(200) 0x42d9b7 VMOVQ	%XMM3,%R12

(200) 0x42d9bc VADDPD	%YMM8,%YMM10,%YMM2

(200) 0x42d9c1 VMOVUPD	%YMM2,(%R12,%R13,8)

(200) 0x42d9c7 MOV	%EDX,%R13D

(200) 0x42d9ca AND	$-0x4,%R13D

(200) 0x42d9ce ADD	%R13D,%R14D

(200) 0x42d9d1 ADD	%R13D,%EDI

(200) 0x42d9d4 AND	$0x3,%EDX

(200) 0x42d9d7 JE	42db90

(200) 0x42d9dd MOV	0x40(%RSP),%R11

(200) 0x42d9e2 MOVSXD	%R14D,%RAX

(200) 0x42d9e5 MOV	0x50(%RSP),%R12

(200) 0x42d9ea MOV	0x48(%RSP),%R13

(200) 0x42d9ef LEA	0x1(%R14),%R9D

(200) 0x42d9f3 LEA	(%R11,%RAX,1),%RDX

(200) 0x42d9f7 LEA	(%R13,%RAX,1),%R8

(200) 0x42d9fc LEA	(%RBX,%RDX,8),%RCX

(200) 0x42da00 MOVSXD	%R9D,%RDX

(200) 0x42da03 MOV	0x68(%RSP),%R9

(200) 0x42da08 LEA	(%RBX,%R8,8),%R15

(200) 0x42da0c LEA	(%R12,%RDX,1),%RSI

(200) 0x42da10 LEA	(%R10,%RSI,8),%R8

(200) 0x42da14 VMOVQ	%R8,%XMM4

(200) 0x42da19 VMOVQ	%XMM19,%R8

(200) 0x42da1f LEA	(%R9,%RAX,1),%RSI

(200) 0x42da23 VMOVSD	(%R8,%RSI,8),%XMM0

(200) 0x42da29 LEA	(%R12,%RAX,1),%RSI

(200) 0x42da2d VADDSD	(%RCX),%XMM0,%XMM1

(200) 0x42da31 VMOVQ	%XMM4,%R8

(200) 0x42da36 VSUBSD	(%R10,%RSI,8),%XMM1,%XMM5

(200) 0x42da3c MOV	0x58(%RSP),%RSI

(200) 0x42da41 VMOVSD	(%R8),%XMM6

(200) 0x42da46 VMOVQ	%XMM11,%R8

(200) 0x42da4b VSUBSD	(%R15),%XMM6,%XMM7

(200) 0x42da50 VADDSD	%XMM7,%XMM5,%XMM8

(200) 0x42da54 ADD	%RAX,%RSI

(200) 0x42da57 VMOVSD	%XMM8,(%R8,%RSI,8)

(200) 0x42da5d MOV	0x78(%RSP),%RSI

(200) 0x42da62 VMOVSD	(%R15),%XMM9

(200) 0x42da67 MOV	0x64(%RSP),%R15D

(200) 0x42da6c VSUBSD	(%RCX),%XMM9,%XMM10

(200) 0x42da70 VMOVQ	%XMM3,%RCX

(200) 0x42da75 VADDSD	%XMM8,%XMM10,%XMM2

(200) 0x42da7a ADD	%RSI,%RAX

(200) 0x42da7d VMOVSD	%XMM2,(%RCX,%RAX,8)

(200) 0x42da82 LEA	0x1(%RDI),%EAX

(200) 0x42da85 CMP	%R15D,%EAX

(200) 0x42da88 JAE	42db90

(200) 0x42da8e LEA	0x2(%R14),%EAX

(200) 0x42da92 LEA	(%RDX,%R11,1),%R8

(200) 0x42da96 ADD	%RDX,%R9

(200) 0x42da99 LEA	(%RDX,%R13,1),%RSI

(200) 0x42da9d CLTQ

(200) 0x42da9f LEA	(%RBX,%R8,8),%RCX

(200) 0x42daa3 LEA	(%RBX,%RSI,8),%R15

(200) 0x42daa7 ADD	$0x2,%EDI

(200) 0x42daaa LEA	(%R12,%RAX,1),%R8

(200) 0x42daae MOV	%RAX,0x70(%RSP)

(200) 0x42dab3 VMOVQ	%XMM19,%RAX

(200) 0x42dab9 VMOVSD	(%RAX,%R9,8),%XMM0

(200) 0x42dabf VMOVQ	%XMM4,%R9

(200) 0x42dac4 LEA	(%R10,%R8,8),%RSI

(200) 0x42dac8 VMOVQ	%XMM11,%RAX

(200) 0x42dacd VMOVSD	(%R9),%XMM4

(200) 0x42dad2 MOV	0x58(%RSP),%R9

(200) 0x42dad7 VADDSD	(%RCX),%XMM0,%XMM1

(200) 0x42dadb VADDSD	(%R15),%XMM4,%XMM6

(200) 0x42dae0 VADDSD	(%RSI),%XMM1,%XMM5

(200) 0x42dae4 VSUBSD	%XMM6,%XMM5,%XMM7

(200) 0x42dae8 MOV	%R9,%R8

(200) 0x42daeb ADD	%RDX,%R8

(200) 0x42daee VMOVSD	%XMM7,(%RAX,%R8,8)

(200) 0x42daf4 MOV	0x78(%RSP),%R8

(200) 0x42daf9 VMOVSD	(%R15),%XMM8

(200) 0x42dafe VSUBSD	(%RCX),%XMM8,%XMM9

(200) 0x42db02 VMOVQ	%XMM3,%RCX

(200) 0x42db07 VADDSD	%XMM7,%XMM9,%XMM10

(200) 0x42db0b ADD	%R8,%RDX

(200) 0x42db0e VMOVSD	%XMM10,(%RCX,%RDX,8)

(200) 0x42db13 MOV	0x64(%RSP),%EDX

(200) 0x42db17 CMP	%EDX,%EDI

(200) 0x42db19 JAE	42db90

(200) 0x42db1b MOV	0x70(%RSP),%RDI

(200) 0x42db20 VMOVQ	%XMM19,%RAX

(200) 0x42db26 ADD	$0x3,%R14D

(200) 0x42db2a MOVSXD	%R14D,%R14

(200) 0x42db2d ADD	%R12,%R14

(200) 0x42db30 VMOVQ	%XMM3,%R12

(200) 0x42db35 ADD	%RDI,%R11

(200) 0x42db38 ADD	%RDI,%R13

(200) 0x42db3b ADD	%RDI,%R9

(200) 0x42db3e LEA	(%RBX,%R11,8),%R15

(200) 0x42db42 LEA	(%RBX,%R13,8),%RCX

(200) 0x42db46 MOV	0x68(%RSP),%RBX

(200) 0x42db4b VMOVSD	(%RCX),%XMM1

(200) 0x42db4f VADDSD	(%RSI),%XMM1,%XMM4

(200) 0x42db53 ADD	%RDI,%RBX

(200) 0x42db56 VMOVSD	(%RAX,%RBX,8),%XMM2

(200) 0x42db5b MOV	0x78(%RSP),%RAX

(200) 0x42db60 VADDSD	(%R15),%XMM2,%XMM0

(200) 0x42db65 VADDSD	(%R10,%R14,8),%XMM0,%XMM5

(200) 0x42db6b VMOVQ	%XMM11,%R10

(200) 0x42db70 VSUBSD	%XMM4,%XMM5,%XMM6

(200) 0x42db74 VMOVSD	%XMM6,(%R10,%R9,8)

(200) 0x42db7a VMOVSD	(%RCX),%XMM11

(200) 0x42db7e VSUBSD	(%R15),%XMM11,%XMM7

(200) 0x42db83 VADDSD	%XMM6,%XMM7,%XMM8

(200) 0x42db87 ADD	%RDI,%RAX

(200) 0x42db8a VMOVSD	%XMM8,(%R12,%RAX,8)

(200) 0x42db90 MOV	0x64(%RSP),%EDI

(200) 0x42db94 MOV	0x38(%RSP),%RSI

(200) 0x42db99 CMP	%ESI,0x34(%RSP)

(200) 0x42db9d JLE	42dbc0

(200) 0x42db9f MOV	0x2c(%RSP),%R8D

(200) 0x42dba4 MOV	0x30(%RSP),%R11D

(200) 0x42dba9 MOV	0x60(%RSP),%EDX

(200) 0x42dbad SUB	%EDI,%R8D

(200) 0x42dbb0 MOV	%R11D,0x70(%RSP)

(200) 0x42dbb5 JMP	42d580

0x42dbba NOPW	(%RAX,%RAX,1)

0x42dbc0 VZEROUPPER

0x42dbc3 LEA	-0x28(%RBP),%RSP

0x42dbc7 POP	%RBX

0x42dbc8 POP	%R12

0x42dbca POP	%R13

0x42dbcc POP	%R14

0x42dbce POP	%R15

0x42dbd0 POP	%RBP

0x42dbd1 RET

0x42dbd2 NOPW	%CS:(%RAX,%RAX,1)

0x42dbdd NOPL	(%RAX)

(200) 0x42dbe0 LEA	0x1(%RSI),%R14

(200) 0x42dbe4 MOV	%R14,0x38(%RSP)

(200) 0x42dbe9 JMP	42db94

0x42dbeb NOPL	(%RAX,%RAX,1)

(200) 0x42dbf0 MOV	0x70(%RSP),%R14D

(200) 0x42dbf5 XOR	%R12D,%R12D

(200) 0x42dbf8 JMP	42d916

0x42dbfd INC	%R8D

0x42dc00 XOR	%EDX,%EDX

0x42dc02 JMP	42d523

0x42dc07 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.89+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.20+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:136	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.63 cycles (1.25x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.38 cycles (1.28x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:139

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	79
nb uops	77
loop length	286
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.63
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42d4a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%R13),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RBX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42dbc3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x723>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(%RCX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R15D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42dbc3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x723>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42dbfd <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x75d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R8D,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R9,%RDX,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R8,%RDI,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R10D,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R10D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42dbc3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x723>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x30(%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%R13),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x60(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x10(%R13),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x8(%R13),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R13),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R13),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA (%RAX,%R14,1),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %R13D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R11D,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42d523 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.38 cycles (1.28x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:138
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:139

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	79
nb uops	77
loop length	286
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.63
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42d4a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%R13),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RBX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EDI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42dbc3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x723>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(%RCX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R15D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42dbc3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x723>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42dbfd <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x75d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R8D,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R9,%RDX,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R8,%RDI,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R10D,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R10D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42dbc3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x723>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x30(%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%R13),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x60(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x10(%R13),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x8(%R13),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R13),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R13),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA (%RAX,%R14,1),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %R13D,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R11D,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42d523 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.4+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.53	0.56
▼Loop 200 - advec_cell.cpp:136-140 - exec–	0.00	0.01
○Loop 201 - advec_cell.cpp:139-140 - exec	1.52	0.56

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code