OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:117-125 [...]	Coverage (incl. loops): 3.56% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 117 - 125

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd collapse(2)

118:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42cdb0 PUSH	%RBP

0x42cdb1 MOV	%RSP,%RBP

0x42cdb4 PUSH	%R15

0x42cdb6 PUSH	%R14

0x42cdb8 PUSH	%R13

0x42cdba PUSH	%R12

0x42cdbc PUSH	%RBX

0x42cdbd AND	$-0x40,%RSP

0x42cdc1 ADD	$-0x80,%RSP

0x42cdc5 MOV	0x38(%RDI),%EAX

0x42cdc8 MOV	0x3c(%RDI),%ECX

0x42cdcb MOV	0x30(%RDI),%ESI

0x42cdce MOV	0x34(%RDI),%EDX

0x42cdd1 ADD	$0x2,%ECX

0x42cdd4 INC	%ESI

0x42cdd6 LEA	0x1(%RAX),%R14D

0x42cdda MOV	%ECX,0x38(%RSP)

0x42cdde MOV	%ESI,0x34(%RSP)

0x42cde2 CMP	%ECX,%R14D

0x42cde5 JGE	42d463

0x42cdeb MOV	%ECX,%EBX

0x42cded LEA	0x2(%RDX),%R15D

0x42cdf1 SUB	%R14D,%EBX

0x42cdf4 CMP	%R15D,%ESI

0x42cdf7 JGE	42d463

0x42cdfd MOV	%RDI,%R13

0x42ce00 MOV	%R15D,%EDI

0x42ce03 SUB	%ESI,%EDI

0x42ce05 MOV	%EDI,0x3c(%RSP)

0x42ce09 CALL	404630 <omp_get_num_threads@plt>

0x42ce0e MOV	%EAX,%R12D

0x42ce11 CALL	404520 <omp_get_thread_num@plt>

0x42ce16 XOR	%EDX,%EDX

0x42ce18 MOV	%EAX,%R8D

0x42ce1b MOV	0x3c(%RSP),%EAX

0x42ce1f IMUL	%EBX,%EAX

0x42ce22 DIV	%R12D

0x42ce25 MOV	%EAX,%R9D

0x42ce28 CMP	%EDX,%R8D

0x42ce2b JB	42d48c

0x42ce31 IMUL	%R9D,%R8D

0x42ce35 LEA	(%R8,%RDX,1),%R11D

0x42ce39 LEA	(%R9,%R11,1),%R10D

0x42ce3d MOV	%R10D,0x30(%RSP)

0x42ce42 CMP	%R10D,%R11D

0x42ce45 JAE	42d463

0x42ce4b MOV	%R11D,%EAX

0x42ce4e XOR	%EDX,%EDX

0x42ce50 MOV	0x34(%RSP),%ECX

0x42ce54 MOV	%R15D,%ESI

0x42ce57 DIVL	0x3c(%RSP)

0x42ce5b VMOVQ	(%R13),%XMM19

0x42ce62 VMOVQ	0x20(%R13),%XMM18

0x42ce69 VMOVQ	0x10(%R13),%XMM17

0x42ce70 VMOVQ	0x8(%R13),%XMM16

0x42ce77 VMOVQ	0x28(%R13),%XMM15

0x42ce7d VMOVQ	0x18(%R13),%XMM14

0x42ce83 ADD	%ECX,%EDX

0x42ce85 ADD	%R14D,%EAX

0x42ce88 MOVSXD	%EAX,%R13

0x42ce8b SUB	%EDX,%ESI

0x42ce8d MOV	%R9D,%EAX

0x42ce90 MOV	%EDX,0x74(%RSP)

0x42ce94 NOPW	%CS:(%RAX,%RAX,1)

0x42ce9f NOP

(198) 0x42cea0 CMP	%ESI,%EAX

(198) 0x42cea2 CMOVA	%ESI,%EAX

(198) 0x42cea5 LEA	(%R11,%RAX,1),%R14D

(198) 0x42cea9 MOV	%R14D,0x70(%RSP)

(198) 0x42ceae CMP	%R14D,%R11D

(198) 0x42ceb1 JAE	42d436

(198) 0x42ceb7 VMOVQ	%XMM18,%RDI

(198) 0x42cebd VMOVQ	%XMM17,%R8

(198) 0x42cec3 VMOVQ	%XMM19,%RSI

(198) 0x42cec9 VMOVQ	%XMM16,%R9

(198) 0x42cecf MOV	(%RDI),%R12

(198) 0x42ced2 MOV	(%R8),%R10

(198) 0x42ced5 VMOVQ	%XMM15,%RCX

(198) 0x42ceda VMOVQ	%XMM14,%R14

(198) 0x42cedf VMOVQ	0x10(%RDI),%XMM13

(198) 0x42cee4 MOV	(%RSI),%RBX

(198) 0x42cee7 MOV	(%R9),%RDX

(198) 0x42ceea MOV	(%RCX),%RDI

(198) 0x42ceed MOV	(%R14),%R15

(198) 0x42cef0 VMOVQ	0x10(%R8),%XMM8

(198) 0x42cef6 LEA	-0x1(%RAX),%R8D

(198) 0x42cefa VMOVQ	0x10(%RSI),%XMM23

(198) 0x42cf01 VMOVQ	0x10(%R9),%XMM12

(198) 0x42cf07 VMOVQ	0x10(%RCX),%XMM7

(198) 0x42cf0c VMOVQ	0x10(%R14),%XMM6

(198) 0x42cf12 IMUL	%R13,%R12

(198) 0x42cf16 IMUL	%R13,%RBX

(198) 0x42cf1a IMUL	%R13,%R10

(198) 0x42cf1e IMUL	%R13,%RDX

(198) 0x42cf22 MOV	%R12,0x60(%RSP)

(198) 0x42cf27 IMUL	%R13,%RDI

(198) 0x42cf2b MOV	%RBX,0x58(%RSP)

(198) 0x42cf30 IMUL	%R13,%R15

(198) 0x42cf34 MOV	%R10,0x48(%RSP)

(198) 0x42cf39 MOV	%RDX,0x68(%RSP)

(198) 0x42cf3e MOV	%RDI,0x50(%RSP)

(198) 0x42cf43 MOV	%R15,0x78(%RSP)

(198) 0x42cf48 CMP	$0x6,%R8D

(198) 0x42cf4c JBE	42d480

(198) 0x42cf52 MOVSXD	0x74(%RSP),%RCX

(198) 0x42cf57 VMOVQ	%XMM13,%R8

(198) 0x42cf5c LEA	(%R10,%RCX,1),%RSI

(198) 0x42cf60 LEA	(%RBX,%RCX,1),%R9

(198) 0x42cf64 VMOVQ	%XMM23,%RBX

(198) 0x42cf6a LEA	(%RDI,%RCX,1),%RDI

(198) 0x42cf6e SAL	$0x3,%RSI

(198) 0x42cf72 LEA	(%RBX,%R9,8),%R15

(198) 0x42cf76 VMOVQ	%XMM8,%R9

(198) 0x42cf7b LEA	(%R12,%RCX,1),%R14

(198) 0x42cf7f LEA	(%R9,%RSI,1),%R10

(198) 0x42cf83 LEA	0x8(%R9,%RSI,1),%RBX

(198) 0x42cf88 MOV	0x78(%RSP),%RSI

(198) 0x42cf8d LEA	(%R8,%R14,8),%R12

(198) 0x42cf91 VMOVQ	%XMM7,%R8

(198) 0x42cf96 LEA	(%RDX,%RCX,1),%R14

(198) 0x42cf9a VMOVQ	%XMM12,%RDX

(198) 0x42cf9f SAL	$0x3,%RDI

(198) 0x42cfa3 LEA	(%R8,%RDI,1),%R9

(198) 0x42cfa7 LEA	0x8(%R8,%RDI,1),%R8

(198) 0x42cfac MOV	%EAX,%EDI

(198) 0x42cfae LEA	(%RDX,%R14,8),%R14

(198) 0x42cfb2 ADD	%RSI,%RCX

(198) 0x42cfb5 VMOVQ	%XMM6,%RDX

(198) 0x42cfba SAL	$0x3,%RCX

(198) 0x42cfbe SHR	$0x3,%EDI

(198) 0x42cfc1 LEA	(%RDX,%RCX,1),%RSI

(198) 0x42cfc5 LEA	0x8(%RDX,%RCX,1),%RDX

(198) 0x42cfca MOV	%RDI,%RCX

(198) 0x42cfcd SAL	$0x6,%RCX

(198) 0x42cfd1 MOV	%RCX,0x40(%RSP)

(198) 0x42cfd6 XOR	%ECX,%ECX

(198) 0x42cfd8 AND	$0x1,%EDI

(198) 0x42cfdb JE	42d03f

(198) 0x42cfdd VMOVUPD	(%R12),%ZMM1

(198) 0x42cfe4 VMULPD	(%R15),%ZMM1,%ZMM20

(198) 0x42cfea VADDPD	(%RSI),%ZMM1,%ZMM0

(198) 0x42cff0 VMOVUPD	(%R9),%ZMM22

(198) 0x42cff6 VSUBPD	(%RDX),%ZMM0,%ZMM2

(198) 0x42cffc VSUBPD	(%R8),%ZMM22,%ZMM25

(198) 0x42d002 MOV	0x40(%RSP),%RDI

(198) 0x42d007 MOV	$0x40,%ECX

(198) 0x42d00c VSUBPD	(%RBX),%ZMM20,%ZMM21

(198) 0x42d012 VFMADD132PD	(%R14),%ZMM25,%ZMM20

(198) 0x42d018 VADDPD	(%R10),%ZMM21,%ZMM24

(198) 0x42d01e VDIVPD	%ZMM2,%ZMM24,%ZMM3

(198) 0x42d024 VDIVPD	%ZMM24,%ZMM20,%ZMM26

(198) 0x42d02a VMOVUPD	%ZMM3,(%R15)

(198) 0x42d030 VMOVUPD	%ZMM26,(%R14)

(198) 0x42d036 CMP	%RDI,%RCX

(198) 0x42d039 JE	42d11e

(198) 0x42d03f MOV	%R13,0x28(%RSP)

(198) 0x42d044 MOV	%EAX,%R13D

(198) 0x42d047 MOV	0x40(%RSP),%RAX

  (199) 0x42d04c VMOVUPD	(%R12,%RCX,1),%ZMM4

  (199) 0x42d053 VMULPD	(%R15,%RCX,1),%ZMM4,%ZMM5

  (199) 0x42d05a VADDPD	(%RSI,%RCX,1),%ZMM4,%ZMM9

  (199) 0x42d061 VMOVUPD	(%R9,%RCX,1),%ZMM29

  (199) 0x42d068 VSUBPD	(%RDX,%RCX,1),%ZMM9,%ZMM10

  (199) 0x42d06f VSUBPD	(%R8,%RCX,1),%ZMM29,%ZMM30

  (199) 0x42d076 VSUBPD	(%RBX,%RCX,1),%ZMM5,%ZMM27

  (199) 0x42d07d VFMADD132PD	(%R14,%RCX,1),%ZMM30,%ZMM5

  (199) 0x42d084 VADDPD	(%R10,%RCX,1),%ZMM27,%ZMM28

  (199) 0x42d08b VDIVPD	%ZMM28,%ZMM5,%ZMM1

  (199) 0x42d091 VDIVPD	%ZMM10,%ZMM28,%ZMM11

  (199) 0x42d097 VMOVUPD	%ZMM11,(%R15,%RCX,1)

  (199) 0x42d09e VMOVUPD	%ZMM1,(%R14,%RCX,1)

  (199) 0x42d0a5 VMOVUPD	0x40(%R12,%RCX,1),%ZMM0

  (199) 0x42d0ad VMULPD	0x40(%R15,%RCX,1),%ZMM0,%ZMM2

  (199) 0x42d0b5 VADDPD	0x40(%RSI,%RCX,1),%ZMM0,%ZMM3

  (199) 0x42d0bd VSUBPD	0x40(%RDX,%RCX,1),%ZMM3,%ZMM4

  (199) 0x42d0c5 VMOVUPD	0x40(%R9,%RCX,1),%ZMM21

  (199) 0x42d0cd VSUBPD	0x40(%R8,%RCX,1),%ZMM21,%ZMM24

  (199) 0x42d0d5 VSUBPD	0x40(%RBX,%RCX,1),%ZMM2,%ZMM31

  (199) 0x42d0dd VFMADD132PD	0x40(%R14,%RCX,1),%ZMM24,%ZMM2

  (199) 0x42d0e5 VADDPD	0x40(%R10,%RCX,1),%ZMM31,%ZMM20

  (199) 0x42d0ed VDIVPD	%ZMM4,%ZMM20,%ZMM5

  (199) 0x42d0f3 VDIVPD	%ZMM20,%ZMM2,%ZMM9

  (199) 0x42d0f9 VMOVUPD	%ZMM5,0x40(%R15,%RCX,1)

  (199) 0x42d101 VMOVUPD	%ZMM9,0x40(%R14,%RCX,1)

  (199) 0x42d109 SUB	$-0x80,%RCX

  (199) 0x42d10d CMP	%RAX,%RCX

  (199) 0x42d110 JNE	42d04c

(198) 0x42d116 MOV	%R13D,%EAX

(198) 0x42d119 MOV	0x28(%RSP),%R13

(198) 0x42d11e MOV	0x74(%RSP),%R15D

(198) 0x42d123 MOV	%EAX,%R12D

(198) 0x42d126 AND	$-0x8,%R12D

(198) 0x42d12a ADD	%R12D,%R11D

(198) 0x42d12d LEA	(%R12,%R15,1),%ESI

(198) 0x42d131 TEST	$0x7,%AL

(198) 0x42d133 JE	42d431

(198) 0x42d139 SUB	%R12D,%EAX

(198) 0x42d13c LEA	-0x1(%RAX),%R10D

(198) 0x42d140 CMP	$0x2,%R10D

(198) 0x42d144 JBE	42d21f

(198) 0x42d14a MOVSXD	0x74(%RSP),%RDX

(198) 0x42d14f MOV	0x58(%RSP),%RBX

(198) 0x42d154 MOV	0x68(%RSP),%RDI

(198) 0x42d159 VMOVQ	%XMM23,%R9

(198) 0x42d15f MOV	0x48(%RSP),%R8

(198) 0x42d164 LEA	(%RBX,%RDX,1),%R14

(198) 0x42d168 LEA	(%RDI,%RDX,1),%R10

(198) 0x42d16c VMOVQ	%XMM12,%RBX

(198) 0x42d171 MOV	0x78(%RSP),%RDI

(198) 0x42d176 ADD	%R12,%R14

(198) 0x42d179 ADD	%R12,%R10

(198) 0x42d17c LEA	(%R8,%RDX,1),%R15

(198) 0x42d180 LEA	(%R9,%R14,8),%RCX

(198) 0x42d184 LEA	(%RBX,%R10,8),%R9

(198) 0x42d188 MOV	0x50(%RSP),%R14

(198) 0x42d18d MOV	0x60(%RSP),%RBX

(198) 0x42d192 ADD	%R12,%R15

(198) 0x42d195 LEA	(%RDI,%RDX,1),%R10

(198) 0x42d199 ADD	%R12,%R10

(198) 0x42d19c LEA	(%R14,%RDX,1),%R8

(198) 0x42d1a0 ADD	%RBX,%RDX

(198) 0x42d1a3 VMOVQ	%XMM6,%R14

(198) 0x42d1a8 ADD	%R12,%RDX

(198) 0x42d1ab ADD	%R12,%R8

(198) 0x42d1ae VMOVQ	%XMM13,%R12

(198) 0x42d1b3 VMOVUPD	(%R12,%RDX,8),%YMM10

(198) 0x42d1b9 VMOVQ	%XMM8,%RDX

(198) 0x42d1be VMULPD	(%RCX),%YMM10,%YMM11

(198) 0x42d1c2 VADDPD	(%R14,%R10,8),%YMM10,%YMM4

(198) 0x42d1c8 VADDPD	(%RDX,%R15,8),%YMM11,%YMM1

(198) 0x42d1ce VSUBPD	0x8(%R14,%R10,8),%YMM4,%YMM5

(198) 0x42d1d5 SAL	$0x3,%R8

(198) 0x42d1d9 VSUBPD	0x8(%RDX,%R15,8),%YMM1,%YMM0

(198) 0x42d1e0 VMOVQ	%XMM7,%R15

(198) 0x42d1e5 VMOVUPD	(%R15,%R8,1),%YMM2

(198) 0x42d1eb VMOVUPD	0x8(%R15,%R8,1),%YMM3

(198) 0x42d1f2 VFMSUB132PD	(%R9),%YMM3,%YMM11

(198) 0x42d1f7 VADDPD	%YMM11,%YMM2,%YMM10

(198) 0x42d1fc VDIVPD	%YMM5,%YMM0,%YMM9

(198) 0x42d200 VDIVPD	%YMM0,%YMM10,%YMM11

(198) 0x42d204 VMOVUPD	%YMM9,(%RCX)

(198) 0x42d208 MOV	%EAX,%ECX

(198) 0x42d20a AND	$-0x4,%ECX

(198) 0x42d20d ADD	%ECX,%ESI

(198) 0x42d20f ADD	%ECX,%R11D

(198) 0x42d212 VMOVUPD	%YMM11,(%R9)

(198) 0x42d217 TEST	$0x3,%AL

(198) 0x42d219 JE	42d431

(198) 0x42d21f MOV	0x60(%RSP),%R10

(198) 0x42d224 MOVSXD	%ESI,%RDX

(198) 0x42d227 MOV	0x58(%RSP),%RAX

(198) 0x42d22c VMOVQ	%XMM13,%RBX

(198) 0x42d231 VMOVQ	%XMM8,%R15

(198) 0x42d236 VMOVQ	%XMM23,%R8

(198) 0x42d23c MOV	0x68(%RSP),%RCX

(198) 0x42d241 ADD	%RDX,%R10

(198) 0x42d244 LEA	(%RAX,%RDX,1),%R9

(198) 0x42d248 LEA	0x1(%RSI),%EAX

(198) 0x42d24b VMOVSD	(%RBX,%R10,8),%XMM0

(198) 0x42d251 MOV	0x48(%RSP),%RBX

(198) 0x42d256 CLTQ

(198) 0x42d258 LEA	(%R8,%R9,8),%RDI

(198) 0x42d25c VMULSD	(%RDI),%XMM0,%XMM1

(198) 0x42d260 VMOVQ	%XMM7,%R10

(198) 0x42d265 ADD	%RDX,%RCX

(198) 0x42d268 VMOVQ	%XMM12,%R8

(198) 0x42d26d LEA	(%R8,%RCX,8),%RCX

(198) 0x42d271 VMOVQ	%XMM6,%R8

(198) 0x42d276 LEA	(%RAX,%RBX,1),%R12

(198) 0x42d27a LEA	(%RBX,%RDX,1),%R14

(198) 0x42d27e LEA	(%R15,%R12,8),%R9

(198) 0x42d282 MOV	0x50(%RSP),%R12

(198) 0x42d287 VADDSD	(%R15,%R14,8),%XMM1,%XMM2

(198) 0x42d28d VSUBSD	(%R9),%XMM2,%XMM3

(198) 0x42d292 LEA	(%R12,%RDX,1),%R15

(198) 0x42d296 LEA	(%R12,%RAX,1),%R14

(198) 0x42d29a VMOVSD	(%R10,%R15,8),%XMM5

(198) 0x42d2a0 LEA	(%R10,%R14,8),%R15

(198) 0x42d2a4 MOV	0x78(%RSP),%R10

(198) 0x42d2a9 VMOVSD	(%R15),%XMM4

(198) 0x42d2ae VFMSUB132SD	(%RCX),%XMM4,%XMM1

(198) 0x42d2b3 LEA	(%R10,%RAX,1),%R14

(198) 0x42d2b7 ADD	%R10,%RDX

(198) 0x42d2ba LEA	(%R8,%R14,8),%R14

(198) 0x42d2be VADDSD	(%R8,%RDX,8),%XMM0,%XMM9

(198) 0x42d2c4 LEA	0x1(%R11),%EDX

(198) 0x42d2c8 VADDSD	%XMM5,%XMM1,%XMM0

(198) 0x42d2cc VSUBSD	(%R14),%XMM9,%XMM10

(198) 0x42d2d1 VDIVSD	%XMM10,%XMM3,%XMM11

(198) 0x42d2d6 VMOVSD	%XMM11,(%RDI)

(198) 0x42d2da MOV	0x70(%RSP),%EDI

(198) 0x42d2de VDIVSD	%XMM3,%XMM0,%XMM1

(198) 0x42d2e2 VMOVSD	%XMM1,(%RCX)

(198) 0x42d2e6 CMP	%EDI,%EDX

(198) 0x42d2e8 JAE	42d431

(198) 0x42d2ee MOV	0x58(%RSP),%RCX

(198) 0x42d2f3 MOV	0x60(%RSP),%RDX

(198) 0x42d2f8 VMOVQ	%XMM23,%R8

(198) 0x42d2fe VMOVQ	%XMM13,%RDI

(198) 0x42d303 VMOVSD	(%R15),%XMM9

(198) 0x42d308 MOV	0x78(%RSP),%R15

(198) 0x42d30d ADD	$0x2,%R11D

(198) 0x42d311 LEA	(%RAX,%RCX,1),%R10

(198) 0x42d315 ADD	%RAX,%RDX

(198) 0x42d318 LEA	(%R8,%R10,8),%RCX

(198) 0x42d31c LEA	0x2(%RSI),%R10D

(198) 0x42d320 VMOVSD	(%RDI,%RDX,8),%XMM5

(198) 0x42d325 VMOVQ	%XMM8,%R8

(198) 0x42d32a MOVSXD	%R10D,%RDX

(198) 0x42d32d VMULSD	(%RCX),%XMM5,%XMM2

(198) 0x42d331 VADDSD	(%R14),%XMM5,%XMM11

(198) 0x42d336 MOV	0x70(%RSP),%R14D

(198) 0x42d33b LEA	(%RBX,%RDX,1),%RDI

(198) 0x42d33f VMOVQ	%XMM12,%R10

(198) 0x42d344 LEA	(%R8,%RDI,8),%R8

(198) 0x42d348 LEA	(%R12,%RDX,1),%RDI

(198) 0x42d34c VSUBSD	(%R8),%XMM2,%XMM3

(198) 0x42d351 VADDSD	(%R9),%XMM3,%XMM4

(198) 0x42d356 MOV	0x68(%RSP),%R9

(198) 0x42d35b ADD	%R9,%RAX

(198) 0x42d35e VMOVQ	%XMM7,%R9

(198) 0x42d363 LEA	(%R10,%RAX,8),%RAX

(198) 0x42d367 LEA	(%R9,%RDI,8),%R10

(198) 0x42d36b LEA	(%R15,%RDX,1),%RDI

(198) 0x42d36f VMOVQ	%XMM6,%R9

(198) 0x42d374 LEA	(%R9,%RDI,8),%RDI

(198) 0x42d378 VSUBSD	(%R10),%XMM9,%XMM10

(198) 0x42d37d VFMADD132SD	(%RAX),%XMM10,%XMM2

(198) 0x42d382 VDIVSD	%XMM4,%XMM2,%XMM5

(198) 0x42d386 VSUBSD	(%RDI),%XMM11,%XMM0

(198) 0x42d38a VDIVSD	%XMM0,%XMM4,%XMM1

(198) 0x42d38e VMOVSD	%XMM1,(%RCX)

(198) 0x42d392 VMOVSD	%XMM5,(%RAX)

(198) 0x42d396 CMP	%R14D,%R11D

(198) 0x42d399 JAE	42d431

(198) 0x42d39f MOV	0x58(%RSP),%R11

(198) 0x42d3a4 MOV	0x60(%RSP),%RAX

(198) 0x42d3a9 ADD	$0x3,%ESI

(198) 0x42d3ac VMOVQ	%XMM23,%RCX

(198) 0x42d3b2 MOVSXD	%ESI,%RSI

(198) 0x42d3b5 VMOVQ	%XMM13,%R9

(198) 0x42d3ba ADD	%RSI,%RBX

(198) 0x42d3bd ADD	%RSI,%R12

(198) 0x42d3c0 ADD	%RSI,%R15

(198) 0x42d3c3 ADD	%RDX,%R11

(198) 0x42d3c6 ADD	%RDX,%RAX

(198) 0x42d3c9 LEA	(%RCX,%R11,8),%R14

(198) 0x42d3cd MOV	%RBX,%R11

(198) 0x42d3d0 VMOVQ	%XMM8,%RBX

(198) 0x42d3d5 VMOVSD	(%R9,%RAX,8),%XMM13

(198) 0x42d3db VMULSD	(%R14),%XMM13,%XMM2

(198) 0x42d3e0 VSUBSD	(%RBX,%R11,8),%XMM2,%XMM8

(198) 0x42d3e6 VADDSD	(%R8),%XMM8,%XMM3

(198) 0x42d3eb MOV	0x68(%RSP),%R8

(198) 0x42d3f0 VMOVQ	%XMM12,%RCX

(198) 0x42d3f5 VADDSD	(%RDI),%XMM13,%XMM4

(198) 0x42d3f9 VMOVSD	(%R10),%XMM12

(198) 0x42d3fe VMOVQ	%XMM6,%RDI

(198) 0x42d403 VMOVQ	%XMM7,%R10

(198) 0x42d408 VSUBSD	(%RDI,%R15,8),%XMM4,%XMM6

(198) 0x42d40e VDIVSD	%XMM6,%XMM3,%XMM9

(198) 0x42d412 VSUBSD	(%R10,%R12,8),%XMM12,%XMM7

(198) 0x42d418 ADD	%RDX,%R8

(198) 0x42d41b LEA	(%RCX,%R8,8),%RAX

(198) 0x42d41f VFMADD132SD	(%RAX),%XMM7,%XMM2

(198) 0x42d424 VMOVSD	%XMM9,(%R14)

(198) 0x42d429 VDIVSD	%XMM3,%XMM2,%XMM10

(198) 0x42d42d VMOVSD	%XMM10,(%RAX)

(198) 0x42d431 MOV	0x70(%RSP),%R11D

(198) 0x42d436 INC	%R13

(198) 0x42d439 CMP	%R13D,0x38(%RSP)

(198) 0x42d43e JLE	42d460

(198) 0x42d440 MOV	0x30(%RSP),%EAX

(198) 0x42d444 MOV	0x34(%RSP),%R14D

(198) 0x42d449 MOV	0x3c(%RSP),%ESI

(198) 0x42d44d SUB	%R11D,%EAX

(198) 0x42d450 MOV	%R14D,0x74(%RSP)

(198) 0x42d455 JMP	42cea0

0x42d45a NOPW	(%RAX,%RAX,1)

0x42d460 VZEROUPPER

0x42d463 LEA	-0x28(%RBP),%RSP

0x42d467 POP	%RBX

0x42d468 POP	%R12

0x42d46a POP	%R13

0x42d46c POP	%R14

0x42d46e POP	%R15

0x42d470 POP	%RBP

0x42d471 RET

0x42d472 NOPW	%CS:(%RAX,%RAX,1)

0x42d47d NOPL	(%RAX)

(198) 0x42d480 MOV	0x74(%RSP),%ESI

(198) 0x42d484 XOR	%R12D,%R12D

(198) 0x42d487 JMP	42d139

0x42d48c INC	%R9D

0x42d48f XOR	%EDX,%EDX

0x42d491 JMP	42ce31

0x42d496 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.82+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.14+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:220	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.10+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:220	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:81	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.75 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.63 cycles (1.25x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	81
nb uops	79
loop length	298
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.88 cycles
front end	9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.88
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42cdb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x3c(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x30(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x34(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x2,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ECX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ESI,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ECX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42d463 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x6b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42d463 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x6b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3c(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42d48c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x6dc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R9,%R11,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R10D,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42d463 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x6b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x34(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
DIVL 0x3c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ (%R13),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R13),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x8(%R13),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x28(%R13),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R13),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDX,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42ce31 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x81>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.75 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.63 cycles (1.25x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:119

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	81
nb uops	79
loop length	298
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.88 cycles
front end	9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	5.00	5.00	5.00	5.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.88
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42cdb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x38(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x3c(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x30(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x34(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x2,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ECX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ESI,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ECX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42d463 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x6b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42d463 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x6b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3c(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42d48c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x6dc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R9,%R11,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R10D,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42d463 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x6b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x34(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
DIVL 0x3c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ (%R13),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R13),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x8(%R13),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x28(%R13),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R13),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %ECX,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDX,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42ce31 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.3+0x81>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.56	1.31
▼Loop 198 - advec_cell.cpp:119-125 - exec–	0.00	0.01
○Loop 199 - advec_cell.cpp:120-125 - exec	3.56	1.30

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code