OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:54-58 [...]	Coverage (incl. loops): 1.28% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 54 - 58

--------------------------------------------------------------------------------

54: #pragma omp parallel for simd collapse(2)

55:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

56:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

57:           pre_vol(i, j) = volume(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

58:           post_vol(i, j) = volume(i, j);

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42c890 PUSH	%RBP

0x42c891 MOV	%RSP,%RBP

0x42c894 PUSH	%R15

0x42c896 PUSH	%R14

0x42c898 PUSH	%R13

0x42c89a PUSH	%R12

0x42c89c PUSH	%RBX

0x42c89d AND	$-0x40,%RSP

0x42c8a1 SUB	$0x40,%RSP

0x42c8a5 MOV	0x28(%RDI),%EAX

0x42c8a8 MOV	0x2c(%RDI),%EDX

0x42c8ab MOV	0x20(%RDI),%EBX

0x42c8ae MOV	0x24(%RDI),%ECX

0x42c8b1 MOV	%RDI,0x38(%RSP)

0x42c8b6 ADD	$0x4,%EDX

0x42c8b9 DEC	%EBX

0x42c8bb LEA	-0x1(%RAX),%R13D

0x42c8bf MOV	%EDX,0x1c(%RSP)

0x42c8c3 MOV	%EBX,0x18(%RSP)

0x42c8c7 CMP	%EDX,%R13D

0x42c8ca JGE	42cd73

0x42c8d0 MOV	%EDX,%R14D

0x42c8d3 LEA	0x4(%RCX),%R15D

0x42c8d7 SUB	%R13D,%R14D

0x42c8da CMP	%R15D,%EBX

0x42c8dd JGE	42cd73

0x42c8e3 MOV	%R15D,%R12D

0x42c8e6 SUB	%EBX,%R12D

0x42c8e9 IMUL	%R12D,%R14D

0x42c8ed MOV	%R12D,0x14(%RSP)

0x42c8f2 CALL	404630 <omp_get_num_threads@plt>

0x42c8f7 MOV	%EAX,%EBX

0x42c8f9 CALL	404520 <omp_get_thread_num@plt>

0x42c8fe XOR	%EDX,%EDX

0x42c900 MOV	0x38(%RSP),%RDI

0x42c905 MOV	%EAX,%ECX

0x42c907 MOV	%R14D,%EAX

0x42c90a DIV	%EBX

0x42c90c CMP	%EDX,%ECX

0x42c90e MOV	%EAX,%ESI

0x42c910 JB	42cd9b

0x42c916 IMUL	%ESI,%ECX

0x42c919 ADD	%EDX,%ECX

0x42c91b LEA	(%RSI,%RCX,1),%R8D

0x42c91f MOV	%R8D,0x10(%RSP)

0x42c924 CMP	%R8D,%ECX

0x42c927 JAE	42cd73

0x42c92d MOV	%ECX,%EAX

0x42c92f XOR	%EDX,%EDX

0x42c931 MOV	0x18(%RSP),%R9D

0x42c936 VMOVQ	(%RDI),%XMM3

0x42c93a DIVL	0x14(%RSP)

0x42c93e VMOVQ	0x8(%RDI),%XMM4

0x42c943 VMOVQ	0x10(%RDI),%XMM2

0x42c948 VMOVQ	0x18(%RDI),%XMM14

0x42c94d ADD	%EDX,%R9D

0x42c950 ADD	%R13D,%EAX

0x42c953 MOV	%ESI,%EDX

0x42c955 SUB	%R9D,%R15D

0x42c958 MOVSXD	%EAX,%R8

0x42c95b MOV	%R9D,0x38(%RSP)

(196) 0x42c960 CMP	%R15D,%EDX

(196) 0x42c963 CMOVA	%R15D,%EDX

(196) 0x42c967 LEA	(%RCX,%RDX,1),%EBX

(196) 0x42c96a CMP	%EBX,%ECX

(196) 0x42c96c JAE	42cd4a

(196) 0x42c972 VMOVQ	%XMM3,%R10

(196) 0x42c977 VMOVQ	%XMM4,%R15

(196) 0x42c97c LEA	-0x1(%RDX),%ESI

(196) 0x42c97f VMOVQ	%XMM2,%R13

(196) 0x42c984 VMOVQ	%XMM14,%R14

(196) 0x42c989 MOV	(%R10),%R11

(196) 0x42c98c MOV	(%R15),%R9

(196) 0x42c98f VMOVQ	0x10(%R10),%XMM7

(196) 0x42c995 MOV	0x10(%R15),%R12

(196) 0x42c999 MOV	(%R13),%R10

(196) 0x42c99d MOV	(%R14),%R15

(196) 0x42c9a0 VMOVQ	0x10(%R13),%XMM6

(196) 0x42c9a6 VMOVQ	0x10(%R14),%XMM5

(196) 0x42c9ac IMUL	%R8,%R11

(196) 0x42c9b0 IMUL	%R8,%R10

(196) 0x42c9b4 IMUL	%R8,%R15

(196) 0x42c9b8 IMUL	%R8,%R9

(196) 0x42c9bc MOV	%R11,0x20(%RSP)

(196) 0x42c9c1 MOV	%R10,0x30(%RSP)

(196) 0x42c9c6 MOV	%R15,0x28(%RSP)

(196) 0x42c9cb CMP	$0x6,%ESI

(196) 0x42c9ce JBE	42cd90

(196) 0x42c9d4 MOVSXD	0x38(%RSP),%RAX

(196) 0x42c9d9 VMOVQ	%XMM7,%R13

(196) 0x42c9de VMOVQ	%XMM6,%RDI

(196) 0x42c9e3 LEA	0x1(%R9,%RAX,1),%RSI

(196) 0x42c9e8 LEA	(%R11,%RAX,1),%R11

(196) 0x42c9ec LEA	(%R10,%RAX,1),%R10

(196) 0x42c9f0 ADD	%R15,%RAX

(196) 0x42c9f3 SAL	$0x3,%RSI

(196) 0x42c9f7 VMOVQ	%XMM5,%R15

(196) 0x42c9fc LEA	(%R13,%R11,8),%R11

(196) 0x42ca01 LEA	(%R12,%RSI,1),%R14

(196) 0x42ca05 LEA	-0x8(%R12,%RSI,1),%R13

(196) 0x42ca0a LEA	(%R15,%RAX,8),%RSI

(196) 0x42ca0e MOV	%EDX,%R15D

(196) 0x42ca11 LEA	(%RDI,%R10,8),%R10

(196) 0x42ca15 XOR	%EAX,%EAX

(196) 0x42ca17 SHR	$0x3,%R15D

(196) 0x42ca1b SAL	$0x6,%R15

(196) 0x42ca1f LEA	-0x40(%R15),%RDI

(196) 0x42ca23 SHR	$0x6,%RDI

(196) 0x42ca27 INC	%RDI

(196) 0x42ca2a AND	$0x3,%EDI

(196) 0x42ca2d JE	42cad0

(196) 0x42ca33 CMP	$0x1,%RDI

(196) 0x42ca37 JE	42ca98

(196) 0x42ca39 CMP	$0x2,%RDI

(196) 0x42ca3d JE	42ca69

(196) 0x42ca3f VMOVUPD	(%R11),%ZMM13

(196) 0x42ca45 VADDPD	(%R14),%ZMM13,%ZMM0

(196) 0x42ca4b MOV	$0x40,%EAX

(196) 0x42ca50 VSUBPD	(%R13),%ZMM0,%ZMM1

(196) 0x42ca57 VMOVUPD	%ZMM1,(%R10)

(196) 0x42ca5d VMOVUPD	(%R11),%ZMM8

(196) 0x42ca63 VMOVUPD	%ZMM8,(%RSI)

(196) 0x42ca69 VMOVUPD	(%R11,%RAX,1),%ZMM9

(196) 0x42ca70 VADDPD	(%R14,%RAX,1),%ZMM9,%ZMM10

(196) 0x42ca77 VSUBPD	(%R13,%RAX,1),%ZMM10,%ZMM11

(196) 0x42ca7f VMOVUPD	%ZMM11,(%R10,%RAX,1)

(196) 0x42ca86 VMOVUPD	(%R11,%RAX,1),%ZMM12

(196) 0x42ca8d VMOVUPD	%ZMM12,(%RSI,%RAX,1)

(196) 0x42ca94 ADD	$0x40,%RAX

(196) 0x42ca98 VMOVUPD	(%R11,%RAX,1),%ZMM15

(196) 0x42ca9f VADDPD	(%R14,%RAX,1),%ZMM15,%ZMM13

(196) 0x42caa6 VSUBPD	(%R13,%RAX,1),%ZMM13,%ZMM0

(196) 0x42caae VMOVUPD	%ZMM0,(%R10,%RAX,1)

(196) 0x42cab5 VMOVUPD	(%R11,%RAX,1),%ZMM1

(196) 0x42cabc VMOVUPD	%ZMM1,(%RSI,%RAX,1)

(196) 0x42cac3 ADD	$0x40,%RAX

(196) 0x42cac7 CMP	%R15,%RAX

(196) 0x42caca JE	42cb9a

  (197) 0x42cad0 VMOVUPD	(%R11,%RAX,1),%ZMM8

  (197) 0x42cad7 VADDPD	(%R14,%RAX,1),%ZMM8,%ZMM9

  (197) 0x42cade VSUBPD	(%R13,%RAX,1),%ZMM9,%ZMM10

  (197) 0x42cae6 VMOVUPD	%ZMM10,(%R10,%RAX,1)

  (197) 0x42caed VMOVUPD	(%R11,%RAX,1),%ZMM11

  (197) 0x42caf4 VMOVUPD	%ZMM11,(%RSI,%RAX,1)

  (197) 0x42cafb VMOVUPD	0x40(%R11,%RAX,1),%ZMM12

  (197) 0x42cb03 VADDPD	0x40(%R14,%RAX,1),%ZMM12,%ZMM15

  (197) 0x42cb0b VSUBPD	0x40(%R13,%RAX,1),%ZMM15,%ZMM13

  (197) 0x42cb13 VMOVUPD	%ZMM13,0x40(%R10,%RAX,1)

  (197) 0x42cb1b VMOVUPD	0x40(%R11,%RAX,1),%ZMM0

  (197) 0x42cb23 VMOVUPD	%ZMM0,0x40(%RSI,%RAX,1)

  (197) 0x42cb2b VMOVUPD	0x80(%R11,%RAX,1),%ZMM1

  (197) 0x42cb33 VADDPD	0x80(%R14,%RAX,1),%ZMM1,%ZMM8

  (197) 0x42cb3b VSUBPD	0x80(%R13,%RAX,1),%ZMM8,%ZMM9

  (197) 0x42cb43 VMOVUPD	%ZMM9,0x80(%R10,%RAX,1)

  (197) 0x42cb4b VMOVUPD	0x80(%R11,%RAX,1),%ZMM10

  (197) 0x42cb53 VMOVUPD	%ZMM10,0x80(%RSI,%RAX,1)

  (197) 0x42cb5b VMOVUPD	0xc0(%R11,%RAX,1),%ZMM11

  (197) 0x42cb63 VADDPD	0xc0(%R14,%RAX,1),%ZMM11,%ZMM12

  (197) 0x42cb6b VSUBPD	0xc0(%R13,%RAX,1),%ZMM12,%ZMM15

  (197) 0x42cb73 VMOVUPD	%ZMM15,0xc0(%R10,%RAX,1)

  (197) 0x42cb7b VMOVUPD	0xc0(%R11,%RAX,1),%ZMM13

  (197) 0x42cb83 VMOVUPD	%ZMM13,0xc0(%RSI,%RAX,1)

  (197) 0x42cb8b ADD	$0x100,%RAX

  (197) 0x42cb91 CMP	%R15,%RAX

  (197) 0x42cb94 JNE	42cad0

(196) 0x42cb9a MOV	0x38(%RSP),%R11D

(196) 0x42cb9f MOV	%EDX,%EAX

(196) 0x42cba1 AND	$-0x8,%EAX

(196) 0x42cba4 ADD	%EAX,%ECX

(196) 0x42cba6 LEA	(%RAX,%R11,1),%EDI

(196) 0x42cbaa TEST	$0x7,%DL

(196) 0x42cbad JE	42cd48

(196) 0x42cbb3 SUB	%EAX,%EDX

(196) 0x42cbb5 LEA	-0x1(%RDX),%R14D

(196) 0x42cbb9 CMP	$0x2,%R14D

(196) 0x42cbbd JBE	42cc3c

(196) 0x42cbbf MOVSXD	0x38(%RSP),%R13

(196) 0x42cbc4 MOV	0x20(%RSP),%R10

(196) 0x42cbc9 VMOVQ	%XMM7,%R15

(196) 0x42cbce LEA	(%R10,%R13,1),%RSI

(196) 0x42cbd2 LEA	(%R9,%R13,1),%R11

(196) 0x42cbd6 ADD	%RAX,%RSI

(196) 0x42cbd9 LEA	0x1(%RAX,%R11,1),%R14

(196) 0x42cbde VMOVQ	%XMM6,%R11

(196) 0x42cbe3 LEA	(%R15,%RSI,8),%R10

(196) 0x42cbe7 VMOVUPD	(%R12,%R14,8),%YMM0

(196) 0x42cbed VSUBPD	-0x8(%R12,%R14,8),%YMM0,%YMM1

(196) 0x42cbf4 MOV	0x30(%RSP),%RSI

(196) 0x42cbf9 VADDPD	(%R10),%YMM1,%YMM8

(196) 0x42cbfe LEA	(%RSI,%R13,1),%R15

(196) 0x42cc02 ADD	%RAX,%R15

(196) 0x42cc05 VMOVUPD	%YMM8,(%R11,%R15,8)

(196) 0x42cc0b VMOVUPD	(%R10),%YMM9

(196) 0x42cc10 MOV	0x28(%RSP),%R10

(196) 0x42cc15 ADD	%R10,%R13

(196) 0x42cc18 ADD	%RAX,%R13

(196) 0x42cc1b VMOVQ	%XMM5,%RAX

(196) 0x42cc20 VMOVUPD	%YMM9,(%RAX,%R13,8)

(196) 0x42cc26 MOV	%EDX,%R13D

(196) 0x42cc29 AND	$-0x4,%R13D

(196) 0x42cc2d ADD	%R13D,%EDI

(196) 0x42cc30 ADD	%R13D,%ECX

(196) 0x42cc33 AND	$0x3,%EDX

(196) 0x42cc36 JE	42cd48

(196) 0x42cc3c MOV	0x20(%RSP),%R14

(196) 0x42cc41 MOV	0x30(%RSP),%R10

(196) 0x42cc46 LEA	0x1(%RDI),%EAX

(196) 0x42cc49 MOVSXD	%EDI,%RDX

(196) 0x42cc4c CLTQ

(196) 0x42cc4e VMOVQ	%XMM7,%RSI

(196) 0x42cc53 LEA	(%R9,%RDX,1),%R13

(196) 0x42cc57 LEA	(%R9,%RAX,1),%R11

(196) 0x42cc5b LEA	(%R14,%RDX,1),%R15

(196) 0x42cc5f LEA	(%R10,%RDX,1),%R10

(196) 0x42cc63 LEA	(%RSI,%R15,8),%RSI

(196) 0x42cc67 LEA	(%R12,%R11,8),%R15

(196) 0x42cc6b VMOVQ	%XMM6,%R11

(196) 0x42cc70 VMOVSD	(%R15),%XMM10

(196) 0x42cc75 VSUBSD	(%R12,%R13,8),%XMM10,%XMM11

(196) 0x42cc7b VADDSD	(%RSI),%XMM11,%XMM12

(196) 0x42cc7f VMOVSD	%XMM12,(%R11,%R10,8)

(196) 0x42cc85 VMOVSD	(%RSI),%XMM15

(196) 0x42cc89 MOV	0x28(%RSP),%RSI

(196) 0x42cc8e VMOVQ	%XMM5,%R10

(196) 0x42cc93 ADD	%RSI,%RDX

(196) 0x42cc96 VMOVSD	%XMM15,(%R10,%RDX,8)

(196) 0x42cc9c LEA	0x1(%RCX),%EDX

(196) 0x42cc9f CMP	%EBX,%EDX

(196) 0x42cca1 JAE	42cd48

(196) 0x42cca7 LEA	0x2(%RDI),%R10D

(196) 0x42ccab LEA	(%RAX,%R14,1),%R11

(196) 0x42ccaf VMOVQ	%XMM7,%R13

(196) 0x42ccb4 ADD	$0x2,%ECX

(196) 0x42ccb7 MOVSXD	%R10D,%RDX

(196) 0x42ccba LEA	(%R13,%R11,8),%RSI

(196) 0x42ccbf LEA	(%R9,%RDX,1),%R11

(196) 0x42ccc3 LEA	(%R12,%R11,8),%R13

(196) 0x42ccc7 MOV	0x30(%RSP),%R11

(196) 0x42cccc VMOVSD	(%R13),%XMM13

(196) 0x42ccd2 VADDSD	(%RSI),%XMM13,%XMM0

(196) 0x42ccd6 VSUBSD	(%R15),%XMM0,%XMM1

(196) 0x42ccdb VMOVQ	%XMM6,%R15

(196) 0x42cce0 LEA	(%R11,%RAX,1),%R10

(196) 0x42cce4 VMOVSD	%XMM1,(%R15,%R10,8)

(196) 0x42ccea VMOVSD	(%RSI),%XMM8

(196) 0x42ccee MOV	0x28(%RSP),%RSI

(196) 0x42ccf3 VMOVQ	%XMM5,%R10

(196) 0x42ccf8 ADD	%RSI,%RAX

(196) 0x42ccfb VMOVSD	%XMM8,(%R10,%RAX,8)

(196) 0x42cd01 CMP	%EBX,%ECX

(196) 0x42cd03 JAE	42cd48

(196) 0x42cd05 ADD	$0x3,%EDI

(196) 0x42cd08 VMOVQ	%XMM7,%RCX

(196) 0x42cd0d MOV	%R11,%R15

(196) 0x42cd10 ADD	%RDX,%R14

(196) 0x42cd13 MOVSXD	%EDI,%RDI

(196) 0x42cd16 LEA	(%RCX,%R14,8),%RAX

(196) 0x42cd1a ADD	%RDX,%R15

(196) 0x42cd1d ADD	%RDX,%RSI

(196) 0x42cd20 ADD	%R9,%RDI

(196) 0x42cd23 VMOVSD	(%R12,%RDI,8),%XMM7

(196) 0x42cd29 VMOVQ	%XMM6,%R12

(196) 0x42cd2e VADDSD	(%RAX),%XMM7,%XMM9

(196) 0x42cd32 VSUBSD	(%R13),%XMM9,%XMM10

(196) 0x42cd38 VMOVSD	%XMM10,(%R12,%R15,8)

(196) 0x42cd3e VMOVSD	(%RAX),%XMM6

(196) 0x42cd42 VMOVSD	%XMM6,(%R10,%RSI,8)

(196) 0x42cd48 MOV	%EBX,%ECX

(196) 0x42cd4a INC	%R8

(196) 0x42cd4d CMP	%R8D,0x1c(%RSP)

(196) 0x42cd52 JLE	42cd70

(196) 0x42cd54 MOV	0x10(%RSP),%EDX

(196) 0x42cd58 MOV	0x18(%RSP),%EBX

(196) 0x42cd5c MOV	0x14(%RSP),%R15D

(196) 0x42cd61 SUB	%ECX,%EDX

(196) 0x42cd63 MOV	%EBX,0x38(%RSP)

(196) 0x42cd67 JMP	42c960

0x42cd6c NOPL	(%RAX)

0x42cd70 VZEROUPPER

0x42cd73 LEA	-0x28(%RBP),%RSP

0x42cd77 POP	%RBX

0x42cd78 POP	%R12

0x42cd7a POP	%R13

0x42cd7c POP	%R14

0x42cd7e POP	%R15

0x42cd80 POP	%RBP

0x42cd81 RET

0x42cd82 NOPW	%CS:(%RAX,%RAX,1)

0x42cd8d NOPL	(%RAX)

(196) 0x42cd90 MOV	0x38(%RSP),%EDI

(196) 0x42cd94 XOR	%EAX,%EAX

(196) 0x42cd96 JMP	42cbb3

0x42cd9b INC	%ESI

0x42cd9d XOR	%EDX,%EDX

0x42cd9f JMP	42c916

0x42cda4 NOPW	%CS:(%RAX,%RAX,1)

0x42cdaf NOP

Coverage (%)	Name	Source Location	Module
►96.86+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.26+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:65	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:81	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:54-58
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:54-58
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.63 cycles (1.25x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.38 cycles (1.28x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:57

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	78
nb uops	77
loop length	265
used x86 registers	14
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.63
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42c890

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x24(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
DEC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x1(%RAX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EBX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42cd73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RCX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42cd73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EBX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R12D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R12D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 42cd9b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x50b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R8D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42cd73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x18(%RSP),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x14(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%RDI),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %R9D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 42c916 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x86>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:54-58
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:54-58
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.38 cycles (1.28x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:56
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:57

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	78
nb uops	77
loop length	265
used x86 registers	14
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.63
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42c890

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x24(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
DEC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA -0x1(%RAX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EBX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42cd73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RCX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42cd73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EBX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R12D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R12D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 42cd9b <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x50b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RSI,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R8D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42cd73 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x18(%RSP),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x14(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%RDI),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %R9D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 42c916 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.1+0x86>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.28	0.47
▼Loop 196 - advec_cell.cpp:56-58 - exec–	0.00	0.01
○Loop 197 - advec_cell.cpp:57-58 - exec	1.28	0.47

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code