OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:44-48 [...]	Coverage (incl. loops): 1.55% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

46:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

47:           pre_vol(i, j) = volume(i, j) + (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j) + vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

48:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42c140 PUSH	%RBP

0x42c141 MOV	%RSP,%RBP

0x42c144 PUSH	%R15

0x42c146 PUSH	%R14

0x42c148 PUSH	%R13

0x42c14a PUSH	%R12

0x42c14c PUSH	%RBX

0x42c14d AND	$-0x40,%RSP

0x42c151 ADD	$-0x80,%RSP

0x42c155 MOV	0x30(%RDI),%EAX

0x42c158 MOV	0x34(%RDI),%EDX

0x42c15b MOV	0x28(%RDI),%EBX

0x42c15e MOV	0x2c(%RDI),%ESI

0x42c161 ADD	$0x4,%EDX

0x42c164 LEA	-0x1(%RBX),%ECX

0x42c167 LEA	-0x1(%RAX),%R14D

0x42c16b MOV	%EDX,0x38(%RSP)

0x42c16f MOV	%ECX,0x34(%RSP)

0x42c173 CMP	%EDX,%R14D

0x42c176 JGE	42c843

0x42c17c MOV	%EDX,%EBX

0x42c17e LEA	0x4(%RSI),%R15D

0x42c182 SUB	%R14D,%EBX

0x42c185 CMP	%R15D,%ECX

0x42c188 JGE	42c843

0x42c18e MOV	%RDI,%R13

0x42c191 MOV	%R15D,%EDI

0x42c194 SUB	%ECX,%EDI

0x42c196 MOV	%EDI,0x3c(%RSP)

0x42c19a CALL	404630 <omp_get_num_threads@plt>

0x42c19f MOV	%EAX,%R12D

0x42c1a2 CALL	404520 <omp_get_thread_num@plt>

0x42c1a7 XOR	%EDX,%EDX

0x42c1a9 MOV	%EAX,%R8D

0x42c1ac MOV	0x3c(%RSP),%EAX

0x42c1b0 IMUL	%EBX,%EAX

0x42c1b3 DIV	%R12D

0x42c1b6 MOV	%EAX,%R9D

0x42c1b9 CMP	%EDX,%R8D

0x42c1bc JB	42c87c

0x42c1c2 IMUL	%R9D,%R8D

0x42c1c6 LEA	(%R8,%RDX,1),%R11D

0x42c1ca LEA	(%R9,%R11,1),%R10D

0x42c1ce MOV	%R10D,0x30(%RSP)

0x42c1d3 CMP	%R10D,%R11D

0x42c1d6 JAE	42c843

0x42c1dc MOV	%R11D,%EAX

0x42c1df XOR	%EDX,%EDX

0x42c1e1 MOV	0x34(%RSP),%ECX

0x42c1e5 VMOVQ	(%R13),%XMM15

0x42c1eb DIVL	0x3c(%RSP)

0x42c1ef VMOVQ	0x8(%R13),%XMM14

0x42c1f5 VMOVQ	0x10(%R13),%XMM13

0x42c1fb MOV	%R15D,%R12D

0x42c1fe VMOVQ	0x18(%R13),%XMM12

0x42c204 VMOVQ	0x20(%R13),%XMM11

0x42c20a ADD	%EDX,%ECX

0x42c20c LEA	(%RAX,%R14,1),%R14D

0x42c210 MOV	%R9D,%EAX

0x42c213 SUB	%ECX,%R12D

0x42c216 MOV	%ECX,0x74(%RSP)

0x42c21a MOVSXD	%R14D,%RCX

0x42c21d NOPL	(%RAX)

(194) 0x42c220 CMP	%R12D,%EAX

(194) 0x42c223 CMOVA	%R12D,%EAX

(194) 0x42c227 LEA	(%R11,%RAX,1),%ESI

(194) 0x42c22b MOV	%ESI,0x70(%RSP)

(194) 0x42c22f CMP	%ESI,%R11D

(194) 0x42c232 JAE	42c860

(194) 0x42c238 VMOVQ	%XMM13,%R8

(194) 0x42c23d LEA	0x1(%RCX),%R9

(194) 0x42c241 VMOVQ	%XMM15,%RBX

(194) 0x42c246 MOV	(%R8),%R14

(194) 0x42c249 MOV	%R9,0x40(%RSP)

(194) 0x42c24e VMOVQ	%XMM14,%RDI

(194) 0x42c253 VMOVQ	%XMM12,%RSI

(194) 0x42c258 MOV	(%RBX),%R13

(194) 0x42c25b MOV	(%RDI),%R15

(194) 0x42c25e VMOVQ	0x10(%RBX),%XMM18

(194) 0x42c265 MOV	0x10(%RDI),%RBX

(194) 0x42c269 VMOVQ	%XMM11,%RDI

(194) 0x42c26e VMOVQ	0x10(%RSI),%XMM10

(194) 0x42c273 MOV	0x10(%R8),%R10

(194) 0x42c277 VMOVQ	0x10(%RDI),%XMM9

(194) 0x42c27c IMUL	%R14,%R9

(194) 0x42c280 IMUL	%RCX,%R13

(194) 0x42c284 IMUL	%RCX,%R15

(194) 0x42c288 MOV	%R9,%RDX

(194) 0x42c28b MOV	%R9,0x58(%RSP)

(194) 0x42c290 SUB	%R14,%RDX

(194) 0x42c293 MOV	(%RSI),%R14

(194) 0x42c296 MOV	%R13,0x48(%RSP)

(194) 0x42c29b MOV	%R15,0x50(%RSP)

(194) 0x42c2a0 MOV	%RDX,0x60(%RSP)

(194) 0x42c2a5 IMUL	%RCX,%R14

(194) 0x42c2a9 IMUL	(%RDI),%RCX

(194) 0x42c2ad MOV	%R14,0x68(%RSP)

(194) 0x42c2b2 MOV	%RCX,0x78(%RSP)

(194) 0x42c2b7 LEA	-0x1(%RAX),%ECX

(194) 0x42c2ba CMP	$0x6,%ECX

(194) 0x42c2bd JBE	42c870

(194) 0x42c2c3 MOVSXD	0x74(%RSP),%RSI

(194) 0x42c2c8 VMOVQ	%XMM18,%R12

(194) 0x42c2ce LEA	0x1(%R15,%RSI,1),%RCX

(194) 0x42c2d3 ADD	%RSI,%R13

(194) 0x42c2d6 LEA	(%RDX,%RSI,1),%RDX

(194) 0x42c2da LEA	(%R14,%RSI,1),%RDI

(194) 0x42c2de SAL	$0x3,%RCX

(194) 0x42c2e2 VMOVQ	%XMM10,%R14

(194) 0x42c2e7 LEA	(%R12,%R13,8),%R8

(194) 0x42c2eb LEA	(%RBX,%RCX,1),%R15

(194) 0x42c2ef LEA	-0x8(%RBX,%RCX,1),%R12

(194) 0x42c2f4 LEA	(%R10,%RDX,8),%RCX

(194) 0x42c2f8 MOV	0x78(%RSP),%RDX

(194) 0x42c2fd LEA	(%R14,%RDI,8),%R13

(194) 0x42c301 MOV	%EAX,%R14D

(194) 0x42c304 LEA	(%R9,%RSI,1),%R9

(194) 0x42c308 VMOVQ	%XMM9,%RDI

(194) 0x42c30d LEA	(%R10,%R9,8),%R9

(194) 0x42c311 SHR	$0x3,%R14D

(194) 0x42c315 SAL	$0x6,%R14

(194) 0x42c319 ADD	%RDX,%RSI

(194) 0x42c31c LEA	(%RDI,%RSI,8),%RDX

(194) 0x42c320 LEA	-0x40(%R14),%RDI

(194) 0x42c324 XOR	%ESI,%ESI

(194) 0x42c326 SHR	$0x6,%RDI

(194) 0x42c32a INC	%RDI

(194) 0x42c32d AND	$0x3,%EDI

(194) 0x42c330 JE	42c439

(194) 0x42c336 CMP	$0x1,%RDI

(194) 0x42c33a JE	42c3e0

(194) 0x42c340 CMP	$0x2,%RDI

(194) 0x42c344 JE	42c390

(194) 0x42c346 VMOVUPD	(%R8),%ZMM16

(194) 0x42c34c VADDPD	(%R15),%ZMM16,%ZMM17

(194) 0x42c352 VMOVUPD	(%R12),%ZMM20

(194) 0x42c359 MOV	$0x40,%ESI

(194) 0x42c35e VADDPD	(%R9),%ZMM17,%ZMM19

(194) 0x42c364 VADDPD	(%RCX),%ZMM20,%ZMM21

(194) 0x42c36a VSUBPD	%ZMM21,%ZMM19,%ZMM22

(194) 0x42c370 VMOVUPD	%ZMM22,(%R13)

(194) 0x42c377 VMOVUPD	(%R12),%ZMM23

(194) 0x42c37e VSUBPD	(%R15),%ZMM23,%ZMM24

(194) 0x42c384 VADDPD	%ZMM22,%ZMM24,%ZMM25

(194) 0x42c38a VMOVUPD	%ZMM25,(%RDX)

(194) 0x42c390 VMOVUPD	(%R8,%RSI,1),%ZMM26

(194) 0x42c397 VADDPD	(%R15,%RSI,1),%ZMM26,%ZMM27

(194) 0x42c39e VMOVUPD	(%R12,%RSI,1),%ZMM29

(194) 0x42c3a5 VADDPD	(%R9,%RSI,1),%ZMM27,%ZMM28

(194) 0x42c3ac VADDPD	(%RCX,%RSI,1),%ZMM29,%ZMM30

(194) 0x42c3b3 VSUBPD	%ZMM30,%ZMM28,%ZMM31

(194) 0x42c3b9 VMOVUPD	%ZMM31,(%R13,%RSI,1)

(194) 0x42c3c1 VMOVUPD	(%R12,%RSI,1),%ZMM16

(194) 0x42c3c8 VSUBPD	(%R15,%RSI,1),%ZMM16,%ZMM17

(194) 0x42c3cf VADDPD	%ZMM31,%ZMM17,%ZMM19

(194) 0x42c3d5 VMOVUPD	%ZMM19,(%RDX,%RSI,1)

(194) 0x42c3dc ADD	$0x40,%RSI

(194) 0x42c3e0 VMOVUPD	(%R8,%RSI,1),%ZMM20

(194) 0x42c3e7 VADDPD	(%R15,%RSI,1),%ZMM20,%ZMM21

(194) 0x42c3ee VMOVUPD	(%R12,%RSI,1),%ZMM23

(194) 0x42c3f5 VADDPD	(%R9,%RSI,1),%ZMM21,%ZMM22

(194) 0x42c3fc VADDPD	(%RCX,%RSI,1),%ZMM23,%ZMM24

(194) 0x42c403 VSUBPD	%ZMM24,%ZMM22,%ZMM25

(194) 0x42c409 VMOVUPD	%ZMM25,(%R13,%RSI,1)

(194) 0x42c411 VMOVUPD	(%R12,%RSI,1),%ZMM26

(194) 0x42c418 VSUBPD	(%R15,%RSI,1),%ZMM26,%ZMM27

(194) 0x42c41f VADDPD	%ZMM25,%ZMM27,%ZMM28

(194) 0x42c425 VMOVUPD	%ZMM28,(%RDX,%RSI,1)

(194) 0x42c42c ADD	$0x40,%RSI

(194) 0x42c430 CMP	%R14,%RSI

(194) 0x42c433 JE	42c591

  (195) 0x42c439 VMOVUPD	(%R8,%RSI,1),%ZMM29

  (195) 0x42c440 VADDPD	(%R15,%RSI,1),%ZMM29,%ZMM30

  (195) 0x42c447 VMOVUPD	(%R12,%RSI,1),%ZMM16

  (195) 0x42c44e VADDPD	(%R9,%RSI,1),%ZMM30,%ZMM31

  (195) 0x42c455 VADDPD	(%RCX,%RSI,1),%ZMM16,%ZMM17

  (195) 0x42c45c VSUBPD	%ZMM17,%ZMM31,%ZMM19

  (195) 0x42c462 VMOVUPD	%ZMM19,(%R13,%RSI,1)

  (195) 0x42c46a VMOVUPD	(%R12,%RSI,1),%ZMM20

  (195) 0x42c471 VSUBPD	(%R15,%RSI,1),%ZMM20,%ZMM21

  (195) 0x42c478 VADDPD	%ZMM19,%ZMM21,%ZMM22

  (195) 0x42c47e VMOVUPD	%ZMM22,(%RDX,%RSI,1)

  (195) 0x42c485 VMOVUPD	0x40(%R8,%RSI,1),%ZMM1

  (195) 0x42c48d VADDPD	0x40(%R15,%RSI,1),%ZMM1,%ZMM0

  (195) 0x42c495 VMOVUPD	0x40(%R12,%RSI,1),%ZMM23

  (195) 0x42c49d VADDPD	0x40(%R9,%RSI,1),%ZMM0,%ZMM2

  (195) 0x42c4a5 VADDPD	0x40(%RCX,%RSI,1),%ZMM23,%ZMM24

  (195) 0x42c4ad VSUBPD	%ZMM24,%ZMM2,%ZMM3

  (195) 0x42c4b3 VMOVUPD	%ZMM3,0x40(%R13,%RSI,1)

  (195) 0x42c4bb VMOVUPD	0x40(%R12,%RSI,1),%ZMM25

  (195) 0x42c4c3 VSUBPD	0x40(%R15,%RSI,1),%ZMM25,%ZMM26

  (195) 0x42c4cb VADDPD	%ZMM3,%ZMM26,%ZMM27

  (195) 0x42c4d1 VMOVUPD	%ZMM27,0x40(%RDX,%RSI,1)

  (195) 0x42c4d9 VMOVUPD	0x80(%R8,%RSI,1),%ZMM4

  (195) 0x42c4e1 VADDPD	0x80(%R15,%RSI,1),%ZMM4,%ZMM5

  (195) 0x42c4e9 VMOVUPD	0x80(%R12,%RSI,1),%ZMM28

  (195) 0x42c4f1 VADDPD	0x80(%R9,%RSI,1),%ZMM5,%ZMM6

  (195) 0x42c4f9 VADDPD	0x80(%RCX,%RSI,1),%ZMM28,%ZMM29

  (195) 0x42c501 VSUBPD	%ZMM29,%ZMM6,%ZMM7

  (195) 0x42c507 VMOVUPD	%ZMM7,0x80(%R13,%RSI,1)

  (195) 0x42c50f VMOVUPD	0x80(%R12,%RSI,1),%ZMM30

  (195) 0x42c517 VSUBPD	0x80(%R15,%RSI,1),%ZMM30,%ZMM31

  (195) 0x42c51f VADDPD	%ZMM7,%ZMM31,%ZMM16

  (195) 0x42c525 VMOVUPD	%ZMM16,0x80(%RDX,%RSI,1)

  (195) 0x42c52d VMOVUPD	0xc0(%R8,%RSI,1),%ZMM8

  (195) 0x42c535 VADDPD	0xc0(%R15,%RSI,1),%ZMM8,%ZMM1

  (195) 0x42c53d VMOVUPD	0xc0(%R12,%RSI,1),%ZMM17

  (195) 0x42c545 VADDPD	0xc0(%R9,%RSI,1),%ZMM1,%ZMM0

  (195) 0x42c54d VADDPD	0xc0(%RCX,%RSI,1),%ZMM17,%ZMM19

  (195) 0x42c555 VSUBPD	%ZMM19,%ZMM0,%ZMM2

  (195) 0x42c55b VMOVUPD	%ZMM2,0xc0(%R13,%RSI,1)

  (195) 0x42c563 VMOVUPD	0xc0(%R12,%RSI,1),%ZMM20

  (195) 0x42c56b VSUBPD	0xc0(%R15,%RSI,1),%ZMM20,%ZMM21

  (195) 0x42c573 VADDPD	%ZMM2,%ZMM21,%ZMM22

  (195) 0x42c579 VMOVUPD	%ZMM22,0xc0(%RDX,%RSI,1)

  (195) 0x42c581 ADD	$0x100,%RSI

  (195) 0x42c588 CMP	%R14,%RSI

  (195) 0x42c58b JNE	42c439

(194) 0x42c591 MOV	0x74(%RSP),%R8D

(194) 0x42c596 MOV	%EAX,%R13D

(194) 0x42c599 AND	$-0x8,%R13D

(194) 0x42c59d ADD	%R13D,%R11D

(194) 0x42c5a0 LEA	(%R13,%R8,1),%EDI

(194) 0x42c5a5 TEST	$0x7,%AL

(194) 0x42c5a7 JE	42c807

(194) 0x42c5ad SUB	%R13D,%EAX

(194) 0x42c5b0 LEA	-0x1(%RAX),%R15D

(194) 0x42c5b4 CMP	$0x2,%R15D

(194) 0x42c5b8 JBE	42c677

(194) 0x42c5be MOVSXD	0x74(%RSP),%R12

(194) 0x42c5c3 MOV	0x50(%RSP),%R9

(194) 0x42c5c8 MOV	0x48(%RSP),%R14

(194) 0x42c5cd MOV	0x58(%RSP),%R15

(194) 0x42c5d2 LEA	(%R9,%R12,1),%RCX

(194) 0x42c5d6 LEA	(%R15,%R12,1),%R9

(194) 0x42c5da MOV	0x68(%RSP),%R15

(194) 0x42c5df LEA	0x1(%R13,%RCX,1),%RDX

(194) 0x42c5e4 LEA	(%R14,%R12,1),%RCX

(194) 0x42c5e8 MOV	0x60(%RSP),%R14

(194) 0x42c5ed ADD	%R13,%R9

(194) 0x42c5f0 ADD	%R13,%RCX

(194) 0x42c5f3 VMOVUPD	(%R10,%R9,8),%YMM3

(194) 0x42c5f9 VMOVQ	%XMM10,%R9

(194) 0x42c5fe SAL	$0x3,%RDX

(194) 0x42c602 LEA	(%RBX,%RDX,1),%RSI

(194) 0x42c606 LEA	-0x8(%RBX,%RDX,1),%R8

(194) 0x42c60b VMOVQ	%XMM18,%RDX

(194) 0x42c611 VADDPD	(%RDX,%RCX,8),%YMM3,%YMM4

(194) 0x42c616 LEA	(%R14,%R12,1),%RCX

(194) 0x42c61a VMOVUPD	(%RSI),%YMM6

(194) 0x42c61e VSUBPD	(%R8),%YMM6,%YMM7

(194) 0x42c623 ADD	%R13,%RCX

(194) 0x42c626 LEA	(%R15,%R12,1),%RDX

(194) 0x42c62a VSUBPD	(%R10,%RCX,8),%YMM4,%YMM5

(194) 0x42c630 ADD	%R13,%RDX

(194) 0x42c633 VADDPD	%YMM7,%YMM5,%YMM8

(194) 0x42c637 VMOVUPD	%YMM8,(%R9,%RDX,8)

(194) 0x42c63d VMOVUPD	(%R8),%YMM1

(194) 0x42c642 VSUBPD	(%RSI),%YMM1,%YMM0

(194) 0x42c646 MOV	0x78(%RSP),%RSI

(194) 0x42c64b ADD	%RSI,%R12

(194) 0x42c64e ADD	%R13,%R12

(194) 0x42c651 VMOVQ	%XMM9,%R13

(194) 0x42c656 VADDPD	%YMM8,%YMM0,%YMM2

(194) 0x42c65b VMOVUPD	%YMM2,(%R13,%R12,8)

(194) 0x42c662 MOV	%EAX,%R12D

(194) 0x42c665 AND	$-0x4,%R12D

(194) 0x42c669 ADD	%R12D,%EDI

(194) 0x42c66c ADD	%R12D,%R11D

(194) 0x42c66f TEST	$0x3,%AL

(194) 0x42c671 JE	42c807

(194) 0x42c677 LEA	0x1(%RDI),%R8D

(194) 0x42c67b MOV	0x48(%RSP),%R9

(194) 0x42c680 MOV	0x58(%RSP),%R13

(194) 0x42c685 MOVSXD	%EDI,%RAX

(194) 0x42c688 MOVSXD	%R8D,%RDX

(194) 0x42c68b MOV	0x50(%RSP),%R8

(194) 0x42c690 VMOVQ	%XMM18,%R12

(194) 0x42c696 LEA	(%R13,%RAX,1),%R15

(194) 0x42c69b LEA	(%R8,%RAX,1),%RCX

(194) 0x42c69f LEA	(%R8,%RDX,1),%R14

(194) 0x42c6a3 LEA	(%RBX,%R14,8),%RSI

(194) 0x42c6a7 LEA	(%RBX,%RCX,8),%R14

(194) 0x42c6ab LEA	(%R9,%RAX,1),%RCX

(194) 0x42c6af VMOVSD	(%R12,%RCX,8),%XMM3

(194) 0x42c6b5 MOV	0x60(%RSP),%R12

(194) 0x42c6ba VADDSD	(%R10,%R15,8),%XMM3,%XMM4

(194) 0x42c6c0 MOV	0x68(%RSP),%R15

(194) 0x42c6c5 VMOVSD	(%RSI),%XMM6

(194) 0x42c6c9 VSUBSD	(%R14),%XMM6,%XMM7

(194) 0x42c6ce LEA	(%R12,%RAX,1),%RCX

(194) 0x42c6d2 LEA	(%R15,%RAX,1),%R15

(194) 0x42c6d6 VSUBSD	(%R10,%RCX,8),%XMM4,%XMM5

(194) 0x42c6dc VMOVQ	%XMM10,%RCX

(194) 0x42c6e1 VADDSD	%XMM7,%XMM5,%XMM8

(194) 0x42c6e5 VMOVSD	%XMM8,(%RCX,%R15,8)

(194) 0x42c6eb MOV	0x78(%RSP),%R15

(194) 0x42c6f0 MOV	0x70(%RSP),%ECX

(194) 0x42c6f4 VMOVSD	(%R14),%XMM1

(194) 0x42c6f9 VMOVQ	%XMM9,%R14

(194) 0x42c6fe VSUBSD	(%RSI),%XMM1,%XMM0

(194) 0x42c702 VADDSD	%XMM8,%XMM0,%XMM2

(194) 0x42c707 ADD	%R15,%RAX

(194) 0x42c70a VMOVSD	%XMM2,(%R14,%RAX,8)

(194) 0x42c710 LEA	0x1(%R11),%EAX

(194) 0x42c714 CMP	%ECX,%EAX

(194) 0x42c716 JAE	42c807

(194) 0x42c71c LEA	0x2(%RDI),%EAX

(194) 0x42c71f MOV	%R8,%RCX

(194) 0x42c722 LEA	(%RDX,%R9,1),%R15

(194) 0x42c726 ADD	$0x2,%R11D

(194) 0x42c72a CLTQ

(194) 0x42c72c LEA	(%R8,%RAX,1),%R8

(194) 0x42c730 LEA	(%RBX,%R8,8),%R14

(194) 0x42c734 MOV	%R9,%R8

(194) 0x42c737 VMOVQ	%XMM18,%R9

(194) 0x42c73d VMOVSD	(%R9,%R15,8),%XMM3

(194) 0x42c743 MOV	0x68(%RSP),%R15

(194) 0x42c748 MOV	%R13,%R9

(194) 0x42c74b LEA	(%R13,%RDX,1),%R13

(194) 0x42c750 VADDSD	(%R14),%XMM3,%XMM4

(194) 0x42c755 VADDSD	(%R10,%R13,8),%XMM4,%XMM5

(194) 0x42c75b MOV	%R12,%R13

(194) 0x42c75e LEA	(%R12,%RDX,1),%R12

(194) 0x42c762 VMOVSD	(%R10,%R12,8),%XMM6

(194) 0x42c768 VMOVQ	%XMM10,%R12

(194) 0x42c76d VADDSD	(%RSI),%XMM6,%XMM7

(194) 0x42c771 VSUBSD	%XMM7,%XMM5,%XMM8

(194) 0x42c775 ADD	%RDX,%R15

(194) 0x42c778 VMOVSD	%XMM8,(%R12,%R15,8)

(194) 0x42c77e MOV	0x78(%RSP),%R15

(194) 0x42c783 VMOVSD	(%RSI),%XMM1

(194) 0x42c787 VMOVQ	%XMM9,%RSI

(194) 0x42c78c VSUBSD	(%R14),%XMM1,%XMM0

(194) 0x42c791 VADDSD	%XMM8,%XMM0,%XMM2

(194) 0x42c796 ADD	%R15,%RDX

(194) 0x42c799 VMOVSD	%XMM2,(%RSI,%RDX,8)

(194) 0x42c79e MOV	0x70(%RSP),%EDX

(194) 0x42c7a2 CMP	%EDX,%R11D

(194) 0x42c7a5 JAE	42c807

(194) 0x42c7a7 ADD	$0x3,%EDI

(194) 0x42c7aa ADD	%RAX,%R8

(194) 0x42c7ad ADD	%RAX,%R9

(194) 0x42c7b0 ADD	%RAX,%R13

(194) 0x42c7b3 MOVSXD	%EDI,%R11

(194) 0x42c7b6 VMOVSD	(%R10,%R13,8),%XMM6

(194) 0x42c7bc ADD	%RAX,%R15

(194) 0x42c7bf VADDSD	(%R14),%XMM6,%XMM7

(194) 0x42c7c4 ADD	%RCX,%R11

(194) 0x42c7c7 LEA	(%RBX,%R11,8),%RDI

(194) 0x42c7cb VMOVQ	%XMM18,%RBX

(194) 0x42c7d1 VMOVSD	(%RBX,%R8,8),%XMM3

(194) 0x42c7d7 VADDSD	(%RDI),%XMM3,%XMM4

(194) 0x42c7db VADDSD	(%R10,%R9,8),%XMM4,%XMM5

(194) 0x42c7e1 MOV	0x68(%RSP),%R10

(194) 0x42c7e6 VSUBSD	%XMM7,%XMM5,%XMM8

(194) 0x42c7ea ADD	%RAX,%R10

(194) 0x42c7ed VMOVSD	%XMM8,(%R12,%R10,8)

(194) 0x42c7f3 VMOVSD	(%R14),%XMM10

(194) 0x42c7f8 VSUBSD	(%RDI),%XMM10,%XMM1

(194) 0x42c7fc VADDSD	%XMM8,%XMM1,%XMM0

(194) 0x42c801 VMOVSD	%XMM0,(%RSI,%R15,8)

(194) 0x42c807 MOV	0x70(%RSP),%R11D

(194) 0x42c80c MOV	0x40(%RSP),%RCX

(194) 0x42c811 CMP	%ECX,0x38(%RSP)

(194) 0x42c815 JLE	42c840

(194) 0x42c817 MOV	0x30(%RSP),%EAX

(194) 0x42c81b MOV	0x34(%RSP),%R14D

(194) 0x42c820 MOV	0x3c(%RSP),%R12D

(194) 0x42c825 SUB	%R11D,%EAX

(194) 0x42c828 MOV	%R14D,0x74(%RSP)

(194) 0x42c82d JMP	42c220

0x42c832 NOPW	%CS:(%RAX,%RAX,1)

0x42c83d NOPL	(%RAX)

0x42c840 VZEROUPPER

0x42c843 LEA	-0x28(%RBP),%RSP

0x42c847 POP	%RBX

0x42c848 POP	%R12

0x42c84a POP	%R13

0x42c84c POP	%R14

0x42c84e POP	%R15

0x42c850 POP	%RBP

0x42c851 RET

0x42c852 NOPW	%CS:(%RAX,%RAX,1)

0x42c85d NOPL	(%RAX)

(194) 0x42c860 LEA	0x1(%RCX),%R15

(194) 0x42c864 MOV	%R15,0x40(%RSP)

(194) 0x42c869 JMP	42c80c

0x42c86b NOPL	(%RAX,%RAX,1)

(194) 0x42c870 MOV	0x74(%RSP),%EDI

(194) 0x42c874 XOR	%R13D,%R13D

(194) 0x42c877 JMP	42c5ad

0x42c87c INC	%R9D

0x42c87f XOR	%EDX,%EDX

0x42c881 JMP	42c1c2

0x42c886 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.93+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.25+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:44	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection(global_variables&)	advection.cpp:50	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:44-48
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.75 cycles (1.23x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	81
nb uops	78
loop length	295
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42c140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RBX),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42c843 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(%RSI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42c843 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ECX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3c(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42c87c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x73c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R9,%R11,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R10D,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42c843 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x34(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%R13),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x3c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%R13),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ 0x18(%R13),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R13),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA (%RAX,%R14,1),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ECX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %R14D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42c1c2 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x82>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_cell.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:44-48
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:47

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 68 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	81
nb uops	78
loop length	295
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	4%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	12%

Vector efficiency ratios

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42c140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RBX),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42c843 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x4(%RSI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 42c843 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ECX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x3c(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 42c87c <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x73c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R9,%R11,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R10D,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 42c843 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x703>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R11D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x34(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%R13),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x3c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%R13),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ 0x18(%R13),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R13),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA (%RAX,%R14,1),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ECX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %R14D,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42c1c2 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_._omp_fn.0+0x82>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.55	0.57
▼Loop 194 - advec_cell.cpp:44-48 - exec–	0.00	0.01
○Loop 195 - advec_cell.cpp:47-48 - exec	1.55	0.57

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code