OV - exec - Function accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D< ...	Module: exec	Source: accelerate.cpp:40-53 [...]	Coverage (incl. loops): 5.29% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp: 40 - 53

--------------------------------------------------------------------------------

40: #pragma omp parallel for simd collapse(2)

41:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42b2c0 PUSH	%RBP

0x42b2c1 MOV	%RSP,%RBP

0x42b2c4 PUSH	%R15

0x42b2c6 PUSH	%R14

0x42b2c8 PUSH	%R13

0x42b2ca PUSH	%R12

0x42b2cc PUSH	%RBX

0x42b2cd MOV	%RDI,%RBX

0x42b2d0 AND	$-0x40,%RSP

0x42b2d4 SUB	$0x100,%RSP

0x42b2db MOV	0x60(%RDI),%EAX

0x42b2de MOV	0x64(%RDI),%EDX

0x42b2e1 MOV	0x58(%RDI),%ESI

0x42b2e4 MOV	0x5c(%RDI),%EDI

0x42b2e7 ADD	$0x3,%EDX

0x42b2ea INC	%ESI

0x42b2ec LEA	0x1(%RAX),%R12D

0x42b2f0 MOV	%EDX,0x58(%RSP)

0x42b2f4 MOV	%ESI,0x54(%RSP)

0x42b2f8 CMP	%EDX,%R12D

0x42b2fb JGE	42bf13

0x42b301 MOV	%EDX,%R14D

0x42b304 LEA	0x3(%RDI),%R15D

0x42b308 SUB	%R12D,%R14D

0x42b30b CMP	%R15D,%ESI

0x42b30e JGE	42bf13

0x42b314 MOV	%R15D,%ECX

0x42b317 SUB	%ESI,%ECX

0x42b319 MOV	%ECX,0x5c(%RSP)

0x42b31d CALL	404630 <omp_get_num_threads@plt>

0x42b322 MOV	%EAX,%R13D

0x42b325 CALL	404520 <omp_get_thread_num@plt>

0x42b32a XOR	%EDX,%EDX

0x42b32c MOV	%EAX,%R8D

0x42b32f MOV	0x5c(%RSP),%EAX

0x42b333 IMUL	%R14D,%EAX

0x42b337 DIV	%R13D

0x42b33a MOV	%EAX,%ECX

0x42b33c CMP	%EDX,%R8D

0x42b33f JB	42bf47

0x42b345 IMUL	%ECX,%R8D

0x42b349 LEA	(%R8,%RDX,1),%EAX

0x42b34d LEA	(%RCX,%RAX,1),%R9D

0x42b351 MOV	%EAX,0xcc(%RSP)

0x42b358 MOV	%R9D,0x50(%RSP)

0x42b35d CMP	%R9D,%EAX

0x42b360 JAE	42bf13

0x42b366 XOR	%EDX,%EDX

0x42b368 MOV	0x54(%RSP),%R10D

0x42b36d MOV	0x18(%RBX),%R11

0x42b371 MOV	0x10(%RBX),%RSI

0x42b375 DIVL	0x5c(%RSP)

0x42b379 MOV	0x30(%RBX),%RDI

0x42b37d MOV	0x20(%RBX),%R14

0x42b381 MOV	0x40(%RBX),%R13

0x42b385 MOV	0x38(%RBX),%R8

0x42b389 MOV	0x8(%RBX),%R9

0x42b38d VMOVSD	0x39083(%RIP),%XMM0

0x42b395 VMULSD	0x50(%RBX),%XMM0,%XMM4

0x42b39a VBROADCASTSD	%XMM4,%YMM1

0x42b39f VBROADCASTSD	%XMM4,%ZMM20

0x42b3a5 MOV	%R11,0x48(%RSP)

0x42b3aa MOV	%RSI,0x40(%RSP)

0x42b3af MOV	%RDI,0x38(%RSP)

0x42b3b4 MOV	%R14,0x28(%RSP)

0x42b3b9 MOV	%R13,0x20(%RSP)

0x42b3be MOV	%R8,0x18(%RSP)

0x42b3c3 MOV	%R9,0x10(%RSP)

0x42b3c8 ADD	%EDX,%R10D

0x42b3cb MOV	0x48(%RBX),%RDX

0x42b3cf ADD	%R12D,%EAX

0x42b3d2 SUB	%R10D,%R15D

0x42b3d5 MOV	%R10D,0xb0(%RSP)

0x42b3dd CLTQ

0x42b3df MOV	%R15D,%R10D

0x42b3e2 MOV	(%RBX),%R15

0x42b3e5 MOV	0x28(%RBX),%RBX

0x42b3e9 MOV	%RAX,0xb8(%RSP)

0x42b3f1 MOV	%RDX,0x8(%RSP)

0x42b3f6 MOV	%R15,0x30(%RSP)

0x42b3fb MOV	%RBX,(%RSP)

0x42b3ff NOP

(190) 0x42b400 MOV	0xcc(%RSP),%R12D

(190) 0x42b408 CMP	%R10D,%ECX

(190) 0x42b40b CMOVBE	%ECX,%R10D

(190) 0x42b40f MOV	%R10D,0xc0(%RSP)

(190) 0x42b417 LEA	(%R12,%R10,1),%ECX

(190) 0x42b41b MOV	%ECX,0xc8(%RSP)

(190) 0x42b422 CMP	%ECX,%R12D

(190) 0x42b425 JAE	42bece

(190) 0x42b42b MOV	0xb8(%RSP),%RSI

(190) 0x42b433 MOV	0x38(%RSP),%R15

(190) 0x42b438 MOV	0x30(%RSP),%RBX

(190) 0x42b43d MOV	0x20(%RSP),%R8

(190) 0x42b442 MOV	%R10D,%R12D

(190) 0x42b445 MOV	0x48(%RSP),%R10

(190) 0x42b44a MOV	0x40(%RSP),%R11

(190) 0x42b44f LEA	-0x1(%R12),%R12D

(190) 0x42b454 MOV	%ESI,%EAX

(190) 0x42b456 MOV	(%R15),%RDX

(190) 0x42b459 MOV	0x10(%R15),%R13

(190) 0x42b45d VMOVQ	0x10(%RBX),%XMM23

(190) 0x42b464 DEC	%EAX

(190) 0x42b466 MOV	(%R10),%R9

(190) 0x42b469 VMOVQ	0x10(%R10),%XMM16

(190) 0x42b470 VMOVQ	0x10(%R11),%XMM6

(190) 0x42b476 MOVSXD	%EAX,%RDI

(190) 0x42b479 MOV	0x28(%RSP),%RAX

(190) 0x42b47e MOV	(%R11),%R10

(190) 0x42b481 VMOVQ	0x10(%R8),%XMM29

(190) 0x42b488 MOV	%RDI,%RCX

(190) 0x42b48b MOV	%RDI,%R14

(190) 0x42b48e MOV	%RDI,%R11

(190) 0x42b491 IMUL	%RSI,%RDX

(190) 0x42b495 MOV	%R13,0x78(%RSP)

(190) 0x42b49a MOV	%RDI,%R13

(190) 0x42b49d IMUL	%R9,%R14

(190) 0x42b4a1 MOV	(%RAX),%R15

(190) 0x42b4a4 VMOVQ	0x10(%RAX),%XMM14

(190) 0x42b4a9 IMUL	%R10,%R11

(190) 0x42b4ad VMOVQ	%RDX,%XMM27

(190) 0x42b4b3 MOV	(%RBX),%RDX

(190) 0x42b4b6 MOV	0x18(%RSP),%RBX

(190) 0x42b4bb IMUL	%RSI,%R9

(190) 0x42b4bf MOV	%R14,0x60(%RSP)

(190) 0x42b4c4 IMUL	%RSI,%R10

(190) 0x42b4c8 VMOVQ	%R11,%XMM9

(190) 0x42b4cd VMOVQ	%R9,%XMM15

(190) 0x42b4d2 IMUL	%R15,%R13

(190) 0x42b4d6 IMUL	%RSI,%R15

(190) 0x42b4da MOV	(%RBX),%RAX

(190) 0x42b4dd VMOVQ	%R10,%XMM11

(190) 0x42b4e2 IMUL	%RDX,%RCX

(190) 0x42b4e6 VMOVQ	%R13,%XMM25

(190) 0x42b4ec MOV	0x10(%RSP),%R13

(190) 0x42b4f1 IMUL	%RSI,%RDX

(190) 0x42b4f5 MOV	%R15,0x88(%RSP)

(190) 0x42b4fd MOV	(%R8),%R15

(190) 0x42b500 VMOVQ	%RCX,%XMM26

(190) 0x42b506 MOV	0x10(%RBX),%RCX

(190) 0x42b50a IMUL	%RSI,%RAX

(190) 0x42b50e MOV	%RDX,0x80(%RSP)

(190) 0x42b516 MOV	(%R13),%R8

(190) 0x42b51a VMOVQ	0x10(%R13),%XMM24

(190) 0x42b521 IMUL	%RSI,%R15

(190) 0x42b525 MOV	%RAX,0x90(%RSP)

(190) 0x42b52d MOV	%RCX,0x98(%RSP)

(190) 0x42b535 MOV	%R15,0x68(%RSP)

(190) 0x42b53a MOV	0x8(%RSP),%RBX

(190) 0x42b53f MOV	(%RSP),%RAX

(190) 0x42b543 IMUL	%RSI,%R8

(190) 0x42b547 MOV	(%RAX),%R13

(190) 0x42b54a MOV	(%RBX),%RCX

(190) 0x42b54d VMOVQ	0x10(%RBX),%XMM28

(190) 0x42b554 VMOVQ	0x10(%RAX),%XMM13

(190) 0x42b559 VMOVQ	%R8,%XMM10

(190) 0x42b55e IMUL	%R13,%RDI

(190) 0x42b562 IMUL	%RSI,%RCX

(190) 0x42b566 IMUL	%RSI,%R13

(190) 0x42b56a MOV	%RDI,0xa0(%RSP)

(190) 0x42b572 MOV	%RCX,0x70(%RSP)

(190) 0x42b577 MOV	%R13,0xa8(%RSP)

(190) 0x42b57f CMP	$0x6,%R12D

(190) 0x42b583 JBE	42bf30

(190) 0x42b589 MOV	%RDX,%RDI

(190) 0x42b58c MOVSXD	0xb0(%RSP),%RDX

(190) 0x42b594 VMOVQ	%XMM6,%RSI

(190) 0x42b599 VMOVQ	%XMM16,%RAX

(190) 0x42b59f ADD	%RDX,%R11

(190) 0x42b5a2 LEA	(%R14,%RDX,1),%RBX

(190) 0x42b5a6 LEA	(%R9,%RDX,1),%R14

(190) 0x42b5aa LEA	(%R10,%RDX,1),%R10

(190) 0x42b5ae SAL	$0x3,%R11

(190) 0x42b5b2 VMOVQ	%XMM16,%R9

(190) 0x42b5b8 LEA	-0x8(%RSI,%R11,1),%R12

(190) 0x42b5bd LEA	(%RDI,%RDX,1),%RDI

(190) 0x42b5c1 LEA	(%RCX,%RDX,1),%RCX

(190) 0x42b5c5 ADD	%RDX,%R8

(190) 0x42b5c8 SAL	$0x3,%RBX

(190) 0x42b5cc VMOVQ	%R12,%XMM22

(190) 0x42b5d2 VMOVQ	%XMM16,%R12

(190) 0x42b5d8 SAL	$0x3,%R14

(190) 0x42b5dc SAL	$0x3,%R10

(190) 0x42b5e0 LEA	-0x8(%RAX,%RBX,1),%R13

(190) 0x42b5e5 ADD	%R14,%R12

(190) 0x42b5e8 LEA	-0x8(%RAX,%R14,1),%RAX

(190) 0x42b5ed VMOVQ	%XMM6,%R14

(190) 0x42b5f2 LEA	-0x8(%RSI,%R10,1),%RSI

(190) 0x42b5f7 ADD	%R10,%R14

(190) 0x42b5fa MOV	0x78(%RSP),%R10

(190) 0x42b5ff VMOVQ	%R13,%XMM31

(190) 0x42b605 VMOVQ	%XMM6,%R13

(190) 0x42b60a VMOVQ	%RAX,%XMM21

(190) 0x42b610 ADD	%RBX,%R9

(190) 0x42b613 MOV	%R12,0xd8(%RSP)

(190) 0x42b61b ADD	%R13,%R11

(190) 0x42b61e VMOVQ	%RSI,%XMM19

(190) 0x42b624 VMOVQ	%XMM26,%RSI

(190) 0x42b62a MOV	%R14,0xe0(%RSP)

(190) 0x42b632 MOV	%R11,0xf0(%RSP)

(190) 0x42b63a VMOVQ	%XMM27,%R11

(190) 0x42b640 LEA	(%RSI,%RDX,1),%R12

(190) 0x42b644 VMOVQ	%XMM23,%R14

(190) 0x42b64a LEA	(%R11,%RDX,1),%RAX

(190) 0x42b64e LEA	(%R14,%RDI,8),%RSI

(190) 0x42b652 MOV	%R9,0xe8(%RSP)

(190) 0x42b65a MOV	0x98(%RSP),%RDI

(190) 0x42b662 LEA	(%R10,%RAX,8),%R13

(190) 0x42b666 MOV	0x90(%RSP),%RAX

(190) 0x42b66e LEA	(%R14,%R12,8),%R9

(190) 0x42b672 MOV	0x88(%RSP),%R12

(190) 0x42b67a VMOVQ	%R9,%XMM12

(190) 0x42b67f VMOVQ	%XMM25,%RBX

(190) 0x42b685 LEA	(%RBX,%RDX,1),%R10

(190) 0x42b689 VMOVQ	%R13,%XMM18

(190) 0x42b68f LEA	(%R15,%RDX,1),%R13

(190) 0x42b693 VMOVQ	%XMM14,%R11

(190) 0x42b698 SAL	$0x3,%R10

(190) 0x42b69c VMOVQ	%XMM29,%R15

(190) 0x42b6a2 VMOVDQA64	%XMM21,%XMM8

(190) 0x42b6a8 ADD	%RDX,%RAX

(190) 0x42b6ab LEA	(%R12,%RDX,1),%R9

(190) 0x42b6af LEA	-0x8(%R11,%R10,1),%RBX

(190) 0x42b6b4 ADD	%R11,%R10

(190) 0x42b6b7 LEA	(%RDI,%RAX,8),%R12

(190) 0x42b6bb VMOVQ	%XMM28,%RAX

(190) 0x42b6c1 MOV	0xa0(%RSP),%RDI

(190) 0x42b6c9 LEA	(%R15,%R13,8),%R15

(190) 0x42b6cd VMOVQ	%R12,%XMM17

(190) 0x42b6d3 LEA	(%RAX,%RCX,8),%R12

(190) 0x42b6d7 MOV	0xa8(%RSP),%RAX

(190) 0x42b6df VMOVQ	%XMM13,%RCX

(190) 0x42b6e4 VMOVQ	%RBX,%XMM5

(190) 0x42b6e9 VMOVDQA64	%XMM17,%XMM7

(190) 0x42b6ef MOV	%RSI,%RBX

(190) 0x42b6f2 SAL	$0x3,%R9

(190) 0x42b6f6 LEA	(%RDI,%RDX,1),%RDI

(190) 0x42b6fa LEA	-0x8(%R11,%R9,1),%R14

(190) 0x42b6ff ADD	%R11,%R9

(190) 0x42b702 VMOVQ	%XMM24,%R11

(190) 0x42b708 ADD	%RAX,%RDX

(190) 0x42b70b VMOVQ	%XMM13,%RAX

(190) 0x42b710 MOV	%R14,%RSI

(190) 0x42b713 VMOVQ	%XMM5,%R14

(190) 0x42b718 SAL	$0x3,%R8

(190) 0x42b71c SAL	$0x3,%RDI

(190) 0x42b720 SAL	$0x3,%RDX

(190) 0x42b724 LEA	-0x8(%R11,%R8,1),%R13

(190) 0x42b729 ADD	%R11,%R8

(190) 0x42b72c LEA	-0x8(%RCX,%RDI,1),%R11

(190) 0x42b731 ADD	%RCX,%RDI

(190) 0x42b734 LEA	-0x8(%RCX,%RDX,1),%RCX

(190) 0x42b739 ADD	%RAX,%RDX

(190) 0x42b73c MOV	0xc0(%RSP),%EAX

(190) 0x42b743 VMOVQ	%R11,%XMM3

(190) 0x42b748 MOV	%RCX,%R11

(190) 0x42b74b MOV	%RDX,0xd0(%RSP)

(190) 0x42b753 SHR	$0x3,%EAX

(190) 0x42b756 SAL	$0x6,%RAX

(190) 0x42b75a MOV	%RAX,0xf8(%RSP)

(190) 0x42b762 XOR	%EAX,%EAX

(190) 0x42b764 NOPW	%CS:(%RAX,%RAX,1)

(190) 0x42b76f NOP

  (192) 0x42b770 VMOVQ	%XMM8,%RDX

  (192) 0x42b775 VMOVQ	%XMM19,%RCX

  (192) 0x42b77b VMOVUPD	(%RSI,%RAX,1),%ZMM30

  (192) 0x42b782 VSUBPD	(%R9,%RAX,1),%ZMM30,%ZMM21

  (192) 0x42b789 VMOVUPD	(%RDX,%RAX,1),%ZMM2

  (192) 0x42b790 VMULPD	(%RCX,%RAX,1),%ZMM2,%ZMM0

  (192) 0x42b797 VMOVQ	%XMM22,%RDX

  (192) 0x42b79d VMOVQ	%XMM31,%RCX

  (192) 0x42b7a3 VMOVUPD	(%RDX,%RAX,1),%ZMM2

  (192) 0x42b7aa MOV	0xe8(%RSP),%RDX

  (192) 0x42b7b2 VMULPD	(%RBX,%RAX,1),%ZMM21,%ZMM17

  (192) 0x42b7b9 VFMADD132PD	(%RCX,%RAX,1),%ZMM0,%ZMM2

  (192) 0x42b7c0 MOV	0xf0(%RSP),%RCX

  (192) 0x42b7c8 VMOVUPD	(%RDX,%RAX,1),%ZMM5

  (192) 0x42b7cf MOV	0xd8(%RSP),%RDX

  (192) 0x42b7d7 VMULPD	(%RCX,%RAX,1),%ZMM5,%ZMM0

  (192) 0x42b7de MOV	0xe0(%RSP),%RCX

  (192) 0x42b7e6 VMOVUPD	(%RCX,%RAX,1),%ZMM5

  (192) 0x42b7ed VFMADD231PD	(%RDX,%RAX,1),%ZMM5,%ZMM0

  (192) 0x42b7f4 VADDPD	%ZMM2,%ZMM0,%ZMM2

  (192) 0x42b7fa VMOVUPD	(%R14,%RAX,1),%ZMM5

  (192) 0x42b801 VMOVQ	%XMM12,%RDX

  (192) 0x42b806 VDIVPD	%ZMM2,%ZMM20,%ZMM0

  (192) 0x42b80c VMOVQ	%XMM18,%RCX

  (192) 0x42b812 VSUBPD	(%R10,%RAX,1),%ZMM5,%ZMM2

  (192) 0x42b819 VFMADD132PD	(%RDX,%RAX,1),%ZMM17,%ZMM2

  (192) 0x42b820 VFMADD213PD	(%RCX,%RAX,1),%ZMM0,%ZMM2

  (192) 0x42b827 VMOVUPD	%ZMM2,(%R15,%RAX,1)

  (192) 0x42b82e VMOVUPD	(%R10,%RAX,1),%ZMM30

  (192) 0x42b835 VSUBPD	(%R9,%RAX,1),%ZMM30,%ZMM21

  (192) 0x42b83c VMULPD	(%R8,%RAX,1),%ZMM21,%ZMM17

  (192) 0x42b843 VMOVUPD	(%R14,%RAX,1),%ZMM5

  (192) 0x42b84a VMOVQ	%XMM7,%RCX

  (192) 0x42b84f VSUBPD	(%RSI,%RAX,1),%ZMM5,%ZMM2

  (192) 0x42b856 VFMADD132PD	(%R13,%RAX,1),%ZMM17,%ZMM2

  (192) 0x42b85e VFMADD213PD	(%RCX,%RAX,1),%ZMM0,%ZMM2

  (192) 0x42b865 VMOVQ	%XMM3,%RCX

  (192) 0x42b86a VMOVUPD	%ZMM2,(%R12,%RAX,1)

  (192) 0x42b871 VMOVUPD	(%RCX,%RAX,1),%ZMM5

  (192) 0x42b878 MOV	0xd0(%RSP),%RCX

  (192) 0x42b880 VSUBPD	(%RDI,%RAX,1),%ZMM5,%ZMM2

  (192) 0x42b887 VMOVUPD	(%R11,%RAX,1),%ZMM30

  (192) 0x42b88e VSUBPD	(%RCX,%RAX,1),%ZMM30,%ZMM21

  (192) 0x42b895 VMULPD	(%RBX,%RAX,1),%ZMM21,%ZMM17

  (192) 0x42b89c VFMADD132PD	(%RDX,%RAX,1),%ZMM17,%ZMM2

  (192) 0x42b8a3 VFMADD213PD	(%R15,%RAX,1),%ZMM0,%ZMM2

  (192) 0x42b8aa VMOVUPD	%ZMM2,(%R15,%RAX,1)

  (192) 0x42b8b1 VMOVUPD	(%RDI,%RAX,1),%ZMM30

  (192) 0x42b8b8 VSUBPD	(%RCX,%RAX,1),%ZMM30,%ZMM21

  (192) 0x42b8bf MOV	0xf8(%RSP),%RCX

  (192) 0x42b8c7 VMOVQ	%XMM3,%RDX

  (192) 0x42b8cc VMULPD	(%R8,%RAX,1),%ZMM21,%ZMM17

  (192) 0x42b8d3 VMOVUPD	(%RDX,%RAX,1),%ZMM5

  (192) 0x42b8da VSUBPD	(%R11,%RAX,1),%ZMM5,%ZMM2

  (192) 0x42b8e1 VFMADD132PD	(%R13,%RAX,1),%ZMM17,%ZMM2

  (192) 0x42b8e9 VFMADD213PD	(%R12,%RAX,1),%ZMM2,%ZMM0

  (192) 0x42b8f0 VMOVUPD	%ZMM0,(%R12,%RAX,1)

  (192) 0x42b8f7 ADD	$0x40,%RAX

  (192) 0x42b8fb CMP	%RCX,%RAX

  (192) 0x42b8fe JNE	42b770

(190) 0x42b904 MOV	0xc0(%RSP),%R8D

(190) 0x42b90c MOV	0xb0(%RSP),%R10D

(190) 0x42b914 MOV	%R8D,%EDX

(190) 0x42b917 AND	$-0x8,%EDX

(190) 0x42b91a ADD	%EDX,0xcc(%RSP)

(190) 0x42b921 LEA	(%RDX,%R10,1),%R9D

(190) 0x42b925 MOV	%R9D,0xf8(%RSP)

(190) 0x42b92d TEST	$0x7,%R8B

(190) 0x42b931 JE	42bec0

(190) 0x42b937 MOV	0xc0(%RSP),%ECX

(190) 0x42b93e SUB	%EDX,%ECX

(190) 0x42b940 LEA	-0x1(%RCX),%R15D

(190) 0x42b944 CMP	$0x2,%R15D

(190) 0x42b948 JBE	42bc63

(190) 0x42b94e MOVSXD	0xb0(%RSP),%RAX

(190) 0x42b956 MOV	0x60(%RSP),%R13

(190) 0x42b95b VMOVQ	%XMM9,%RDI

(190) 0x42b960 VMOVQ	%XMM15,%R11

(190) 0x42b965 VMOVQ	%XMM26,%R9

(190) 0x42b96b VMOVQ	%XMM23,%R15

(190) 0x42b971 VMOVQ	%XMM27,%R10

(190) 0x42b977 VMOVQ	%XMM11,%R8

(190) 0x42b97c LEA	(%RDI,%RAX,1),%RBX

(190) 0x42b980 LEA	(%R11,%RAX,1),%R14

(190) 0x42b984 LEA	(%R13,%RAX,1),%R12

(190) 0x42b989 LEA	(%R9,%RAX,1),%R13

(190) 0x42b98d LEA	(%RBX,%RDX,1),%RSI

(190) 0x42b991 ADD	%RDX,%R13

(190) 0x42b994 LEA	(%R14,%RDX,1),%RBX

(190) 0x42b998 ADD	%RAX,%R10

(190) 0x42b99b MOV	%RSI,0xd0(%RSP)

(190) 0x42b9a3 VMOVQ	%XMM25,%RSI

(190) 0x42b9a9 LEA	(%R15,%R13,8),%RDI

(190) 0x42b9ad MOV	0x80(%RSP),%R15

(190) 0x42b9b5 LEA	(%RSI,%RAX,1),%R14

(190) 0x42b9b9 ADD	%RDX,%R10

(190) 0x42b9bc LEA	(%R8,%RAX,1),%R11

(190) 0x42b9c0 VMOVQ	%XMM14,%R8

(190) 0x42b9c5 ADD	%RDX,%R14

(190) 0x42b9c8 MOV	%R10,0xc0(%RSP)

(190) 0x42b9d0 VMOVQ	%RDI,%XMM8

(190) 0x42b9d5 VMOVQ	%XMM23,%RSI

(190) 0x42b9db SAL	$0x3,%R14

(190) 0x42b9df MOV	%RBX,0xf0(%RSP)

(190) 0x42b9e7 VMOVQ	%XMM14,%R9

(190) 0x42b9ec LEA	-0x8(%R8,%R14,1),%R10

(190) 0x42b9f1 LEA	(%R8,%R14,1),%R13

(190) 0x42b9f5 MOV	0x88(%RSP),%R8

(190) 0x42b9fd LEA	(%R15,%RAX,1),%RDI

(190) 0x42ba01 ADD	%RDX,%RDI

(190) 0x42ba04 VMOVQ	%R10,%XMM7

(190) 0x42ba09 MOV	%R13,0xe8(%RSP)

(190) 0x42ba11 ADD	%RDX,%R11

(190) 0x42ba14 LEA	(%RSI,%RDI,8),%R14

(190) 0x42ba18 MOV	0x68(%RSP),%RDI

(190) 0x42ba1d LEA	(%R12,%RDX,1),%R12

(190) 0x42ba21 VMOVQ	%R14,%XMM12

(190) 0x42ba26 VMOVQ	%XMM29,%R14

(190) 0x42ba2c SAL	$0x3,%R11

(190) 0x42ba30 LEA	(%R8,%RAX,1),%R10

(190) 0x42ba34 MOV	0x90(%RSP),%R8

(190) 0x42ba3c ADD	%RDX,%R10

(190) 0x42ba3f LEA	(%RDI,%RAX,1),%RSI

(190) 0x42ba43 VMOVQ	%XMM10,%RDI

(190) 0x42ba48 SAL	$0x3,%R10

(190) 0x42ba4c ADD	%RDX,%RSI

(190) 0x42ba4f LEA	-0x8(%R9,%R10,1),%R13

(190) 0x42ba54 ADD	%R9,%R10

(190) 0x42ba57 LEA	(%R8,%RAX,1),%R9

(190) 0x42ba5b MOV	0xa0(%RSP),%R8

(190) 0x42ba63 MOV	%R10,0xe0(%RSP)

(190) 0x42ba6b LEA	(%R14,%RSI,8),%R10

(190) 0x42ba6f LEA	(%RDI,%RAX,1),%RSI

(190) 0x42ba73 MOV	0x70(%RSP),%RDI

(190) 0x42ba78 LEA	(%R9,%RDX,1),%R15

(190) 0x42ba7c VMOVQ	%XMM24,%R14

(190) 0x42ba82 ADD	%RDX,%RSI

(190) 0x42ba85 MOV	%R15,0xb0(%RSP)

(190) 0x42ba8d SAL	$0x3,%RSI

(190) 0x42ba91 ADD	%RAX,%R8

(190) 0x42ba94 LEA	-0x8(%R14,%RSI,1),%R9

(190) 0x42ba99 LEA	(%R14,%RSI,1),%R15

(190) 0x42ba9d VMOVQ	%XMM28,%R14

(190) 0x42baa3 LEA	(%RDI,%RAX,1),%RSI

(190) 0x42baa7 ADD	%RDX,%R8

(190) 0x42baaa VMOVQ	%XMM13,%RDI

(190) 0x42baaf ADD	%RDX,%RSI

(190) 0x42bab2 SAL	$0x3,%R8

(190) 0x42bab6 LEA	(%R14,%RSI,8),%R14

(190) 0x42baba VMOVQ	%XMM13,%RSI

(190) 0x42babf LEA	-0x8(%RDI,%R8,1),%RDI

(190) 0x42bac4 ADD	%RSI,%R8

(190) 0x42bac7 MOV	0xa8(%RSP),%RSI

(190) 0x42bacf ADD	%RSI,%RAX

(190) 0x42bad2 VMOVQ	%XMM13,%RSI

(190) 0x42bad7 ADD	%RDX,%RAX

(190) 0x42bada VMOVQ	%XMM13,%RDX

(190) 0x42badf SAL	$0x3,%RAX

(190) 0x42bae3 ADD	%RAX,%RSI

(190) 0x42bae6 LEA	-0x8(%RDX,%RAX,1),%RDX

(190) 0x42baeb VMOVQ	%XMM6,%RAX

(190) 0x42baf0 MOV	%RSI,0xd8(%RSP)

(190) 0x42baf8 VMOVQ	%XMM16,%RSI

(190) 0x42bafe VMOVUPD	-0x8(%RAX,%R11,1),%YMM3

(190) 0x42bb05 VMOVQ	%XMM16,%RAX

(190) 0x42bb0b VMULPD	-0x8(%RSI,%RBX,8),%YMM3,%YMM5

(190) 0x42bb11 MOV	0xd0(%RSP),%RBX

(190) 0x42bb19 MOV	%R12,%RSI

(190) 0x42bb1c VMOVQ	%XMM6,%R12

(190) 0x42bb21 VMOVUPD	-0x8(%RAX,%RSI,8),%YMM0

(190) 0x42bb27 VMOVUPD	(%R12,%RBX,8),%YMM2

(190) 0x42bb2d VFMADD231PD	-0x8(%R12,%RBX,8),%YMM0,%YMM5

(190) 0x42bb34 VMULPD	(%RAX,%RSI,8),%YMM2,%YMM0

(190) 0x42bb39 MOV	0xf0(%RSP),%RSI

(190) 0x42bb41 MOV	0xe0(%RSP),%RBX

(190) 0x42bb49 VMOVUPD	(%RAX,%RSI,8),%YMM3

(190) 0x42bb4e VFMADD231PD	(%R12,%R11,1),%YMM3,%YMM0

(190) 0x42bb54 MOV	0xe8(%RSP),%R12

(190) 0x42bb5c VADDPD	%YMM5,%YMM0,%YMM5

(190) 0x42bb60 VMOVQ	%XMM7,%R11

(190) 0x42bb65 VMOVUPD	(%R13),%YMM3

(190) 0x42bb6b VMOVQ	%XMM12,%RAX

(190) 0x42bb70 VMOVUPD	(%R11),%YMM2

(190) 0x42bb75 VMOVQ	%XMM8,%RSI

(190) 0x42bb7a VDIVPD	%YMM5,%YMM1,%YMM0

(190) 0x42bb7e VSUBPD	(%R12),%YMM2,%YMM5

(190) 0x42bb84 VSUBPD	(%RBX),%YMM3,%YMM2

(190) 0x42bb88 VMULPD	(%RAX),%YMM2,%YMM3

(190) 0x42bb8c MOV	0x78(%RSP),%RAX

(190) 0x42bb91 MOV	0xc0(%RSP),%R11

(190) 0x42bb99 VFMADD132PD	(%RSI),%YMM3,%YMM5

(190) 0x42bb9e VMOVQ	%XMM7,%RSI

(190) 0x42bba3 VFMADD213PD	(%RAX,%R11,8),%YMM0,%YMM5

(190) 0x42bba9 VMOVUPD	%YMM5,(%R10)

(190) 0x42bbae VMOVUPD	(%R12),%YMM2

(190) 0x42bbb4 VMOVUPD	(%RSI),%YMM7

(190) 0x42bbb8 VSUBPD	(%RBX),%YMM2,%YMM3

(190) 0x42bbbc VSUBPD	(%R13),%YMM7,%YMM5

(190) 0x42bbc2 MOV	0xd8(%RSP),%RBX

(190) 0x42bbca MOV	0x98(%RSP),%R13

(190) 0x42bbd2 MOV	0xb0(%RSP),%R12

(190) 0x42bbda VMULPD	(%R15),%YMM3,%YMM7

(190) 0x42bbdf VMOVQ	%XMM12,%RAX

(190) 0x42bbe4 VFMADD132PD	(%R9),%YMM7,%YMM5

(190) 0x42bbe9 VMOVQ	%XMM8,%R11

(190) 0x42bbee VFMADD213PD	(%R13,%R12,8),%YMM0,%YMM5

(190) 0x42bbf5 VMOVUPD	%YMM5,(%R14)

(190) 0x42bbfa VMOVUPD	(%RDX),%YMM3

(190) 0x42bbfe VSUBPD	(%RBX),%YMM3,%YMM7

(190) 0x42bc02 VMULPD	(%RAX),%YMM7,%YMM12

(190) 0x42bc06 VMOVUPD	(%RDI),%YMM5

(190) 0x42bc0a VSUBPD	(%R8),%YMM5,%YMM2

(190) 0x42bc0f VFMADD132PD	(%R11),%YMM12,%YMM2

(190) 0x42bc14 VFMADD213PD	(%R10),%YMM0,%YMM2

(190) 0x42bc19 VMOVUPD	%YMM2,(%R10)

(190) 0x42bc1e VMOVUPD	(%R8),%YMM2

(190) 0x42bc23 VSUBPD	(%RBX),%YMM2,%YMM3

(190) 0x42bc27 VMOVUPD	(%RDI),%YMM8

(190) 0x42bc2b MOV	%ECX,%R10D

(190) 0x42bc2e VSUBPD	(%RDX),%YMM8,%YMM5

(190) 0x42bc32 VMULPD	(%R15),%YMM3,%YMM7

(190) 0x42bc37 AND	$-0x4,%R10D

(190) 0x42bc3b VFMADD132PD	(%R9),%YMM7,%YMM5

(190) 0x42bc40 VFMADD213PD	(%R14),%YMM5,%YMM0

(190) 0x42bc45 VMOVUPD	%YMM0,(%R14)

(190) 0x42bc4a ADD	%R10D,0xf8(%RSP)

(190) 0x42bc52 ADD	%R10D,0xcc(%RSP)

(190) 0x42bc5a AND	$0x3,%ECX

(190) 0x42bc5d JE	42bec0

(190) 0x42bc63 MOVSXD	0xf8(%RSP),%RAX

(190) 0x42bc6b MOV	0x70(%RSP),%R15

(190) 0x42bc70 VMOVQ	%XMM28,%R14

(190) 0x42bc76 MOV	0x68(%RSP),%RCX

(190) 0x42bc7b MOV	0x60(%RSP),%RDX

(190) 0x42bc80 VMOVQ	%XMM16,%RDI

(190) 0x42bc86 VMOVQ	%XMM15,%RBX

(190) 0x42bc8b VMOVQ	%XMM29,%R9

(190) 0x42bc91 LEA	(%RDI,%RBX,8),%R11

(190) 0x42bc95 VMOVQ	%XMM6,%R13

(190) 0x42bc9a VMOVQ	%XMM9,%R12

(190) 0x42bc9f LEA	(%R13,%R12,8),%R10

(190) 0x42bca4 VMOVQ	%XMM26,%R12

(190) 0x42bcaa ADD	%RAX,%R15

(190) 0x42bcad ADD	%RAX,%RCX

(190) 0x42bcb0 LEA	(%R14,%R15,8),%R8

(190) 0x42bcb4 LEA	(%R9,%RCX,8),%RCX

(190) 0x42bcb8 LEA	(%RDI,%RDX,8),%R9

(190) 0x42bcbc VMOVQ	%XMM27,%RDI

(190) 0x42bcc2 MOV	%R8,0xf0(%RSP)

(190) 0x42bcca MOV	0x78(%RSP),%R8

(190) 0x42bccf VMOVQ	%XMM11,%R14

(190) 0x42bcd4 VMOVQ	%XMM14,%R15

(190) 0x42bcd9 LEA	(%R13,%R14,8),%RBX

(190) 0x42bcde VMOVQ	%XMM25,%R14

(190) 0x42bce4 VMOVQ	%XMM23,%R13

(190) 0x42bcea LEA	(%R15,%R14,8),%R15

(190) 0x42bcee MOV	0x88(%RSP),%R14

(190) 0x42bcf6 LEA	(%R13,%R12,8),%R13

(190) 0x42bcfb VMOVQ	%XMM14,%R12

(190) 0x42bd00 VMOVQ	%R13,%XMM9

(190) 0x42bd05 MOV	%R10,%R13

(190) 0x42bd08 LEA	(%R8,%RDI,8),%RDX

(190) 0x42bd0c MOV	0x80(%RSP),%RDI

(190) 0x42bd14 VMOVQ	%XMM23,%R8

(190) 0x42bd1a VMOVQ	%RDX,%XMM15

(190) 0x42bd1f LEA	(%R8,%RDI,8),%RDX

(190) 0x42bd23 MOV	0x98(%RSP),%RDI

(190) 0x42bd2b LEA	(%R12,%R14,8),%R8

(190) 0x42bd2f VMOVQ	%XMM24,%R14

(190) 0x42bd35 VMOVQ	%RDX,%XMM11

(190) 0x42bd3a MOV	0x90(%RSP),%RDX

(190) 0x42bd42 LEA	(%RDI,%RDX,8),%R12

(190) 0x42bd46 MOV	0xa0(%RSP),%RDX

(190) 0x42bd4e VMOVQ	%XMM10,%RDI

(190) 0x42bd53 LEA	(%R14,%RDI,8),%R14

(190) 0x42bd57 VMOVQ	%XMM13,%RDI

(190) 0x42bd5c VMOVQ	%R12,%XMM6

(190) 0x42bd61 LEA	(%RDI,%RDX,8),%R12

(190) 0x42bd65 MOV	0xa8(%RSP),%RDX

(190) 0x42bd6d LEA	(%RDI,%RDX,8),%RDI

(190) 0x42bd71 MOV	0xcc(%RSP),%EDX

(190) 0x42bd78 SUB	%EAX,%EDX

(190) 0x42bd7a MOV	%EDX,0xf8(%RSP)

(190) 0x42bd81 MOV	0xf0(%RSP),%RDX

  (191) 0x42bd89 VMOVQ	%XMM11,%RSI

  (191) 0x42bd8e VMOVSD	-0x8(%R11,%RAX,8),%XMM14

  (191) 0x42bd95 VMOVSD	-0x8(%R9,%RAX,8),%XMM13

  (191) 0x42bd9c VMULSD	-0x8(%RBX,%RAX,8),%XMM14,%XMM10

  (191) 0x42bda2 VMOVSD	(%R9,%RAX,8),%XMM0

  (191) 0x42bda8 VFMADD231SD	-0x8(%R13,%RAX,8),%XMM13,%XMM10

  (191) 0x42bdaf VMULSD	(%R13,%RAX,8),%XMM0,%XMM12

  (191) 0x42bdb6 VMOVSD	(%R11,%RAX,8),%XMM8

  (191) 0x42bdbc VMOVSD	-0x8(%R8,%RAX,8),%XMM7

  (191) 0x42bdc3 VFMADD231SD	(%RBX,%RAX,8),%XMM8,%XMM12

  (191) 0x42bdc9 VMOVQ	%XMM15,%R10

  (191) 0x42bdce VADDSD	%XMM12,%XMM10,%XMM5

  (191) 0x42bdd3 VSUBSD	(%R8,%RAX,8),%XMM7,%XMM10

  (191) 0x42bdd9 VMULSD	(%RSI,%RAX,8),%XMM10,%XMM13

  (191) 0x42bdde VMOVQ	%XMM9,%RSI

  (191) 0x42bde3 VMOVSD	-0x8(%R15,%RAX,8),%XMM2

  (191) 0x42bdea VDIVSD	%XMM5,%XMM4,%XMM3

  (191) 0x42bdee VSUBSD	(%R15,%RAX,8),%XMM2,%XMM14

  (191) 0x42bdf4 VFMADD132SD	(%RSI,%RAX,8),%XMM13,%XMM14

  (191) 0x42bdfa VFMADD213SD	(%R10,%RAX,8),%XMM3,%XMM14

  (191) 0x42be00 VMOVQ	%XMM6,%R10

  (191) 0x42be05 VMOVSD	%XMM14,(%RCX)

  (191) 0x42be09 VMOVSD	-0x8(%R15,%RAX,8),%XMM0

  (191) 0x42be10 VMOVSD	(%R15,%RAX,8),%XMM8

  (191) 0x42be16 VSUBSD	-0x8(%R8,%RAX,8),%XMM0,%XMM12

  (191) 0x42be1d VSUBSD	(%R8,%RAX,8),%XMM8,%XMM5

  (191) 0x42be23 VMULSD	(%R14,%RAX,8),%XMM5,%XMM2

  (191) 0x42be29 VFMADD132SD	-0x8(%R14,%RAX,8),%XMM2,%XMM12

  (191) 0x42be30 VFMADD213SD	(%R10,%RAX,8),%XMM3,%XMM12

  (191) 0x42be36 VMOVQ	%XMM11,%R10

  (191) 0x42be3b VMOVSD	%XMM12,(%RDX)

  (191) 0x42be3f VMOVSD	-0x8(%R12,%RAX,8),%XMM14

  (191) 0x42be46 VMOVSD	-0x8(%RDI,%RAX,8),%XMM7

  (191) 0x42be4c VSUBSD	(%R12,%RAX,8),%XMM14,%XMM10

  (191) 0x42be52 VSUBSD	(%RDI,%RAX,8),%XMM7,%XMM13

  (191) 0x42be57 VMULSD	(%R10,%RAX,8),%XMM13,%XMM0

  (191) 0x42be5d VFMADD132SD	(%RSI,%RAX,8),%XMM0,%XMM10

  (191) 0x42be63 VFMADD213SD	(%RCX),%XMM3,%XMM10

  (191) 0x42be68 VMOVSD	%XMM10,(%RCX)

  (191) 0x42be6c VMOVSD	-0x8(%R12,%RAX,8),%XMM12

  (191) 0x42be73 MOV	0xf8(%RSP),%R10D

  (191) 0x42be7b MOV	0xc8(%RSP),%ESI

  (191) 0x42be82 VSUBSD	-0x8(%RDI,%RAX,8),%XMM12,%XMM8

  (191) 0x42be88 VMOVSD	(%R12,%RAX,8),%XMM5

  (191) 0x42be8e VSUBSD	(%RDI,%RAX,8),%XMM5,%XMM2

  (191) 0x42be93 VMULSD	(%R14,%RAX,8),%XMM2,%XMM14

  (191) 0x42be99 VFMADD132SD	-0x8(%R14,%RAX,8),%XMM14,%XMM8

  (191) 0x42bea0 INC	%RAX

  (191) 0x42bea3 VFMADD213SD	(%RDX),%XMM8,%XMM3

  (191) 0x42bea8 ADD	$0x8,%RCX

  (191) 0x42beac VMOVSD	%XMM3,(%RDX)

  (191) 0x42beb0 ADD	$0x8,%RDX

  (191) 0x42beb4 ADD	%EAX,%R10D

  (191) 0x42beb7 CMP	%ESI,%R10D

  (191) 0x42beba JB	42bd89

(190) 0x42bec0 MOV	0xc8(%RSP),%EAX

(190) 0x42bec7 MOV	%EAX,0xcc(%RSP)

(190) 0x42bece INCQ	0xb8(%RSP)

(190) 0x42bed6 MOV	0xb8(%RSP),%RCX

(190) 0x42bede CMP	%ECX,0x58(%RSP)

(190) 0x42bee2 JLE	42bf10

(190) 0x42bee4 MOV	0x50(%RSP),%ECX

(190) 0x42bee8 MOV	0xcc(%RSP),%R9D

(190) 0x42bef0 MOV	0x54(%RSP),%R11D

(190) 0x42bef5 MOV	0x5c(%RSP),%R10D

(190) 0x42befa SUB	%R9D,%ECX

(190) 0x42befd MOV	%R11D,0xb0(%RSP)

(190) 0x42bf05 JMP	42b400

0x42bf0a NOPW	(%RAX,%RAX,1)

0x42bf10 VZEROUPPER

0x42bf13 LEA	-0x28(%RBP),%RSP

0x42bf17 POP	%RBX

0x42bf18 POP	%R12

0x42bf1a POP	%R13

0x42bf1c POP	%R14

0x42bf1e POP	%R15

0x42bf20 POP	%RBP

0x42bf21 RET

0x42bf22 NOPW	%CS:(%RAX,%RAX,1)

0x42bf2d NOPL	(%RAX)

(190) 0x42bf30 MOV	0xb0(%RSP),%R14D

(190) 0x42bf38 XOR	%EDX,%EDX

(190) 0x42bf3a MOV	%R14D,0xf8(%RSP)

(190) 0x42bf42 JMP	42b937

0x42bf47 INC	%ECX

0x42bf49 XOR	%EDX,%EDX

0x42bf4b JMP	42b345

Coverage (%)	Name	Source Location	Module
►96.75+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.26+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	accelerate(global_variables&)	accelerate.cpp:70	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1231	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.94 cycles (12.72x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:42
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:42

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:42
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:43

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:48

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 124 bytes (15 double precision FP elements). The binary function is storing 112 bytes (14 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	97
nb uops	96
loop length	367
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	9.50	9.50	9.50	9.50	0.50	1.50	1.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	9.50	9.50	9.50	9.50	0.50	1.50	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.00
Dispatch	9.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	9%

Vector efficiency ratios

INT

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	10%
store	10%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

4% of peak load performance is reached (10.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

ASM code

In the binary file, the address of the function is: 42b2c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x100,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x60(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x64(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x5c(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %ESI,0x54(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42bf13 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xc53>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RDI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R12D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42bf13 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xc53>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,0x5c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x5c(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 42bf47 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xc87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%RAX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0xcc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R9D,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R9D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 42bf13 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xc53>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x54(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x18(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
DIVL 0x5c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV 0x30(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x40(%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVSD 0x39083(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD 0x50(%RBX),%XMM0,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %R11,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x48(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R10D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R10D,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CLTQ																				scal (12.5%)
MOV %R15D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV (%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42b345 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:42
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:42

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:42
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:43

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:48

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 124 bytes (15 double precision FP elements). The binary function is storing 112 bytes (14 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	97
nb uops	96
loop length	367
used x86 registers	16
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.00 cycles
front end	12.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	9.50	9.50	9.50	9.50	0.50	1.50	1.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	9.50	9.50	9.50	9.50	0.50	1.50	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.00
Dispatch	9.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	9%

Vector efficiency ratios

INT

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	10%
store	10%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

4% of peak load performance is reached (10.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (9.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 42b2c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x100,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x60(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x64(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x5c(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %ESI,0x54(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42bf13 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xc53>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RDI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R12D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 42bf13 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xc53>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,0x5c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x5c(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 42bf47 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xc87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%RAX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0xcc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R9D,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R9D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 42bf13 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xc53>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x54(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x18(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
DIVL 0x5c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV 0x30(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x40(%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x38(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVSD 0x39083(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD 0x50(%RBX),%XMM0,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %R11,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x48(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R10D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R10D,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CLTQ																				scal (12.5%)
MOV %R15D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV (%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 42b345 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x85>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Name	Coverage (%)	Time (s)
▼accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.29	1.94
▼Loop 190 - accelerate.cpp:42-53 - exec–	0.00	0.01
○Loop 192 - accelerate.cpp:43-53 - exec	5.28	1.94
○Loop 191 - accelerate.cpp:43-53 - exec	0.00	0.01

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