OV - exec - Function viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: viscosity_kernel(int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, ...	Module: exec	Source: viscosity.cpp:36-64 [...]	Coverage (incl. loops): 2.30% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp: 36 - 64

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

39:       double ugrad = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) - (xvel0(i, j) + xvel0(i + 0, j + 1));

40:       double vgrad = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) - (yvel0(i, j) + yvel0(i + 1, j + 0));

41:       double div = (celldx[i] * (ugrad) + celldy[j] * (vgrad));

42:       double strain2 = 0.5 * (xvel0(i + 0, j + 1) + xvel0(i + 1, j + 1) - xvel0(i, j) - xvel0(i + 1, j + 0)) / celldy[j] +

43:                        0.5 * (yvel0(i + 1, j + 0) + yvel0(i + 1, j + 1) - yvel0(i, j) - yvel0(i + 0, j + 1)) / celldx[i];

44:       double pgradx = (pressure(i + 1, j + 0) - pressure(i - 1, j + 0)) / (celldx[i] + celldx[i + 1]);

45:       double pgrady = (pressure(i + 0, j + 1) - pressure(i + 0, j - 1)) / (celldy[j] + celldy[j + 2]);

46:       double pgradx2 = pgradx * pgradx;

47:       double pgrady2 = pgrady * pgrady;

48:       double limiter = ((0.5 * (ugrad) / celldx[i]) * pgradx2 + (0.5 * (vgrad) / celldy[j]) * pgrady2 + strain2 * pgradx * pgrady) /

49:                        std::fmax(pgradx2 + pgrady2, g_small);

50:       if ((limiter > 0.0) || (div >= 0.0)) {

51:         viscosity(i, j) = 0.0;

52:       } else {

53:         double dirx = 1.0;

54:         if (pgradx < 0.0) dirx = -1.0;

55:         pgradx = dirx * std::fmax(g_small, std::fabs(pgradx));

56:         double diry = 1.0;

57:         if (pgradx < 0.0) diry = -1.0;

58:         pgrady = diry * std::fmax(g_small, std::fabs(pgrady));

59:         double pgrad = std::sqrt(pgradx * pgradx + pgrady * pgrady);

60:         double xgrad = std::fabs(celldx[i] * pgrad / pgradx);

61:         double ygrad = std::fabs(celldy[j] * pgrad / pgrady);

62:         double grad = std::fmin(xgrad, ygrad);

63:         double grad2 = grad * grad;

64:         viscosity(i, j) = 2.0 * density0(i, j) * grad2 * limiter * limiter;

0x4625a0 PUSH	%RBP

0x4625a1 MOV	%RSP,%RBP

0x4625a4 PUSH	%R15

0x4625a6 PUSH	%R14

0x4625a8 PUSH	%R13

0x4625aa PUSH	%R12

0x4625ac PUSH	%RBX

0x4625ad SUB	$0x38,%RSP

0x4625b1 MOV	0x40(%RDI),%EAX

0x4625b4 MOV	0x44(%RDI),%EBX

0x4625b7 MOV	0x38(%RDI),%ECX

0x4625ba MOV	0x3c(%RDI),%EDX

0x4625bd ADD	$0x2,%EBX

0x4625c0 INC	%ECX

0x4625c2 LEA	0x1(%RAX),%R12D

0x4625c6 MOV	%EBX,-0x54(%RBP)

0x4625c9 MOV	%ECX,-0x58(%RBP)

0x4625cc CMP	%EBX,%R12D

0x4625cf JGE	4629b0

0x4625d5 MOV	%EBX,%R14D

0x4625d8 LEA	0x2(%RDX),%R15D

0x4625dc SUB	%R12D,%R14D

0x4625df CMP	%R15D,%ECX

0x4625e2 JGE	4629b0

0x4625e8 MOV	%R15D,%ESI

0x4625eb MOV	%RDI,%RBX

0x4625ee SUB	%ECX,%ESI

0x4625f0 MOV	%ESI,-0x50(%RBP)

0x4625f3 CALL	404630 <omp_get_num_threads@plt>

0x4625f8 MOV	%EAX,%R13D

0x4625fb CALL	404520 <omp_get_thread_num@plt>

0x462600 XOR	%EDX,%EDX

0x462602 MOV	%EAX,%R8D

0x462605 MOV	-0x50(%RBP),%EAX

0x462608 IMUL	%R14D,%EAX

0x46260c DIV	%R13D

0x46260f MOV	%EAX,%R13D

0x462612 CMP	%EDX,%R8D

0x462615 JB	462a10

0x46261b IMUL	%R13D,%R8D

0x46261f LEA	(%R8,%RDX,1),%R9D

0x462623 LEA	(%R13,%R9,1),%R10D

0x462628 MOV	%R10D,-0x5c(%RBP)

0x46262c CMP	%R10D,%R9D

0x46262f JAE	4629b0

0x462635 MOV	%R9D,%EAX

0x462638 XOR	%EDX,%EDX

0x46263a VMOVQ	0x28(%RBX),%XMM21

0x462641 VMOVQ	(%RBX),%XMM7

0x462645 DIVL	-0x50(%RBP)

0x462648 VMOVQ	0x18(%RBX),%XMM1

0x46264d VMOVQ	0x20(%RBX),%XMM0

0x462652 MOV	-0x58(%RBP),%R11D

0x462656 MOV	%R15D,%R10D

0x462659 VMOVQ	0x30(%RBX),%XMM20

0x462660 MOV	0x10(%RBX),%R15

0x462664 VMOVQ	0x8(%RBX),%XMM25

0x46266b VXORPD	%XMM10,%XMM10,%XMM10

0x462670 VMOVQ	0x15b8(%RIP),%XMM13

0x462678 VMOVSD	0x130e(%RIP),%XMM18

0x462682 VMOVQ	0x2ba4(%RIP),%XMM23

0x46268c VMOVSD	0xeea(%RIP),%XMM22

0x462696 VMOVDQA64	%XMM21,%XMM11

0x46269c VMOVDQA64	%XMM7,%XMM26

0x4626a2 VMOVDQA64	%XMM1,%XMM19

0x4626a8 VMOVQ	%R15,%XMM29

0x4626ae VMOVDQA64	%XMM0,%XMM24

0x4626b4 ADD	%R11D,%EDX

0x4626b7 ADD	%R12D,%EAX

0x4626ba SUB	%EDX,%R10D

0x4626bd MOVSXD	%EAX,%RCX

(581) 0x4626c0 CMP	%R10D,%R13D

(581) 0x4626c3 CMOVBE	%R13D,%R10D

(581) 0x4626c7 LEA	(%R9,%R10,1),%EDI

(581) 0x4626cb MOV	%R10D,%R15D

(581) 0x4626ce MOV	%EDI,-0x4c(%RBP)

(581) 0x4626d1 CMP	%EDI,%R9D

(581) 0x4626d4 JAE	4629e0

(581) 0x4626da VMOVQ	%XMM11,%R12

(581) 0x4626df VMOVQ	%XMM20,%R14

(581) 0x4626e5 MOV	%RCX,%R8

(581) 0x4626e8 LEA	0x1(%RCX),%RDI

(581) 0x4626ec MOV	(%R12),%R11

(581) 0x4626f0 MOV	(%R14),%RBX

(581) 0x4626f3 VMOVQ	%XMM25,%R10

(581) 0x4626f9 MOV	0x10(%R12),%R9

(581) 0x4626fe MOV	0x8(%R10),%RAX

(581) 0x462702 MOV	0x10(%R14),%R12

(581) 0x462706 VMOVQ	%XMM26,%RSI

(581) 0x46270c LEA	0x2(%RCX),%R10D

(581) 0x462710 MOV	%RDI,-0x48(%RBP)

(581) 0x462714 MOV	0x8(%RSI),%R13

(581) 0x462718 VMOVQ	%XMM19,%RSI

(581) 0x46271e MOVSXD	%R10D,%R10

(581) 0x462721 MOV	(%RSI),%RSI

(581) 0x462724 LEA	-0x1(%R15),%R15D

(581) 0x462728 MOV	%RCX,-0x40(%RBP)

(581) 0x46272c VMOVSD	0x127c(%RIP),%XMM8

(581) 0x462734 VMOVSD	0xe4c(%RIP),%XMM12

(581) 0x46273c IMUL	%R11,%R8

(581) 0x462740 IMUL	%RBX,%RDI

(581) 0x462744 LEA	(%RAX,%RCX,8),%R14

(581) 0x462748 LEA	(%RAX,%R10,8),%RAX

(581) 0x46274c VMOVQ	%R14,%XMM16

(581) 0x462752 VMOVQ	%RAX,%XMM15

(581) 0x462757 MOVSXD	%EDX,%RAX

(581) 0x46275a LEA	(%R9,%R8,8),%R10

(581) 0x46275e ADD	%R11,%R8

(581) 0x462761 VMOVQ	%XMM19,%R11

(581) 0x462767 LEA	(,%RSI,8),%R14

(581) 0x46276f LEA	(%R9,%R8,8),%R9

(581) 0x462773 LEA	(%R12,%RDI,8),%R8

(581) 0x462777 SUB	%RBX,%RDI

(581) 0x46277a LEA	0x1(%RAX,%R15,1),%R15

(581) 0x46277f LEA	(%R12,%RDI,8),%RDI

(581) 0x462783 MOV	0x10(%R11),%R12

(581) 0x462787 IMUL	%RCX,%RSI

(581) 0x46278b LEA	0x1(%RAX),%RDX

(581) 0x46278f LEA	(%R12,%RSI,8),%RSI

(581) 0x462793 MOV	-0x48(%RBP),%R12

(581) 0x462797 IMUL	%R14,%R12

(581) 0x46279b ADD	0x10(%R11),%R12

(581) 0x46279f LEA	-0x1(%RCX),%R11D

(581) 0x4627a3 MOVSXD	%R11D,%RBX

(581) 0x4627a6 VMOVQ	%XMM24,%R11

(581) 0x4627ac IMUL	%R14,%RBX

(581) 0x4627b0 VMOVQ	%XMM19,%R14

(581) 0x4627b6 ADD	0x10(%R14),%RBX

(581) 0x4627ba MOV	(%R11),%R14

(581) 0x4627bd MOV	0x10(%R11),%R11

(581) 0x4627c1 IMUL	%RCX,%R14

(581) 0x4627c5 MOV	%RBX,-0x38(%RBP)

(581) 0x4627c9 VMOVQ	%XMM29,%RCX

(581) 0x4627cf LEA	(%R11,%R14,8),%R14

(581) 0x4627d3 VMOVQ	%R14,%XMM14

(581) 0x4627d8 VMOVQ	%XMM15,%R14

(581) 0x4627dd VMOVQ	%R15,%XMM15

(581) 0x4627e2 VMOVQ	%XMM16,%R15

(581) 0x4627e8 JMP	462888

0x4627ed NOPL	(%RAX)

  (582) 0x4627f0 VANDPD	%XMM13,%XMM5,%XMM0

  (582) 0x4627f5 VMOVAPD	%XMM18,%XMM4

  (582) 0x4627fb VCOMISD	%XMM5,%XMM10

  (582) 0x4627ff VMAXSD	%XMM12,%XMM0,%XMM1

  (582) 0x462804 JA	4629c0

  (582) 0x46280a MOV	-0x40(%RBP),%R11

  (582) 0x46280e VANDPD	%XMM13,%XMM2,%XMM2

  (582) 0x462813 MOV	0x10(%RCX),%RBX

  (582) 0x462817 IMUL	(%RCX),%R11

  (582) 0x46281b VMAXSD	%XMM12,%XMM2,%XMM9

  (582) 0x462820 VMULSD	%XMM4,%XMM9,%XMM0

  (582) 0x462824 VMULSD	%XMM0,%XMM0,%XMM5

  (582) 0x462828 VFMADD231SD	%XMM1,%XMM1,%XMM5

  (582) 0x46282d VSQRTSD	%XMM5,%XMM5,%XMM5

  (582) 0x462831 VMULSD	%XMM3,%XMM5,%XMM3

  (582) 0x462835 VMULSD	%XMM7,%XMM5,%XMM7

  (582) 0x462839 VDIVSD	%XMM0,%XMM3,%XMM4

  (582) 0x46283d VDIVSD	%XMM1,%XMM7,%XMM1

  (582) 0x462841 VANDPD	%XMM13,%XMM4,%XMM2

  (582) 0x462846 VANDPD	%XMM13,%XMM1,%XMM9

  (582) 0x46284b ADD	%RAX,%R11

  (582) 0x46284e VMINSD	%XMM9,%XMM2,%XMM0

  (582) 0x462853 VMULSD	%XMM6,%XMM0,%XMM6

  (582) 0x462857 VMULSD	%XMM6,%XMM6,%XMM4

  (582) 0x46285b VMOVSD	(%RBX,%R11,8),%XMM5

  (582) 0x462861 VADDSD	%XMM5,%XMM5,%XMM3

  (582) 0x462865 VMULSD	%XMM4,%XMM3,%XMM2

  (582) 0x462869 VMOVQ	%XMM14,%R11

  (582) 0x46286e VMOVQ	%XMM15,%RBX

  (582) 0x462873 VMOVSD	%XMM2,(%R11,%RAX,8)

  (582) 0x462879 MOV	%RDX,%RAX

  (582) 0x46287c CMP	%RBX,%RDX

  (582) 0x46287f JE	4629f0

  (582) 0x462885 INC	%RDX

  (582) 0x462888 MOV	-0x38(%RBP),%RBX

  (582) 0x46288c VMOVSD	0x8(%R9,%RAX,8),%XMM3

  (582) 0x462893 VMOVSD	(%R10,%RAX,8),%XMM2

  (582) 0x462899 VMOVSD	(%R9,%RAX,8),%XMM4

  (582) 0x46289f VMOVSD	0x8(%R8,%RAX,8),%XMM7

  (582) 0x4628a6 VADDSD	%XMM2,%XMM4,%XMM9

  (582) 0x4628aa VADDSD	%XMM3,%XMM4,%XMM28

  (582) 0x4628b0 VMOVSD	0x8(%R10,%RAX,8),%XMM6

  (582) 0x4628b7 VMOVSD	(%RDI,%RAX,8),%XMM27

  (582) 0x4628be VADDSD	%XMM6,%XMM3,%XMM5

  (582) 0x4628c2 VMOVSD	0x8(%RDI,%RAX,8),%XMM3

  (582) 0x4628c8 VSUBSD	%XMM9,%XMM5,%XMM1

  (582) 0x4628cd VADDSD	%XMM7,%XMM3,%XMM4

  (582) 0x4628d1 VADDSD	%XMM27,%XMM3,%XMM9

  (582) 0x4628d7 VADDSD	%XMM6,%XMM2,%XMM6

  (582) 0x4628db VMOVSD	(%R15),%XMM3

  (582) 0x4628e0 VMOVSD	(%R8,%RAX,8),%XMM5

  (582) 0x4628e6 VSUBSD	%XMM6,%XMM28,%XMM30

  (582) 0x4628ec VADDSD	%XMM5,%XMM7,%XMM0

  (582) 0x4628f0 VMOVSD	0x8(%RSI,%RAX,8),%XMM2

  (582) 0x4628f6 VMOVSD	(%R13,%RAX,8),%XMM7

  (582) 0x4628fd VSUBSD	%XMM9,%XMM0,%XMM0

  (582) 0x462902 VADDSD	%XMM5,%XMM27,%XMM5

  (582) 0x462908 VMULSD	%XMM0,%XMM3,%XMM17

  (582) 0x46290e VSUBSD	%XMM5,%XMM4,%XMM4

  (582) 0x462912 VFMADD231SD	%XMM1,%XMM7,%XMM17

  (582) 0x462918 VMULSD	%XMM8,%XMM4,%XMM9

  (582) 0x46291d VMOVSD	(%R12,%RAX,8),%XMM6

  (582) 0x462923 VDIVSD	%XMM7,%XMM9,%XMM5

  (582) 0x462927 VMULSD	%XMM8,%XMM30,%XMM31

  (582) 0x46292d VSUBSD	-0x8(%RSI,%RAX,8),%XMM2,%XMM9

  (582) 0x462933 VDIVSD	%XMM3,%XMM31,%XMM21

  (582) 0x462939 VSUBSD	(%RBX,%RAX,8),%XMM6,%XMM2

  (582) 0x46293e VADDSD	%XMM21,%XMM5,%XMM4

  (582) 0x462944 VMULSD	%XMM8,%XMM1,%XMM1

  (582) 0x462949 VADDSD	0x8(%R13,%RAX,8),%XMM7,%XMM5

  (582) 0x462950 VDIVSD	%XMM7,%XMM1,%XMM1

  (582) 0x462954 VDIVSD	%XMM5,%XMM9,%XMM5

  (582) 0x462958 VMULSD	%XMM8,%XMM0,%XMM0

  (582) 0x46295d VADDSD	(%R14),%XMM3,%XMM9

  (582) 0x462962 VDIVSD	%XMM3,%XMM0,%XMM0

  (582) 0x462966 VDIVSD	%XMM9,%XMM2,%XMM2

  (582) 0x46296b VMULSD	%XMM5,%XMM5,%XMM9

  (582) 0x46296f VMULSD	%XMM2,%XMM2,%XMM6

  (582) 0x462973 VMULSD	%XMM6,%XMM0,%XMM0

  (582) 0x462977 VFMADD231SD	%XMM9,%XMM1,%XMM0

  (582) 0x46297c VMULSD	%XMM5,%XMM2,%XMM1

  (582) 0x462980 VCOMISD	%XMM10,%XMM17

  (582) 0x462986 VFMADD132SD	%XMM4,%XMM0,%XMM1

  (582) 0x46298b VADDSD	%XMM9,%XMM6,%XMM4

  (582) 0x462990 VMAXSD	%XMM12,%XMM4,%XMM9

  (582) 0x462995 VDIVSD	%XMM9,%XMM1,%XMM6

  (582) 0x46299a JAE	4629a7

  (582) 0x46299c VCOMISD	%XMM10,%XMM6

  (582) 0x4629a1 JBE	4627f0

  (582) 0x4629a7 VXORPD	%XMM2,%XMM2,%XMM2

  (582) 0x4629ab JMP	462869

0x4629b0 ADD	$0x38,%RSP

0x4629b4 POP	%RBX

0x4629b5 POP	%R12

0x4629b7 POP	%R13

0x4629b9 POP	%R14

0x4629bb POP	%R15

0x4629bd POP	%RBP

0x4629be RET

0x4629bf NOP

  (582) 0x4629c0 VXORPD	%XMM23,%XMM1,%XMM5

  (582) 0x4629c6 VCOMISD	%XMM10,%XMM1

  (582) 0x4629cb VMOVAPD	%XMM5,%XMM1

  (582) 0x4629cf JBE	462a1a

  (582) 0x4629d1 VMOVAPD	%XMM22,%XMM4

  (582) 0x4629d7 JMP	46280a

0x4629dc NOPL	(%RAX)

(581) 0x4629e0 MOV	%R9D,-0x4c(%RBP)

(581) 0x4629e4 LEA	0x1(%RCX),%R9

(581) 0x4629e8 MOV	%R9,-0x48(%RBP)

(581) 0x4629ec NOPL	(%RAX)

(581) 0x4629f0 MOV	-0x48(%RBP),%RCX

(581) 0x4629f4 CMP	%ECX,-0x54(%RBP)

(581) 0x4629f7 JLE	4629b0

(581) 0x4629f9 MOV	-0x5c(%RBP),%R13D

(581) 0x4629fd MOV	-0x4c(%RBP),%R9D

(581) 0x462a01 MOV	-0x50(%RBP),%R10D

(581) 0x462a05 MOV	-0x58(%RBP),%EDX

(581) 0x462a08 SUB	%R9D,%R13D

(581) 0x462a0b JMP	4626c0

0x462a10 INC	%R13D

0x462a13 XOR	%EDX,%EDX

0x462a15 JMP	46261b

  (582) 0x462a1a VMOVSD	0xf6e(%RIP),%XMM4

  (582) 0x462a22 JMP	46280a

0x462a27 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.88+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.29+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	viscosity(global_variables&)	viscosity.cpp:76	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:64	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:60	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 3.00 cycles (4.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.77 cycles (15.52x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.75 cycles (1.12x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.50 cycles (1.14x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:41

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	86
nb uops	86
loop length	330
used x86 registers	16
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.75
Dispatch	6.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	35%

Vector efficiency ratios

INT

all	10%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (9.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4625a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x40(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x44(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x38(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x3c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EBX,-0x54(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EBX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4629b0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EBX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R12D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4629b0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ECX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x50(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 462a10 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x470>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R13D,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R13,%R9,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R10D,-0x5c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4629b0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVQ 0x28(%RBX),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ (%RBX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL -0x50(%RBP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x18(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV -0x58(%RBP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %R15D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ 0x30(%RBX),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x10(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
VMOVQ 0x8(%RBX),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ 0x15b8(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0x130e(%RIP),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x2ba4(%RIP),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0xeea(%RIP),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVDQA64 %XMM21,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA64 %XMM7,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA64 %XMM1,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %R15,%XMM29	1	0	0	1	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVDQA64 %XMM0,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 46261b <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x7b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	viscosity.cpp:36-64
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:36-64

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 3.00 cycles (4.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.50 cycles (1.14x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:38
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/viscosity.cpp:41

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	86
nb uops	86
loop length	330
used x86 registers	16
used mmx registers	0
used xmm registers	16
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.75
Dispatch	6.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	11%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	26%

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	35%

Vector efficiency ratios

INT

all	10%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	16%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	11%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	8%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (9.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4625a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x40(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x44(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x38(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x3c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EBX,-0x54(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EBX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4629b0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EBX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R12D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4629b0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ECX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x50(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 462a10 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x470>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R13D,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R13,%R9,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R10D,-0x5c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4629b0 <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x410>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVQ 0x28(%RBX),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ (%RBX),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL -0x50(%RBP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x18(%RBX),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%RBX),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV -0x58(%RBP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %R15D,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ 0x30(%RBX),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x10(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
VMOVQ 0x8(%RBX),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VXORPD %XMM10,%XMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ 0x15b8(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0x130e(%RIP),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x2ba4(%RIP),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0xeea(%RIP),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVDQA64 %XMM21,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA64 %XMM7,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA64 %XMM1,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVQ %R15,%XMM29	1	0	0	1	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVDQA64 %XMM0,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 46261b <_Z16viscosity_kerneliiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_._omp_fn.0+0x7b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼viscosity_kernel(int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	2.30	0.85
▼Loop 581 - viscosity.cpp:38-64 - exec–	0.00	0.01
○Loop 582 - viscosity.cpp:39-64 - exec	2.30	0.84

Report Configuration

Code clean check

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Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code