OV - exec - Function revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: revert_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, cl ...	Module: exec	Source: revert.cpp:34-38 [...]	Coverage (incl. loops): 2.64% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp: 34 - 38

--------------------------------------------------------------------------------

34: #pragma omp parallel for simd collapse(2)

35:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

36:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

37:       density1(i, j) = density0(i, j);

38:       energy1(i, j) = energy0(i, j);

0x448f90 PUSH	%RBP

0x448f91 MOV	%RSP,%RBP

0x448f94 PUSH	%R15

0x448f96 PUSH	%R14

0x448f98 PUSH	%R13

0x448f9a PUSH	%R12

0x448f9c PUSH	%RBX

0x448f9d AND	$-0x40,%RSP

0x448fa1 SUB	$0x40,%RSP

0x448fa5 MOV	0x28(%RDI),%EAX

0x448fa8 MOV	0x2c(%RDI),%ESI

0x448fab MOV	0x20(%RDI),%ECX

0x448fae MOV	0x24(%RDI),%EDX

0x448fb1 MOV	%RDI,0x38(%RSP)

0x448fb6 ADD	$0x2,%ESI

0x448fb9 INC	%ECX

0x448fbb LEA	0x1(%RAX),%EBX

0x448fbe MOV	%ESI,0x14(%RSP)

0x448fc2 MOV	%ECX,0x10(%RSP)

0x448fc6 CMP	%ESI,%EBX

0x448fc8 JGE	4494c3

0x448fce MOV	%ESI,%R14D

0x448fd1 LEA	0x2(%RDX),%R15D

0x448fd5 SUB	%EBX,%R14D

0x448fd8 CMP	%R15D,%ECX

0x448fdb JGE	4494c3

0x448fe1 MOV	%R15D,%R13D

0x448fe4 SUB	%ECX,%R13D

0x448fe7 IMUL	%R13D,%R14D

0x448feb MOV	%R13D,0xc(%RSP)

0x448ff0 CALL	404630 <omp_get_num_threads@plt>

0x448ff5 MOV	%EAX,%R12D

0x448ff8 CALL	404520 <omp_get_thread_num@plt>

0x448ffd XOR	%EDX,%EDX

0x448fff MOV	0x38(%RSP),%RDI

0x449004 MOV	%EAX,%ECX

0x449006 MOV	%R14D,%EAX

0x449009 DIV	%R12D

0x44900c CMP	%EDX,%ECX

0x44900e MOV	%EAX,%R9D

0x449011 JB	4494eb

0x449017 IMUL	%R9D,%ECX

0x44901b ADD	%EDX,%ECX

0x44901d LEA	(%R9,%RCX,1),%R8D

0x449021 MOV	%R8D,0x8(%RSP)

0x449026 CMP	%R8D,%ECX

0x449029 JAE	4494c3

0x44902f MOV	%ECX,%EAX

0x449031 XOR	%EDX,%EDX

0x449033 MOV	0x10(%RSP),%R10D

0x449038 VMOVQ	(%RDI),%XMM3

0x44903c DIVL	0xc(%RSP)

0x449040 VMOVQ	0x8(%RDI),%XMM4

0x449045 VMOVQ	0x10(%RDI),%XMM2

0x44904a VMOVQ	0x18(%RDI),%XMM1

0x44904f ADD	%R10D,%EDX

0x449052 ADD	%EBX,%EAX

0x449054 SUB	%EDX,%R15D

0x449057 MOV	%EDX,0x38(%RSP)

0x44905b MOVSXD	%EAX,%R8

0x44905e MOV	%R9D,%EDX

0x449061 MOV	%R15D,%R12D

0x449064 NOPW	%CS:(%RAX,%RAX,1)

0x44906f NOP

(337) 0x449070 CMP	%R12D,%EDX

(337) 0x449073 CMOVA	%R12D,%EDX

(337) 0x449077 LEA	(%RCX,%RDX,1),%R12D

(337) 0x44907b CMP	%R12D,%ECX

(337) 0x44907e JAE	449495

(337) 0x449084 VMOVQ	%XMM3,%R11

(337) 0x449089 VMOVQ	%XMM2,%R14

(337) 0x44908e LEA	-0x1(%RDX),%EDI

(337) 0x449091 VMOVQ	%XMM4,%RSI

(337) 0x449096 VMOVQ	%XMM1,%R9

(337) 0x44909b MOV	(%R11),%RBX

(337) 0x44909e VMOVQ	0x10(%R11),%XMM5

(337) 0x4490a4 MOV	0x10(%RSI),%R13

(337) 0x4490a8 MOV	(%R14),%R11

(337) 0x4490ab MOV	(%RSI),%RSI

(337) 0x4490ae MOV	0x10(%R14),%R15

(337) 0x4490b2 MOV	0x10(%R9),%R14

(337) 0x4490b6 MOV	(%R9),%R9

(337) 0x4490b9 IMUL	%R8,%RBX

(337) 0x4490bd IMUL	%R8,%RSI

(337) 0x4490c1 IMUL	%R8,%R11

(337) 0x4490c5 IMUL	%R8,%R9

(337) 0x4490c9 MOV	%RBX,0x18(%RSP)

(337) 0x4490ce MOV	%RSI,0x20(%RSP)

(337) 0x4490d3 MOV	%R11,0x28(%RSP)

(337) 0x4490d8 MOV	%R9,0x30(%RSP)

(337) 0x4490dd CMP	$0x6,%EDI

(337) 0x4490e0 JBE	4494e0

(337) 0x4490e6 MOVSXD	0x38(%RSP),%RAX

(337) 0x4490eb LEA	(%RBX,%RAX,1),%R10

(337) 0x4490ef LEA	(%RSI,%RAX,1),%RSI

(337) 0x4490f3 LEA	(%R11,%RAX,1),%R11

(337) 0x4490f7 ADD	%R9,%RAX

(337) 0x4490fa MOV	%EDX,%R9D

(337) 0x4490fd VMOVQ	%XMM5,%RBX

(337) 0x449102 LEA	(%R15,%R11,8),%R11

(337) 0x449106 SHR	$0x3,%R9D

(337) 0x44910a SAL	$0x6,%R9

(337) 0x44910e LEA	-0x40(%R9),%RDI

(337) 0x449112 LEA	(%RBX,%R10,8),%R10

(337) 0x449116 LEA	(%R13,%RSI,8),%RBX

(337) 0x44911b LEA	(%R14,%RAX,8),%RSI

(337) 0x44911f SHR	$0x6,%RDI

(337) 0x449123 INC	%RDI

(337) 0x449126 XOR	%EAX,%EAX

(337) 0x449128 AND	$0x7,%EDI

(337) 0x44912b JE	449247

(337) 0x449131 CMP	$0x1,%RDI

(337) 0x449135 JE	44921e

(337) 0x44913b CMP	$0x2,%RDI

(337) 0x44913f JE	4491fe

(337) 0x449145 CMP	$0x3,%RDI

(337) 0x449149 JE	4491de

(337) 0x44914f CMP	$0x4,%RDI

(337) 0x449153 JE	4491be

(337) 0x449155 CMP	$0x5,%RDI

(337) 0x449159 JE	44919e

(337) 0x44915b CMP	$0x6,%RDI

(337) 0x44915f JE	44917e

(337) 0x449161 VMOVUPD	(%R10),%ZMM12

(337) 0x449167 MOV	$0x40,%EAX

(337) 0x44916c VMOVUPD	%ZMM12,(%RBX)

(337) 0x449172 VMOVUPD	(%R11),%ZMM0

(337) 0x449178 VMOVUPD	%ZMM0,(%RSI)

(337) 0x44917e VMOVUPD	(%R10,%RAX,1),%ZMM6

(337) 0x449185 VMOVUPD	%ZMM6,(%RBX,%RAX,1)

(337) 0x44918c VMOVUPD	(%R11,%RAX,1),%ZMM7

(337) 0x449193 VMOVUPD	%ZMM7,(%RSI,%RAX,1)

(337) 0x44919a ADD	$0x40,%RAX

(337) 0x44919e VMOVUPD	(%R10,%RAX,1),%ZMM8

(337) 0x4491a5 VMOVUPD	%ZMM8,(%RBX,%RAX,1)

(337) 0x4491ac VMOVUPD	(%R11,%RAX,1),%ZMM9

(337) 0x4491b3 VMOVUPD	%ZMM9,(%RSI,%RAX,1)

(337) 0x4491ba ADD	$0x40,%RAX

(337) 0x4491be VMOVUPD	(%R10,%RAX,1),%ZMM10

(337) 0x4491c5 VMOVUPD	%ZMM10,(%RBX,%RAX,1)

(337) 0x4491cc VMOVUPD	(%R11,%RAX,1),%ZMM11

(337) 0x4491d3 VMOVUPD	%ZMM11,(%RSI,%RAX,1)

(337) 0x4491da ADD	$0x40,%RAX

(337) 0x4491de VMOVUPD	(%R10,%RAX,1),%ZMM13

(337) 0x4491e5 VMOVUPD	%ZMM13,(%RBX,%RAX,1)

(337) 0x4491ec VMOVUPD	(%R11,%RAX,1),%ZMM14

(337) 0x4491f3 VMOVUPD	%ZMM14,(%RSI,%RAX,1)

(337) 0x4491fa ADD	$0x40,%RAX

(337) 0x4491fe VMOVUPD	(%R10,%RAX,1),%ZMM15

(337) 0x449205 VMOVUPD	%ZMM15,(%RBX,%RAX,1)

(337) 0x44920c VMOVUPD	(%R11,%RAX,1),%ZMM12

(337) 0x449213 VMOVUPD	%ZMM12,(%RSI,%RAX,1)

(337) 0x44921a ADD	$0x40,%RAX

(337) 0x44921e VMOVUPD	(%R10,%RAX,1),%ZMM0

(337) 0x449225 VMOVUPD	%ZMM0,(%RBX,%RAX,1)

(337) 0x44922c VMOVUPD	(%R11,%RAX,1),%ZMM6

(337) 0x449233 VMOVUPD	%ZMM6,(%RSI,%RAX,1)

(337) 0x44923a ADD	$0x40,%RAX

(337) 0x44923e CMP	%R9,%RAX

(337) 0x449241 JE	449352

  (338) 0x449247 VMOVUPD	(%R10,%RAX,1),%ZMM7

  (338) 0x44924e VMOVUPD	%ZMM7,(%RBX,%RAX,1)

  (338) 0x449255 VMOVUPD	(%R11,%RAX,1),%ZMM8

  (338) 0x44925c VMOVUPD	%ZMM8,(%RSI,%RAX,1)

  (338) 0x449263 VMOVUPD	0x40(%R10,%RAX,1),%ZMM9

  (338) 0x44926b VMOVUPD	%ZMM9,0x40(%RBX,%RAX,1)

  (338) 0x449273 VMOVUPD	0x40(%R11,%RAX,1),%ZMM10

  (338) 0x44927b VMOVUPD	%ZMM10,0x40(%RSI,%RAX,1)

  (338) 0x449283 VMOVUPD	0x80(%R10,%RAX,1),%ZMM11

  (338) 0x44928b VMOVUPD	%ZMM11,0x80(%RBX,%RAX,1)

  (338) 0x449293 VMOVUPD	0x80(%R11,%RAX,1),%ZMM13

  (338) 0x44929b VMOVUPD	%ZMM13,0x80(%RSI,%RAX,1)

  (338) 0x4492a3 VMOVUPD	0xc0(%R10,%RAX,1),%ZMM14

  (338) 0x4492ab VMOVUPD	%ZMM14,0xc0(%RBX,%RAX,1)

  (338) 0x4492b3 VMOVUPD	0xc0(%R11,%RAX,1),%ZMM15

  (338) 0x4492bb VMOVUPD	%ZMM15,0xc0(%RSI,%RAX,1)

  (338) 0x4492c3 VMOVUPD	0x100(%R10,%RAX,1),%ZMM12

  (338) 0x4492cb VMOVUPD	%ZMM12,0x100(%RBX,%RAX,1)

  (338) 0x4492d3 VMOVUPD	0x100(%R11,%RAX,1),%ZMM0

  (338) 0x4492db VMOVUPD	%ZMM0,0x100(%RSI,%RAX,1)

  (338) 0x4492e3 VMOVUPD	0x140(%R10,%RAX,1),%ZMM6

  (338) 0x4492eb VMOVUPD	%ZMM6,0x140(%RBX,%RAX,1)

  (338) 0x4492f3 VMOVUPD	0x140(%R11,%RAX,1),%ZMM7

  (338) 0x4492fb VMOVUPD	%ZMM7,0x140(%RSI,%RAX,1)

  (338) 0x449303 VMOVUPD	0x180(%R10,%RAX,1),%ZMM8

  (338) 0x44930b VMOVUPD	%ZMM8,0x180(%RBX,%RAX,1)

  (338) 0x449313 VMOVUPD	0x180(%R11,%RAX,1),%ZMM9

  (338) 0x44931b VMOVUPD	%ZMM9,0x180(%RSI,%RAX,1)

  (338) 0x449323 VMOVUPD	0x1c0(%R10,%RAX,1),%ZMM10

  (338) 0x44932b VMOVUPD	%ZMM10,0x1c0(%RBX,%RAX,1)

  (338) 0x449333 VMOVUPD	0x1c0(%R11,%RAX,1),%ZMM11

  (338) 0x44933b VMOVUPD	%ZMM11,0x1c0(%RSI,%RAX,1)

  (338) 0x449343 ADD	$0x200,%RAX

  (338) 0x449349 CMP	%R9,%RAX

  (338) 0x44934c JNE	449247

(337) 0x449352 MOV	0x38(%RSP),%R10D

(337) 0x449357 MOV	%EDX,%EAX

(337) 0x449359 AND	$-0x8,%EAX

(337) 0x44935c ADD	%EAX,%ECX

(337) 0x44935e LEA	(%RAX,%R10,1),%EDI

(337) 0x449362 TEST	$0x7,%DL

(337) 0x449365 JE	449492

(337) 0x44936b SUB	%EAX,%EDX

(337) 0x44936d LEA	-0x1(%RDX),%EBX

(337) 0x449370 CMP	$0x2,%EBX

(337) 0x449373 JBE	4493d9

(337) 0x449375 MOVSXD	0x38(%RSP),%R11

(337) 0x44937a MOV	0x18(%RSP),%RSI

(337) 0x44937f MOV	0x20(%RSP),%RBX

(337) 0x449384 VMOVQ	%XMM5,%R10

(337) 0x449389 LEA	(%RSI,%R11,1),%R9

(337) 0x44938d LEA	(%RBX,%R11,1),%RSI

(337) 0x449391 MOV	0x30(%RSP),%RBX

(337) 0x449396 ADD	%RAX,%R9

(337) 0x449399 ADD	%RAX,%RSI

(337) 0x44939c VMOVUPD	(%R10,%R9,8),%YMM13

(337) 0x4493a2 MOV	0x28(%RSP),%R9

(337) 0x4493a7 LEA	(%R9,%R11,1),%R10

(337) 0x4493ab ADD	%RBX,%R11

(337) 0x4493ae ADD	%RAX,%R10

(337) 0x4493b1 VMOVUPD	%YMM13,(%R13,%RSI,8)

(337) 0x4493b8 ADD	%RAX,%R11

(337) 0x4493bb MOV	%EDX,%EAX

(337) 0x4493bd VMOVUPD	(%R15,%R10,8),%YMM14

(337) 0x4493c3 AND	$-0x4,%EAX

(337) 0x4493c6 ADD	%EAX,%EDI

(337) 0x4493c8 ADD	%EAX,%ECX

(337) 0x4493ca AND	$0x3,%EDX

(337) 0x4493cd VMOVUPD	%YMM14,(%R14,%R11,8)

(337) 0x4493d3 JE	449492

(337) 0x4493d9 MOV	0x18(%RSP),%RBX

(337) 0x4493de MOV	0x20(%RSP),%RSI

(337) 0x4493e3 MOVSXD	%EDI,%R9

(337) 0x4493e6 VMOVQ	%XMM5,%R11

(337) 0x4493eb LEA	(%RSI,%R9,1),%R10

(337) 0x4493ef LEA	(%RBX,%R9,1),%RDX

(337) 0x4493f3 VMOVSD	(%R11,%RDX,8),%XMM15

(337) 0x4493f9 MOV	0x30(%RSP),%R11

(337) 0x4493fe VMOVSD	%XMM15,(%R13,%R10,8)

(337) 0x449405 MOV	0x28(%RSP),%R10

(337) 0x44940a LEA	(%R10,%R9,1),%RAX

(337) 0x44940e ADD	%R11,%R9

(337) 0x449411 VMOVSD	(%R15,%RAX,8),%XMM12

(337) 0x449417 VMOVSD	%XMM12,(%R14,%R9,8)

(337) 0x44941d LEA	0x1(%RCX),%R9D

(337) 0x449421 CMP	%R12D,%R9D

(337) 0x449424 JAE	449492

(337) 0x449426 LEA	0x1(%RDI),%EAX

(337) 0x449429 VMOVQ	%XMM5,%R9

(337) 0x44942e ADD	$0x2,%ECX

(337) 0x449431 CLTQ

(337) 0x449433 LEA	(%RBX,%RAX,1),%RDX

(337) 0x449437 VMOVSD	(%R9,%RDX,8),%XMM0

(337) 0x44943d LEA	(%RSI,%RAX,1),%RDX

(337) 0x449441 LEA	(%R10,%RAX,1),%R9

(337) 0x449445 ADD	%R11,%RAX

(337) 0x449448 VMOVSD	%XMM0,(%R13,%RDX,8)

(337) 0x44944f MOV	%R11,%RDX

(337) 0x449452 VMOVSD	(%R15,%R9,8),%XMM6

(337) 0x449458 VMOVSD	%XMM6,(%R14,%RAX,8)

(337) 0x44945e CMP	%R12D,%ECX

(337) 0x449461 JAE	449492

(337) 0x449463 ADD	$0x2,%EDI

(337) 0x449466 MOVSXD	%EDI,%RCX

(337) 0x449469 VMOVQ	%XMM5,%RDI

(337) 0x44946e ADD	%RCX,%RBX

(337) 0x449471 ADD	%RCX,%RSI

(337) 0x449474 ADD	%RCX,%R10

(337) 0x449477 ADD	%RCX,%RDX

(337) 0x44947a VMOVSD	(%RDI,%RBX,8),%XMM5

(337) 0x44947f VMOVSD	%XMM5,(%R13,%RSI,8)

(337) 0x449486 VMOVSD	(%R15,%R10,8),%XMM7

(337) 0x44948c VMOVSD	%XMM7,(%R14,%RDX,8)

(337) 0x449492 MOV	%R12D,%ECX

(337) 0x449495 INC	%R8

(337) 0x449498 CMP	%R8D,0x14(%RSP)

(337) 0x44949d JLE	4494c0

(337) 0x44949f MOV	0x8(%RSP),%EDX

(337) 0x4494a3 MOV	0x10(%RSP),%R13D

(337) 0x4494a8 MOV	0xc(%RSP),%R12D

(337) 0x4494ad SUB	%ECX,%EDX

(337) 0x4494af MOV	%R13D,0x38(%RSP)

(337) 0x4494b4 JMP	449070

0x4494b9 NOPL	(%RAX)

0x4494c0 VZEROUPPER

0x4494c3 LEA	-0x28(%RBP),%RSP

0x4494c7 POP	%RBX

0x4494c8 POP	%R12

0x4494ca POP	%R13

0x4494cc POP	%R14

0x4494ce POP	%R15

0x4494d0 POP	%RBP

0x4494d1 RET

0x4494d2 NOPW	%CS:(%RAX,%RAX,1)

0x4494dd NOPL	(%RAX)

(337) 0x4494e0 MOV	0x38(%RSP),%EDI

(337) 0x4494e4 XOR	%EAX,%EAX

(337) 0x4494e6 JMP	44936b

0x4494eb INC	%R9D

0x4494ee XOR	%EDX,%EDX

0x4494f0 JMP	449017

0x4494f5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.70+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.24+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	revert(global_variables&)	revert.cpp:48	exec
○	PdV(global_variables&, bool)	PdV.cpp:131	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:64	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	revert.cpp:34-38
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:34-38

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.75 cycles (1.23x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:37

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	80
nb uops	78
loop length	284
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 448f90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x2,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ESI,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4494c3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4494c3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 4494eb <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x55b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R8D,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4494c3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0xc(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%RDI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 449017 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	revert.cpp:34-38
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:34-38

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:36
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/revert.cpp:37

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	80
nb uops	78
loop length	284
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 448f90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x2,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ESI,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4494c3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4494c3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 4494eb <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x55b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R8D,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4494c3 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0xc(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%RDI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 449017 <_Z13revert_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼revert_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	2.64	0.97
▼Loop 337 - revert.cpp:36-38 - exec–	0.00	0.01
○Loop 338 - revert.cpp:37-38 - exec	2.64	0.97

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Matching between your function (in the source code) and the binary function

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Cycles and memory resources usage

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