OV - exec - Function reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ...	Module: exec	Source: reset_field.cpp:34-38 [...]	Coverage (incl. loops): 2.62% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp: 34 - 38

--------------------------------------------------------------------------------

34: #pragma omp parallel for simd collapse(2)

35:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

36:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

37:       density0(i, j) = density1(i, j);

38:       energy0(i, j) = energy1(i, j);

0x4487f0 PUSH	%RBP

0x4487f1 MOV	%RSP,%RBP

0x4487f4 PUSH	%R15

0x4487f6 PUSH	%R14

0x4487f8 PUSH	%R13

0x4487fa PUSH	%R12

0x4487fc PUSH	%RBX

0x4487fd AND	$-0x40,%RSP

0x448801 SUB	$0x40,%RSP

0x448805 MOV	0x28(%RDI),%EAX

0x448808 MOV	0x2c(%RDI),%ESI

0x44880b MOV	0x20(%RDI),%ECX

0x44880e MOV	0x24(%RDI),%EDX

0x448811 MOV	%RDI,0x38(%RSP)

0x448816 ADD	$0x2,%ESI

0x448819 INC	%ECX

0x44881b LEA	0x1(%RAX),%EBX

0x44881e MOV	%ESI,0x14(%RSP)

0x448822 MOV	%ECX,0x10(%RSP)

0x448826 CMP	%ESI,%EBX

0x448828 JGE	448d23

0x44882e MOV	%ESI,%R14D

0x448831 LEA	0x2(%RDX),%R15D

0x448835 SUB	%EBX,%R14D

0x448838 CMP	%R15D,%ECX

0x44883b JGE	448d23

0x448841 MOV	%R15D,%R13D

0x448844 SUB	%ECX,%R13D

0x448847 IMUL	%R13D,%R14D

0x44884b MOV	%R13D,0xc(%RSP)

0x448850 CALL	404630 <omp_get_num_threads@plt>

0x448855 MOV	%EAX,%R12D

0x448858 CALL	404520 <omp_get_thread_num@plt>

0x44885d XOR	%EDX,%EDX

0x44885f MOV	0x38(%RSP),%RDI

0x448864 MOV	%EAX,%ECX

0x448866 MOV	%R14D,%EAX

0x448869 DIV	%R12D

0x44886c CMP	%EDX,%ECX

0x44886e MOV	%EAX,%R9D

0x448871 JB	448d4b

0x448877 IMUL	%R9D,%ECX

0x44887b ADD	%EDX,%ECX

0x44887d LEA	(%R9,%RCX,1),%R8D

0x448881 MOV	%R8D,0x8(%RSP)

0x448886 CMP	%R8D,%ECX

0x448889 JAE	448d23

0x44888f MOV	%ECX,%EAX

0x448891 XOR	%EDX,%EDX

0x448893 MOV	0x10(%RSP),%R10D

0x448898 VMOVQ	0x8(%RDI),%XMM3

0x44889d DIVL	0xc(%RSP)

0x4488a1 VMOVQ	(%RDI),%XMM4

0x4488a5 VMOVQ	0x18(%RDI),%XMM2

0x4488aa VMOVQ	0x10(%RDI),%XMM1

0x4488af ADD	%R10D,%EDX

0x4488b2 ADD	%EBX,%EAX

0x4488b4 SUB	%EDX,%R15D

0x4488b7 MOV	%EDX,0x38(%RSP)

0x4488bb MOVSXD	%EAX,%R8

0x4488be MOV	%R9D,%EDX

0x4488c1 MOV	%R15D,%R12D

0x4488c4 NOPW	%CS:(%RAX,%RAX,1)

0x4488cf NOP

(334) 0x4488d0 CMP	%R12D,%EDX

(334) 0x4488d3 CMOVA	%R12D,%EDX

(334) 0x4488d7 LEA	(%RCX,%RDX,1),%R12D

(334) 0x4488db CMP	%R12D,%ECX

(334) 0x4488de JAE	448cf5

(334) 0x4488e4 VMOVQ	%XMM3,%R11

(334) 0x4488e9 VMOVQ	%XMM2,%R14

(334) 0x4488ee LEA	-0x1(%RDX),%EDI

(334) 0x4488f1 VMOVQ	%XMM4,%RSI

(334) 0x4488f6 VMOVQ	%XMM1,%R9

(334) 0x4488fb MOV	(%R11),%RBX

(334) 0x4488fe VMOVQ	0x10(%R11),%XMM5

(334) 0x448904 MOV	0x10(%RSI),%R13

(334) 0x448908 MOV	(%R14),%R11

(334) 0x44890b MOV	(%RSI),%RSI

(334) 0x44890e MOV	0x10(%R14),%R15

(334) 0x448912 MOV	0x10(%R9),%R14

(334) 0x448916 MOV	(%R9),%R9

(334) 0x448919 IMUL	%R8,%RBX

(334) 0x44891d IMUL	%R8,%RSI

(334) 0x448921 IMUL	%R8,%R11

(334) 0x448925 IMUL	%R8,%R9

(334) 0x448929 MOV	%RBX,0x18(%RSP)

(334) 0x44892e MOV	%RSI,0x20(%RSP)

(334) 0x448933 MOV	%R11,0x28(%RSP)

(334) 0x448938 MOV	%R9,0x30(%RSP)

(334) 0x44893d CMP	$0x6,%EDI

(334) 0x448940 JBE	448d40

(334) 0x448946 MOVSXD	0x38(%RSP),%RAX

(334) 0x44894b LEA	(%RBX,%RAX,1),%R10

(334) 0x44894f LEA	(%RSI,%RAX,1),%RSI

(334) 0x448953 LEA	(%R11,%RAX,1),%R11

(334) 0x448957 ADD	%R9,%RAX

(334) 0x44895a MOV	%EDX,%R9D

(334) 0x44895d VMOVQ	%XMM5,%RBX

(334) 0x448962 LEA	(%R15,%R11,8),%R11

(334) 0x448966 SHR	$0x3,%R9D

(334) 0x44896a SAL	$0x6,%R9

(334) 0x44896e LEA	-0x40(%R9),%RDI

(334) 0x448972 LEA	(%RBX,%R10,8),%R10

(334) 0x448976 LEA	(%R13,%RSI,8),%RBX

(334) 0x44897b LEA	(%R14,%RAX,8),%RSI

(334) 0x44897f SHR	$0x6,%RDI

(334) 0x448983 INC	%RDI

(334) 0x448986 XOR	%EAX,%EAX

(334) 0x448988 AND	$0x7,%EDI

(334) 0x44898b JE	448aa7

(334) 0x448991 CMP	$0x1,%RDI

(334) 0x448995 JE	448a7e

(334) 0x44899b CMP	$0x2,%RDI

(334) 0x44899f JE	448a5e

(334) 0x4489a5 CMP	$0x3,%RDI

(334) 0x4489a9 JE	448a3e

(334) 0x4489af CMP	$0x4,%RDI

(334) 0x4489b3 JE	448a1e

(334) 0x4489b5 CMP	$0x5,%RDI

(334) 0x4489b9 JE	4489fe

(334) 0x4489bb CMP	$0x6,%RDI

(334) 0x4489bf JE	4489de

(334) 0x4489c1 VMOVUPD	(%R10),%ZMM12

(334) 0x4489c7 MOV	$0x40,%EAX

(334) 0x4489cc VMOVUPD	%ZMM12,(%RBX)

(334) 0x4489d2 VMOVUPD	(%R11),%ZMM0

(334) 0x4489d8 VMOVUPD	%ZMM0,(%RSI)

(334) 0x4489de VMOVUPD	(%R10,%RAX,1),%ZMM6

(334) 0x4489e5 VMOVUPD	%ZMM6,(%RBX,%RAX,1)

(334) 0x4489ec VMOVUPD	(%R11,%RAX,1),%ZMM7

(334) 0x4489f3 VMOVUPD	%ZMM7,(%RSI,%RAX,1)

(334) 0x4489fa ADD	$0x40,%RAX

(334) 0x4489fe VMOVUPD	(%R10,%RAX,1),%ZMM8

(334) 0x448a05 VMOVUPD	%ZMM8,(%RBX,%RAX,1)

(334) 0x448a0c VMOVUPD	(%R11,%RAX,1),%ZMM9

(334) 0x448a13 VMOVUPD	%ZMM9,(%RSI,%RAX,1)

(334) 0x448a1a ADD	$0x40,%RAX

(334) 0x448a1e VMOVUPD	(%R10,%RAX,1),%ZMM10

(334) 0x448a25 VMOVUPD	%ZMM10,(%RBX,%RAX,1)

(334) 0x448a2c VMOVUPD	(%R11,%RAX,1),%ZMM11

(334) 0x448a33 VMOVUPD	%ZMM11,(%RSI,%RAX,1)

(334) 0x448a3a ADD	$0x40,%RAX

(334) 0x448a3e VMOVUPD	(%R10,%RAX,1),%ZMM13

(334) 0x448a45 VMOVUPD	%ZMM13,(%RBX,%RAX,1)

(334) 0x448a4c VMOVUPD	(%R11,%RAX,1),%ZMM14

(334) 0x448a53 VMOVUPD	%ZMM14,(%RSI,%RAX,1)

(334) 0x448a5a ADD	$0x40,%RAX

(334) 0x448a5e VMOVUPD	(%R10,%RAX,1),%ZMM15

(334) 0x448a65 VMOVUPD	%ZMM15,(%RBX,%RAX,1)

(334) 0x448a6c VMOVUPD	(%R11,%RAX,1),%ZMM12

(334) 0x448a73 VMOVUPD	%ZMM12,(%RSI,%RAX,1)

(334) 0x448a7a ADD	$0x40,%RAX

(334) 0x448a7e VMOVUPD	(%R10,%RAX,1),%ZMM0

(334) 0x448a85 VMOVUPD	%ZMM0,(%RBX,%RAX,1)

(334) 0x448a8c VMOVUPD	(%R11,%RAX,1),%ZMM6

(334) 0x448a93 VMOVUPD	%ZMM6,(%RSI,%RAX,1)

(334) 0x448a9a ADD	$0x40,%RAX

(334) 0x448a9e CMP	%R9,%RAX

(334) 0x448aa1 JE	448bb2

  (335) 0x448aa7 VMOVUPD	(%R10,%RAX,1),%ZMM7

  (335) 0x448aae VMOVUPD	%ZMM7,(%RBX,%RAX,1)

  (335) 0x448ab5 VMOVUPD	(%R11,%RAX,1),%ZMM8

  (335) 0x448abc VMOVUPD	%ZMM8,(%RSI,%RAX,1)

  (335) 0x448ac3 VMOVUPD	0x40(%R10,%RAX,1),%ZMM9

  (335) 0x448acb VMOVUPD	%ZMM9,0x40(%RBX,%RAX,1)

  (335) 0x448ad3 VMOVUPD	0x40(%R11,%RAX,1),%ZMM10

  (335) 0x448adb VMOVUPD	%ZMM10,0x40(%RSI,%RAX,1)

  (335) 0x448ae3 VMOVUPD	0x80(%R10,%RAX,1),%ZMM11

  (335) 0x448aeb VMOVUPD	%ZMM11,0x80(%RBX,%RAX,1)

  (335) 0x448af3 VMOVUPD	0x80(%R11,%RAX,1),%ZMM13

  (335) 0x448afb VMOVUPD	%ZMM13,0x80(%RSI,%RAX,1)

  (335) 0x448b03 VMOVUPD	0xc0(%R10,%RAX,1),%ZMM14

  (335) 0x448b0b VMOVUPD	%ZMM14,0xc0(%RBX,%RAX,1)

  (335) 0x448b13 VMOVUPD	0xc0(%R11,%RAX,1),%ZMM15

  (335) 0x448b1b VMOVUPD	%ZMM15,0xc0(%RSI,%RAX,1)

  (335) 0x448b23 VMOVUPD	0x100(%R10,%RAX,1),%ZMM12

  (335) 0x448b2b VMOVUPD	%ZMM12,0x100(%RBX,%RAX,1)

  (335) 0x448b33 VMOVUPD	0x100(%R11,%RAX,1),%ZMM0

  (335) 0x448b3b VMOVUPD	%ZMM0,0x100(%RSI,%RAX,1)

  (335) 0x448b43 VMOVUPD	0x140(%R10,%RAX,1),%ZMM6

  (335) 0x448b4b VMOVUPD	%ZMM6,0x140(%RBX,%RAX,1)

  (335) 0x448b53 VMOVUPD	0x140(%R11,%RAX,1),%ZMM7

  (335) 0x448b5b VMOVUPD	%ZMM7,0x140(%RSI,%RAX,1)

  (335) 0x448b63 VMOVUPD	0x180(%R10,%RAX,1),%ZMM8

  (335) 0x448b6b VMOVUPD	%ZMM8,0x180(%RBX,%RAX,1)

  (335) 0x448b73 VMOVUPD	0x180(%R11,%RAX,1),%ZMM9

  (335) 0x448b7b VMOVUPD	%ZMM9,0x180(%RSI,%RAX,1)

  (335) 0x448b83 VMOVUPD	0x1c0(%R10,%RAX,1),%ZMM10

  (335) 0x448b8b VMOVUPD	%ZMM10,0x1c0(%RBX,%RAX,1)

  (335) 0x448b93 VMOVUPD	0x1c0(%R11,%RAX,1),%ZMM11

  (335) 0x448b9b VMOVUPD	%ZMM11,0x1c0(%RSI,%RAX,1)

  (335) 0x448ba3 ADD	$0x200,%RAX

  (335) 0x448ba9 CMP	%R9,%RAX

  (335) 0x448bac JNE	448aa7

(334) 0x448bb2 MOV	0x38(%RSP),%R10D

(334) 0x448bb7 MOV	%EDX,%EAX

(334) 0x448bb9 AND	$-0x8,%EAX

(334) 0x448bbc ADD	%EAX,%ECX

(334) 0x448bbe LEA	(%RAX,%R10,1),%EDI

(334) 0x448bc2 TEST	$0x7,%DL

(334) 0x448bc5 JE	448cf2

(334) 0x448bcb SUB	%EAX,%EDX

(334) 0x448bcd LEA	-0x1(%RDX),%EBX

(334) 0x448bd0 CMP	$0x2,%EBX

(334) 0x448bd3 JBE	448c39

(334) 0x448bd5 MOVSXD	0x38(%RSP),%R11

(334) 0x448bda MOV	0x18(%RSP),%RSI

(334) 0x448bdf MOV	0x20(%RSP),%RBX

(334) 0x448be4 VMOVQ	%XMM5,%R10

(334) 0x448be9 LEA	(%RSI,%R11,1),%R9

(334) 0x448bed LEA	(%RBX,%R11,1),%RSI

(334) 0x448bf1 MOV	0x30(%RSP),%RBX

(334) 0x448bf6 ADD	%RAX,%R9

(334) 0x448bf9 ADD	%RAX,%RSI

(334) 0x448bfc VMOVUPD	(%R10,%R9,8),%YMM13

(334) 0x448c02 MOV	0x28(%RSP),%R9

(334) 0x448c07 LEA	(%R9,%R11,1),%R10

(334) 0x448c0b ADD	%RBX,%R11

(334) 0x448c0e ADD	%RAX,%R10

(334) 0x448c11 VMOVUPD	%YMM13,(%R13,%RSI,8)

(334) 0x448c18 ADD	%RAX,%R11

(334) 0x448c1b MOV	%EDX,%EAX

(334) 0x448c1d VMOVUPD	(%R15,%R10,8),%YMM14

(334) 0x448c23 AND	$-0x4,%EAX

(334) 0x448c26 ADD	%EAX,%EDI

(334) 0x448c28 ADD	%EAX,%ECX

(334) 0x448c2a AND	$0x3,%EDX

(334) 0x448c2d VMOVUPD	%YMM14,(%R14,%R11,8)

(334) 0x448c33 JE	448cf2

(334) 0x448c39 MOV	0x18(%RSP),%RBX

(334) 0x448c3e MOV	0x20(%RSP),%RSI

(334) 0x448c43 MOVSXD	%EDI,%R9

(334) 0x448c46 VMOVQ	%XMM5,%R11

(334) 0x448c4b LEA	(%RSI,%R9,1),%R10

(334) 0x448c4f LEA	(%RBX,%R9,1),%RDX

(334) 0x448c53 VMOVSD	(%R11,%RDX,8),%XMM15

(334) 0x448c59 MOV	0x30(%RSP),%R11

(334) 0x448c5e VMOVSD	%XMM15,(%R13,%R10,8)

(334) 0x448c65 MOV	0x28(%RSP),%R10

(334) 0x448c6a LEA	(%R10,%R9,1),%RAX

(334) 0x448c6e ADD	%R11,%R9

(334) 0x448c71 VMOVSD	(%R15,%RAX,8),%XMM12

(334) 0x448c77 VMOVSD	%XMM12,(%R14,%R9,8)

(334) 0x448c7d LEA	0x1(%RCX),%R9D

(334) 0x448c81 CMP	%R12D,%R9D

(334) 0x448c84 JAE	448cf2

(334) 0x448c86 LEA	0x1(%RDI),%EAX

(334) 0x448c89 VMOVQ	%XMM5,%R9

(334) 0x448c8e ADD	$0x2,%ECX

(334) 0x448c91 CLTQ

(334) 0x448c93 LEA	(%RBX,%RAX,1),%RDX

(334) 0x448c97 VMOVSD	(%R9,%RDX,8),%XMM0

(334) 0x448c9d LEA	(%RSI,%RAX,1),%RDX

(334) 0x448ca1 LEA	(%R10,%RAX,1),%R9

(334) 0x448ca5 ADD	%R11,%RAX

(334) 0x448ca8 VMOVSD	%XMM0,(%R13,%RDX,8)

(334) 0x448caf MOV	%R11,%RDX

(334) 0x448cb2 VMOVSD	(%R15,%R9,8),%XMM6

(334) 0x448cb8 VMOVSD	%XMM6,(%R14,%RAX,8)

(334) 0x448cbe CMP	%R12D,%ECX

(334) 0x448cc1 JAE	448cf2

(334) 0x448cc3 ADD	$0x2,%EDI

(334) 0x448cc6 MOVSXD	%EDI,%RCX

(334) 0x448cc9 VMOVQ	%XMM5,%RDI

(334) 0x448cce ADD	%RCX,%RBX

(334) 0x448cd1 ADD	%RCX,%RSI

(334) 0x448cd4 ADD	%RCX,%R10

(334) 0x448cd7 ADD	%RCX,%RDX

(334) 0x448cda VMOVSD	(%RDI,%RBX,8),%XMM5

(334) 0x448cdf VMOVSD	%XMM5,(%R13,%RSI,8)

(334) 0x448ce6 VMOVSD	(%R15,%R10,8),%XMM7

(334) 0x448cec VMOVSD	%XMM7,(%R14,%RDX,8)

(334) 0x448cf2 MOV	%R12D,%ECX

(334) 0x448cf5 INC	%R8

(334) 0x448cf8 CMP	%R8D,0x14(%RSP)

(334) 0x448cfd JLE	448d20

(334) 0x448cff MOV	0x8(%RSP),%EDX

(334) 0x448d03 MOV	0x10(%RSP),%R13D

(334) 0x448d08 MOV	0xc(%RSP),%R12D

(334) 0x448d0d SUB	%ECX,%EDX

(334) 0x448d0f MOV	%R13D,0x38(%RSP)

(334) 0x448d14 JMP	4488d0

0x448d19 NOPL	(%RAX)

0x448d20 VZEROUPPER

0x448d23 LEA	-0x28(%RBP),%RSP

0x448d27 POP	%RBX

0x448d28 POP	%R12

0x448d2a POP	%R13

0x448d2c POP	%R14

0x448d2e POP	%R15

0x448d30 POP	%RBP

0x448d31 RET

0x448d32 NOPW	%CS:(%RAX,%RAX,1)

0x448d3d NOPL	(%RAX)

(334) 0x448d40 MOV	0x38(%RSP),%EDI

(334) 0x448d44 XOR	%EAX,%EAX

(334) 0x448d46 JMP	448bcb

0x448d4b INC	%R9D

0x448d4e XOR	%EDX,%EDX

0x448d50 JMP	448877

0x448d55 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.96+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.20+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	reset_field(global_variables&)	reset_field.cpp:44	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	reset_field.cpp:34-38
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:34-38

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.75 cycles (1.23x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:37

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	80
nb uops	78
loop length	284
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4487f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x2,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ESI,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 448d23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 448d23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 448d4b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x55b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R8D,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 448d23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ 0x8(%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0xc(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ (%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%RDI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 448877 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	reset_field.cpp:34-38
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:34-38

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:36
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:37

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	80
nb uops	78
loop length	284
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4487f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x2,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ESI,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 448d23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 448d23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 448d4b <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x55b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R8D,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 448d23 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ 0x8(%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0xc(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ (%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%RDI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 448877 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼reset_field_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [...–	2.62	0.96
▼Loop 334 - reset_field.cpp:36-38 - exec–	0.00	0.01
○Loop 335 - reset_field.cpp:37-38 - exec	2.62	0.96

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code