OV - exec - Function reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: reset_field_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double> ...	Module: exec	Source: reset_field.cpp:44-48 [...]	Coverage (incl. loops): 2.67% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp: 44 - 48

--------------------------------------------------------------------------------

44: #pragma omp parallel for simd collapse(2)

45:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

46:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

47:       xvel0(i, j) = xvel1(i, j);

48:       yvel0(i, j) = yvel1(i, j);

0x448280 PUSH	%RBP

0x448281 MOV	%RSP,%RBP

0x448284 PUSH	%R15

0x448286 PUSH	%R14

0x448288 PUSH	%R13

0x44828a PUSH	%R12

0x44828c PUSH	%RBX

0x44828d AND	$-0x40,%RSP

0x448291 SUB	$0x40,%RSP

0x448295 MOV	0x28(%RDI),%EAX

0x448298 MOV	0x2c(%RDI),%ESI

0x44829b MOV	0x20(%RDI),%ECX

0x44829e MOV	0x24(%RDI),%EDX

0x4482a1 MOV	%RDI,0x38(%RSP)

0x4482a6 ADD	$0x3,%ESI

0x4482a9 INC	%ECX

0x4482ab LEA	0x1(%RAX),%EBX

0x4482ae MOV	%ESI,0x14(%RSP)

0x4482b2 MOV	%ECX,0x10(%RSP)

0x4482b6 CMP	%ESI,%EBX

0x4482b8 JGE	4487b3

0x4482be MOV	%ESI,%R14D

0x4482c1 LEA	0x3(%RDX),%R15D

0x4482c5 SUB	%EBX,%R14D

0x4482c8 CMP	%R15D,%ECX

0x4482cb JGE	4487b3

0x4482d1 MOV	%R15D,%R13D

0x4482d4 SUB	%ECX,%R13D

0x4482d7 IMUL	%R13D,%R14D

0x4482db MOV	%R13D,0xc(%RSP)

0x4482e0 CALL	404630 <omp_get_num_threads@plt>

0x4482e5 MOV	%EAX,%R12D

0x4482e8 CALL	404520 <omp_get_thread_num@plt>

0x4482ed XOR	%EDX,%EDX

0x4482ef MOV	0x38(%RSP),%RDI

0x4482f4 MOV	%EAX,%ECX

0x4482f6 MOV	%R14D,%EAX

0x4482f9 DIV	%R12D

0x4482fc CMP	%EDX,%ECX

0x4482fe MOV	%EAX,%R9D

0x448301 JB	4487db

0x448307 IMUL	%R9D,%ECX

0x44830b ADD	%EDX,%ECX

0x44830d LEA	(%R9,%RCX,1),%R8D

0x448311 MOV	%R8D,0x8(%RSP)

0x448316 CMP	%R8D,%ECX

0x448319 JAE	4487b3

0x44831f MOV	%ECX,%EAX

0x448321 XOR	%EDX,%EDX

0x448323 MOV	0x10(%RSP),%R10D

0x448328 VMOVQ	0x8(%RDI),%XMM3

0x44832d DIVL	0xc(%RSP)

0x448331 VMOVQ	(%RDI),%XMM4

0x448335 VMOVQ	0x18(%RDI),%XMM2

0x44833a VMOVQ	0x10(%RDI),%XMM1

0x44833f ADD	%R10D,%EDX

0x448342 ADD	%EBX,%EAX

0x448344 SUB	%EDX,%R15D

0x448347 MOV	%EDX,0x38(%RSP)

0x44834b MOVSXD	%EAX,%R8

0x44834e MOV	%R9D,%EDX

0x448351 MOV	%R15D,%R12D

0x448354 NOPW	%CS:(%RAX,%RAX,1)

0x44835f NOP

(332) 0x448360 CMP	%R12D,%EDX

(332) 0x448363 CMOVA	%R12D,%EDX

(332) 0x448367 LEA	(%RCX,%RDX,1),%R12D

(332) 0x44836b CMP	%R12D,%ECX

(332) 0x44836e JAE	448785

(332) 0x448374 VMOVQ	%XMM3,%R11

(332) 0x448379 VMOVQ	%XMM2,%R14

(332) 0x44837e LEA	-0x1(%RDX),%EDI

(332) 0x448381 VMOVQ	%XMM4,%RSI

(332) 0x448386 VMOVQ	%XMM1,%R9

(332) 0x44838b MOV	(%R11),%RBX

(332) 0x44838e VMOVQ	0x10(%R11),%XMM5

(332) 0x448394 MOV	0x10(%RSI),%R13

(332) 0x448398 MOV	(%R14),%R11

(332) 0x44839b MOV	(%RSI),%RSI

(332) 0x44839e MOV	0x10(%R14),%R15

(332) 0x4483a2 MOV	0x10(%R9),%R14

(332) 0x4483a6 MOV	(%R9),%R9

(332) 0x4483a9 IMUL	%R8,%RBX

(332) 0x4483ad IMUL	%R8,%RSI

(332) 0x4483b1 IMUL	%R8,%R11

(332) 0x4483b5 IMUL	%R8,%R9

(332) 0x4483b9 MOV	%RBX,0x18(%RSP)

(332) 0x4483be MOV	%RSI,0x20(%RSP)

(332) 0x4483c3 MOV	%R11,0x28(%RSP)

(332) 0x4483c8 MOV	%R9,0x30(%RSP)

(332) 0x4483cd CMP	$0x6,%EDI

(332) 0x4483d0 JBE	4487d0

(332) 0x4483d6 MOVSXD	0x38(%RSP),%RAX

(332) 0x4483db LEA	(%RBX,%RAX,1),%R10

(332) 0x4483df LEA	(%RSI,%RAX,1),%RSI

(332) 0x4483e3 LEA	(%R11,%RAX,1),%R11

(332) 0x4483e7 ADD	%R9,%RAX

(332) 0x4483ea MOV	%EDX,%R9D

(332) 0x4483ed VMOVQ	%XMM5,%RBX

(332) 0x4483f2 LEA	(%R15,%R11,8),%R11

(332) 0x4483f6 SHR	$0x3,%R9D

(332) 0x4483fa SAL	$0x6,%R9

(332) 0x4483fe LEA	-0x40(%R9),%RDI

(332) 0x448402 LEA	(%RBX,%R10,8),%R10

(332) 0x448406 LEA	(%R13,%RSI,8),%RBX

(332) 0x44840b LEA	(%R14,%RAX,8),%RSI

(332) 0x44840f SHR	$0x6,%RDI

(332) 0x448413 INC	%RDI

(332) 0x448416 XOR	%EAX,%EAX

(332) 0x448418 AND	$0x7,%EDI

(332) 0x44841b JE	448537

(332) 0x448421 CMP	$0x1,%RDI

(332) 0x448425 JE	44850e

(332) 0x44842b CMP	$0x2,%RDI

(332) 0x44842f JE	4484ee

(332) 0x448435 CMP	$0x3,%RDI

(332) 0x448439 JE	4484ce

(332) 0x44843f CMP	$0x4,%RDI

(332) 0x448443 JE	4484ae

(332) 0x448445 CMP	$0x5,%RDI

(332) 0x448449 JE	44848e

(332) 0x44844b CMP	$0x6,%RDI

(332) 0x44844f JE	44846e

(332) 0x448451 VMOVUPD	(%R10),%ZMM12

(332) 0x448457 MOV	$0x40,%EAX

(332) 0x44845c VMOVUPD	%ZMM12,(%RBX)

(332) 0x448462 VMOVUPD	(%R11),%ZMM0

(332) 0x448468 VMOVUPD	%ZMM0,(%RSI)

(332) 0x44846e VMOVUPD	(%R10,%RAX,1),%ZMM6

(332) 0x448475 VMOVUPD	%ZMM6,(%RBX,%RAX,1)

(332) 0x44847c VMOVUPD	(%R11,%RAX,1),%ZMM7

(332) 0x448483 VMOVUPD	%ZMM7,(%RSI,%RAX,1)

(332) 0x44848a ADD	$0x40,%RAX

(332) 0x44848e VMOVUPD	(%R10,%RAX,1),%ZMM8

(332) 0x448495 VMOVUPD	%ZMM8,(%RBX,%RAX,1)

(332) 0x44849c VMOVUPD	(%R11,%RAX,1),%ZMM9

(332) 0x4484a3 VMOVUPD	%ZMM9,(%RSI,%RAX,1)

(332) 0x4484aa ADD	$0x40,%RAX

(332) 0x4484ae VMOVUPD	(%R10,%RAX,1),%ZMM10

(332) 0x4484b5 VMOVUPD	%ZMM10,(%RBX,%RAX,1)

(332) 0x4484bc VMOVUPD	(%R11,%RAX,1),%ZMM11

(332) 0x4484c3 VMOVUPD	%ZMM11,(%RSI,%RAX,1)

(332) 0x4484ca ADD	$0x40,%RAX

(332) 0x4484ce VMOVUPD	(%R10,%RAX,1),%ZMM13

(332) 0x4484d5 VMOVUPD	%ZMM13,(%RBX,%RAX,1)

(332) 0x4484dc VMOVUPD	(%R11,%RAX,1),%ZMM14

(332) 0x4484e3 VMOVUPD	%ZMM14,(%RSI,%RAX,1)

(332) 0x4484ea ADD	$0x40,%RAX

(332) 0x4484ee VMOVUPD	(%R10,%RAX,1),%ZMM15

(332) 0x4484f5 VMOVUPD	%ZMM15,(%RBX,%RAX,1)

(332) 0x4484fc VMOVUPD	(%R11,%RAX,1),%ZMM12

(332) 0x448503 VMOVUPD	%ZMM12,(%RSI,%RAX,1)

(332) 0x44850a ADD	$0x40,%RAX

(332) 0x44850e VMOVUPD	(%R10,%RAX,1),%ZMM0

(332) 0x448515 VMOVUPD	%ZMM0,(%RBX,%RAX,1)

(332) 0x44851c VMOVUPD	(%R11,%RAX,1),%ZMM6

(332) 0x448523 VMOVUPD	%ZMM6,(%RSI,%RAX,1)

(332) 0x44852a ADD	$0x40,%RAX

(332) 0x44852e CMP	%R9,%RAX

(332) 0x448531 JE	448642

  (333) 0x448537 VMOVUPD	(%R10,%RAX,1),%ZMM7

  (333) 0x44853e VMOVUPD	%ZMM7,(%RBX,%RAX,1)

  (333) 0x448545 VMOVUPD	(%R11,%RAX,1),%ZMM8

  (333) 0x44854c VMOVUPD	%ZMM8,(%RSI,%RAX,1)

  (333) 0x448553 VMOVUPD	0x40(%R10,%RAX,1),%ZMM9

  (333) 0x44855b VMOVUPD	%ZMM9,0x40(%RBX,%RAX,1)

  (333) 0x448563 VMOVUPD	0x40(%R11,%RAX,1),%ZMM10

  (333) 0x44856b VMOVUPD	%ZMM10,0x40(%RSI,%RAX,1)

  (333) 0x448573 VMOVUPD	0x80(%R10,%RAX,1),%ZMM11

  (333) 0x44857b VMOVUPD	%ZMM11,0x80(%RBX,%RAX,1)

  (333) 0x448583 VMOVUPD	0x80(%R11,%RAX,1),%ZMM13

  (333) 0x44858b VMOVUPD	%ZMM13,0x80(%RSI,%RAX,1)

  (333) 0x448593 VMOVUPD	0xc0(%R10,%RAX,1),%ZMM14

  (333) 0x44859b VMOVUPD	%ZMM14,0xc0(%RBX,%RAX,1)

  (333) 0x4485a3 VMOVUPD	0xc0(%R11,%RAX,1),%ZMM15

  (333) 0x4485ab VMOVUPD	%ZMM15,0xc0(%RSI,%RAX,1)

  (333) 0x4485b3 VMOVUPD	0x100(%R10,%RAX,1),%ZMM12

  (333) 0x4485bb VMOVUPD	%ZMM12,0x100(%RBX,%RAX,1)

  (333) 0x4485c3 VMOVUPD	0x100(%R11,%RAX,1),%ZMM0

  (333) 0x4485cb VMOVUPD	%ZMM0,0x100(%RSI,%RAX,1)

  (333) 0x4485d3 VMOVUPD	0x140(%R10,%RAX,1),%ZMM6

  (333) 0x4485db VMOVUPD	%ZMM6,0x140(%RBX,%RAX,1)

  (333) 0x4485e3 VMOVUPD	0x140(%R11,%RAX,1),%ZMM7

  (333) 0x4485eb VMOVUPD	%ZMM7,0x140(%RSI,%RAX,1)

  (333) 0x4485f3 VMOVUPD	0x180(%R10,%RAX,1),%ZMM8

  (333) 0x4485fb VMOVUPD	%ZMM8,0x180(%RBX,%RAX,1)

  (333) 0x448603 VMOVUPD	0x180(%R11,%RAX,1),%ZMM9

  (333) 0x44860b VMOVUPD	%ZMM9,0x180(%RSI,%RAX,1)

  (333) 0x448613 VMOVUPD	0x1c0(%R10,%RAX,1),%ZMM10

  (333) 0x44861b VMOVUPD	%ZMM10,0x1c0(%RBX,%RAX,1)

  (333) 0x448623 VMOVUPD	0x1c0(%R11,%RAX,1),%ZMM11

  (333) 0x44862b VMOVUPD	%ZMM11,0x1c0(%RSI,%RAX,1)

  (333) 0x448633 ADD	$0x200,%RAX

  (333) 0x448639 CMP	%R9,%RAX

  (333) 0x44863c JNE	448537

(332) 0x448642 MOV	0x38(%RSP),%R10D

(332) 0x448647 MOV	%EDX,%EAX

(332) 0x448649 AND	$-0x8,%EAX

(332) 0x44864c ADD	%EAX,%ECX

(332) 0x44864e LEA	(%RAX,%R10,1),%EDI

(332) 0x448652 TEST	$0x7,%DL

(332) 0x448655 JE	448782

(332) 0x44865b SUB	%EAX,%EDX

(332) 0x44865d LEA	-0x1(%RDX),%EBX

(332) 0x448660 CMP	$0x2,%EBX

(332) 0x448663 JBE	4486c9

(332) 0x448665 MOVSXD	0x38(%RSP),%R11

(332) 0x44866a MOV	0x18(%RSP),%RSI

(332) 0x44866f MOV	0x20(%RSP),%RBX

(332) 0x448674 VMOVQ	%XMM5,%R10

(332) 0x448679 LEA	(%RSI,%R11,1),%R9

(332) 0x44867d LEA	(%RBX,%R11,1),%RSI

(332) 0x448681 MOV	0x30(%RSP),%RBX

(332) 0x448686 ADD	%RAX,%R9

(332) 0x448689 ADD	%RAX,%RSI

(332) 0x44868c VMOVUPD	(%R10,%R9,8),%YMM13

(332) 0x448692 MOV	0x28(%RSP),%R9

(332) 0x448697 LEA	(%R9,%R11,1),%R10

(332) 0x44869b ADD	%RBX,%R11

(332) 0x44869e ADD	%RAX,%R10

(332) 0x4486a1 VMOVUPD	%YMM13,(%R13,%RSI,8)

(332) 0x4486a8 ADD	%RAX,%R11

(332) 0x4486ab MOV	%EDX,%EAX

(332) 0x4486ad VMOVUPD	(%R15,%R10,8),%YMM14

(332) 0x4486b3 AND	$-0x4,%EAX

(332) 0x4486b6 ADD	%EAX,%EDI

(332) 0x4486b8 ADD	%EAX,%ECX

(332) 0x4486ba AND	$0x3,%EDX

(332) 0x4486bd VMOVUPD	%YMM14,(%R14,%R11,8)

(332) 0x4486c3 JE	448782

(332) 0x4486c9 MOV	0x18(%RSP),%RBX

(332) 0x4486ce MOV	0x20(%RSP),%RSI

(332) 0x4486d3 MOVSXD	%EDI,%R9

(332) 0x4486d6 VMOVQ	%XMM5,%R11

(332) 0x4486db LEA	(%RSI,%R9,1),%R10

(332) 0x4486df LEA	(%RBX,%R9,1),%RDX

(332) 0x4486e3 VMOVSD	(%R11,%RDX,8),%XMM15

(332) 0x4486e9 MOV	0x30(%RSP),%R11

(332) 0x4486ee VMOVSD	%XMM15,(%R13,%R10,8)

(332) 0x4486f5 MOV	0x28(%RSP),%R10

(332) 0x4486fa LEA	(%R10,%R9,1),%RAX

(332) 0x4486fe ADD	%R11,%R9

(332) 0x448701 VMOVSD	(%R15,%RAX,8),%XMM12

(332) 0x448707 VMOVSD	%XMM12,(%R14,%R9,8)

(332) 0x44870d LEA	0x1(%RCX),%R9D

(332) 0x448711 CMP	%R12D,%R9D

(332) 0x448714 JAE	448782

(332) 0x448716 LEA	0x1(%RDI),%EAX

(332) 0x448719 VMOVQ	%XMM5,%R9

(332) 0x44871e ADD	$0x2,%ECX

(332) 0x448721 CLTQ

(332) 0x448723 LEA	(%RBX,%RAX,1),%RDX

(332) 0x448727 VMOVSD	(%R9,%RDX,8),%XMM0

(332) 0x44872d LEA	(%RSI,%RAX,1),%RDX

(332) 0x448731 LEA	(%R10,%RAX,1),%R9

(332) 0x448735 ADD	%R11,%RAX

(332) 0x448738 VMOVSD	%XMM0,(%R13,%RDX,8)

(332) 0x44873f MOV	%R11,%RDX

(332) 0x448742 VMOVSD	(%R15,%R9,8),%XMM6

(332) 0x448748 VMOVSD	%XMM6,(%R14,%RAX,8)

(332) 0x44874e CMP	%R12D,%ECX

(332) 0x448751 JAE	448782

(332) 0x448753 ADD	$0x2,%EDI

(332) 0x448756 MOVSXD	%EDI,%RCX

(332) 0x448759 VMOVQ	%XMM5,%RDI

(332) 0x44875e ADD	%RCX,%RBX

(332) 0x448761 ADD	%RCX,%RSI

(332) 0x448764 ADD	%RCX,%R10

(332) 0x448767 ADD	%RCX,%RDX

(332) 0x44876a VMOVSD	(%RDI,%RBX,8),%XMM5

(332) 0x44876f VMOVSD	%XMM5,(%R13,%RSI,8)

(332) 0x448776 VMOVSD	(%R15,%R10,8),%XMM7

(332) 0x44877c VMOVSD	%XMM7,(%R14,%RDX,8)

(332) 0x448782 MOV	%R12D,%ECX

(332) 0x448785 INC	%R8

(332) 0x448788 CMP	%R8D,0x14(%RSP)

(332) 0x44878d JLE	4487b0

(332) 0x44878f MOV	0x8(%RSP),%EDX

(332) 0x448793 MOV	0x10(%RSP),%R13D

(332) 0x448798 MOV	0xc(%RSP),%R12D

(332) 0x44879d SUB	%ECX,%EDX

(332) 0x44879f MOV	%R13D,0x38(%RSP)

(332) 0x4487a4 JMP	448360

0x4487a9 NOPL	(%RAX)

0x4487b0 VZEROUPPER

0x4487b3 LEA	-0x28(%RBP),%RSP

0x4487b7 POP	%RBX

0x4487b8 POP	%R12

0x4487ba POP	%R13

0x4487bc POP	%R14

0x4487be POP	%R15

0x4487c0 POP	%RBP

0x4487c1 RET

0x4487c2 NOPW	%CS:(%RAX,%RAX,1)

0x4487cd NOPL	(%RAX)

(332) 0x4487d0 MOV	0x38(%RSP),%EDI

(332) 0x4487d4 XOR	%EAX,%EAX

(332) 0x4487d6 JMP	44865b

0x4487db INC	%R9D

0x4487de XOR	%EDX,%EDX

0x4487e0 JMP	448307

0x4487e5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.86+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.26+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	reset_field(global_variables&)	reset_field.cpp:61	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	reset_field.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.75 cycles (1.23x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:47

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	80
nb uops	78
loop length	284
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 448280

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x3,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ESI,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4487b3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4487b3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 4487db <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x55b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R8D,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4487b3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ 0x8(%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0xc(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ (%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%RDI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 448307 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	reset_field.cpp:44-48
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:44-48

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/reset_field.cpp:47

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	80
nb uops	78
loop length	284
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 448280

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x3,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ESI,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4487b3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4487b3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 4487db <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x55b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R8D,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4487b3 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x533>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ 0x8(%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0xc(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ (%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%RDI),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 448307 <_Z18reset_field_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼reset_field_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [...–	2.67	0.98
▼Loop 332 - reset_field.cpp:46-48 - exec–	0.00	0.01
○Loop 333 - reset_field.cpp:47-48 - exec	2.67	0.98

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code