OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:69-83 [...]	Coverage (incl. loops): 6.59% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 69 - 83

--------------------------------------------------------------------------------

69: #pragma omp parallel for simd collapse(2)

70:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

71:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

72:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1))) * 0.25 * dt;

73:         double right_flux =

74:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel1(i + 1, j + 0) + xvel1(i + 1, j + 1))) * 0.25 * dt;

75:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0))) * 0.25 * dt;

76:         double top_flux =

77:             (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel1(i + 0, j + 1) + yvel1(i + 1, j + 1))) * 0.25 * dt;

78:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

79:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

80:         double recip_volume = 1.0 / volume(i, j);

81:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

82:         energy1(i, j) = energy0(i, j) - energy_change;

83:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x446fc0 PUSH	%RBP

0x446fc1 MOV	%RSP,%RBP

0x446fc4 PUSH	%R15

0x446fc6 PUSH	%R14

0x446fc8 PUSH	%R13

0x446fca PUSH	%R12

0x446fcc PUSH	%RBX

0x446fcd MOV	%RDI,%RBX

0x446fd0 AND	$-0x40,%RSP

0x446fd4 SUB	$0x1c0,%RSP

0x446fdb MOV	0x78(%RDI),%EAX

0x446fde MOV	0x7c(%RDI),%EDX

0x446fe1 MOV	0x70(%RDI),%ESI

0x446fe4 MOV	0x74(%RDI),%EDI

0x446fe7 ADD	$0x2,%EDX

0x446fea INC	%ESI

0x446fec LEA	0x1(%RAX),%R12D

0x446ff0 MOV	%EDX,0xb8(%RSP)

0x446ff7 MOV	%ESI,0x8c(%RSP)

0x446ffe CMP	%EDX,%R12D

0x447001 JGE	447d73

0x447007 MOV	%EDX,%R14D

0x44700a LEA	0x2(%RDI),%R15D

0x44700e SUB	%R12D,%R14D

0x447011 CMP	%R15D,%ESI

0x447014 JGE	447d73

0x44701a MOV	%R15D,%ECX

0x44701d SUB	%ESI,%ECX

0x44701f MOV	%ECX,0xbc(%RSP)

0x447026 CALL	404630 <omp_get_num_threads@plt>

0x44702b MOV	%EAX,%R13D

0x44702e CALL	404520 <omp_get_thread_num@plt>

0x447033 XOR	%EDX,%EDX

0x447035 MOV	%EAX,%R8D

0x447038 MOV	0xbc(%RSP),%EAX

0x44703f IMUL	%R14D,%EAX

0x447043 DIV	%R13D

0x447046 MOV	%EAX,%ECX

0x447048 CMP	%EDX,%R8D

0x44704b JB	447da5

0x447051 IMUL	%ECX,%R8D

0x447055 LEA	(%R8,%RDX,1),%EAX

0x447059 LEA	(%RCX,%RAX,1),%R9D

0x44705d MOV	%EAX,0x1b4(%RSP)

0x447064 MOV	%R9D,0x88(%RSP)

0x44706c CMP	%R9D,%EAX

0x44706f JAE	447d73

0x447075 XOR	%EDX,%EDX

0x447077 MOV	0x8c(%RSP),%R10D

0x44707f MOV	0x8(%RBX),%R11

0x447083 MOV	0x50(%RBX),%RSI

0x447087 DIVL	0xbc(%RSP)

0x44708e MOV	0x58(%RBX),%RDI

0x447092 MOV	0x60(%RBX),%R14

0x447096 MOV	0x68(%RBX),%R13

0x44709a MOV	0x18(%RBX),%R8

0x44709e MOV	0x40(%RBX),%R9

0x4470a2 VMOVSD	0x1d5f6(%RIP),%XMM0

0x4470aa VMULSD	(%RBX),%XMM0,%XMM2

0x4470ae VBROADCASTSD	%XMM2,%YMM0

0x4470b3 VBROADCASTSD	%XMM2,%ZMM7

0x4470b9 MOV	%R11,0x80(%RSP)

0x4470c1 MOV	%RSI,0x78(%RSP)

0x4470c6 MOV	0x48(%RBX),%R11

0x4470ca MOV	0x30(%RBX),%RSI

0x4470ce MOV	%RDI,0x70(%RSP)

0x4470d3 MOV	0x38(%RBX),%RDI

0x4470d7 MOV	%R14,0x60(%RSP)

0x4470dc MOV	%R13,0x58(%RSP)

0x4470e1 MOV	%R8,0x50(%RSP)

0x4470e6 MOV	%R9,0x48(%RSP)

0x4470eb MOV	%R11,0x38(%RSP)

0x4470f0 MOV	%RSI,0x30(%RSP)

0x4470f5 MOV	%RDI,0x28(%RSP)

0x4470fa ADD	%EDX,%R10D

0x4470fd MOV	%R15D,%EDX

0x447100 MOV	0x10(%RBX),%R15

0x447104 ADD	%R12D,%EAX

0x447107 MOV	%R10D,0x1a0(%RSP)

0x44710f SUB	%R10D,%EDX

0x447112 MOV	0x20(%RBX),%R10

0x447116 MOV	0x28(%RBX),%RBX

0x44711a CLTQ

0x44711c MOV	%R15,0x68(%RSP)

0x447121 MOV	%R10,0x40(%RSP)

0x447126 MOV	%RBX,0x20(%RSP)

0x44712b MOV	%RAX,0x1a8(%RSP)

0x447133 VMOVSD	0x1c855(%RIP),%XMM12

0x44713b VBROADCASTSD	%XMM12,%YMM11

0x447140 VBROADCASTSD	%XMM12,%ZMM6

0x447146 NOPW	%CS:(%RAX,%RAX,1)

(326) 0x447150 MOV	0x1b4(%RSP),%R12D

(326) 0x447158 CMP	%EDX,%ECX

(326) 0x44715a MOV	%EDX,%ESI

(326) 0x44715c CMOVBE	%ECX,%ESI

(326) 0x44715f LEA	(%R12,%RSI,1),%ECX

(326) 0x447163 MOV	%ECX,0x1b0(%RSP)

(326) 0x44716a CMP	%ECX,%R12D

(326) 0x44716d JAE	447d21

(326) 0x447173 MOV	0x78(%RSP),%R15

(326) 0x447178 MOV	0x1a8(%RSP),%RBX

(326) 0x447180 MOV	0x70(%RSP),%R13

(326) 0x447185 MOV	0x80(%RSP),%RAX

(326) 0x44718d MOV	0x68(%RSP),%RDI

(326) 0x447192 MOV	(%R15),%R14

(326) 0x447195 MOV	%RBX,%R8

(326) 0x447198 MOV	(%R13),%R9

(326) 0x44719c MOV	0x10(%RAX),%RDX

(326) 0x4471a0 MOV	(%RAX),%R11

(326) 0x4471a3 VMOVQ	0x10(%R13),%XMM30

(326) 0x4471aa MOV	0x60(%RSP),%RAX

(326) 0x4471af MOV	0x58(%RSP),%R13

(326) 0x4471b4 MOV	0x10(%RDI),%R12

(326) 0x4471b8 MOV	(%RDI),%RCX

(326) 0x4471bb VMOVQ	0x10(%R15),%XMM28

(326) 0x4471c2 MOV	%RBX,%RDI

(326) 0x4471c5 MOV	%RBX,%R15

(326) 0x4471c8 IMUL	%R14,%R8

(326) 0x4471cc MOV	%RDX,0x100(%RSP)

(326) 0x4471d4 MOV	(%RAX),%RDX

(326) 0x4471d7 IMUL	%RBX,%R11

(326) 0x4471db VMOVQ	0x10(%RAX),%XMM31

(326) 0x4471e2 VMOVQ	0x10(%R13),%XMM26

(326) 0x4471e9 MOV	%R12,0x118(%RSP)

(326) 0x4471f1 MOV	%RBX,%R12

(326) 0x4471f4 ADD	%R8,%R14

(326) 0x4471f7 IMUL	%RCX,%R12

(326) 0x4471fb MOV	%R8,0xd0(%RSP)

(326) 0x447203 MOV	%R14,0x108(%RSP)

(326) 0x44720b MOV	%RBX,%R14

(326) 0x44720e MOV	%R11,0xc8(%RSP)

(326) 0x447216 IMUL	%R9,%R14

(326) 0x44721a IMUL	%RDX,%R15

(326) 0x44721e ADD	%R12,%RCX

(326) 0x447221 MOV	%R12,0xe0(%RSP)

(326) 0x447229 MOV	%RCX,0x120(%RSP)

(326) 0x447231 LEA	(%R9,%R14,1),%R10

(326) 0x447235 MOV	(%R13),%R9

(326) 0x447239 MOV	%R14,0xd8(%RSP)

(326) 0x447241 MOV	%R10,0x110(%RSP)

(326) 0x447249 LEA	(%RDX,%R15,1),%R10

(326) 0x44724d MOV	%R15,0xe8(%RSP)

(326) 0x447255 MOV	%R10,0x128(%RSP)

(326) 0x44725d IMUL	%R9,%RDI

(326) 0x447261 LEA	(%R9,%RDI,1),%RCX

(326) 0x447265 MOV	%RDI,0xf0(%RSP)

(326) 0x44726d MOV	%RCX,0x130(%RSP)

(326) 0x447275 MOV	0x50(%RSP),%RDX

(326) 0x44727a MOV	0x48(%RSP),%R13

(326) 0x44727f MOV	0x10(%R13),%R9

(326) 0x447283 MOV	0x10(%RDX),%RAX

(326) 0x447287 MOV	(%R13),%R10

(326) 0x44728b MOV	0x38(%RSP),%R13

(326) 0x447290 MOV	%R9,0x148(%RSP)

(326) 0x447298 MOV	0x40(%RSP),%R9

(326) 0x44729d MOV	%RAX,0x138(%RSP)

(326) 0x4472a5 MOV	%RBX,%RAX

(326) 0x4472a8 IMUL	%RAX,%R10

(326) 0x4472ac IMUL	(%RDX),%RBX

(326) 0x4472b0 MOV	%R10,0x140(%RSP)

(326) 0x4472b8 MOV	0x10(%R13),%R10

(326) 0x4472bc MOV	(%R9),%RDX

(326) 0x4472bf MOV	0x10(%R9),%RCX

(326) 0x4472c3 MOV	0x30(%RSP),%R9

(326) 0x4472c8 MOV	%RBX,0xf8(%RSP)

(326) 0x4472d0 MOV	%R10,0x198(%RSP)

(326) 0x4472d8 MOV	0x28(%RSP),%R10

(326) 0x4472dd IMUL	%RAX,%RDX

(326) 0x4472e1 MOV	%RCX,0x158(%RSP)

(326) 0x4472e9 MOV	(%R13),%RCX

(326) 0x4472ed MOV	(%R9),%R13

(326) 0x4472f0 MOV	%RDX,0x150(%RSP)

(326) 0x4472f8 MOV	0x10(%R9),%RDX

(326) 0x4472fc MOV	0x20(%RSP),%R9

(326) 0x447301 IMUL	%RAX,%RCX

(326) 0x447305 IMUL	%RAX,%R13

(326) 0x447309 MOV	%RDX,0x188(%RSP)

(326) 0x447311 MOV	(%R10),%RDX

(326) 0x447314 MOV	%RCX,0x160(%RSP)

(326) 0x44731c MOV	0x10(%R10),%RCX

(326) 0x447320 MOV	%R13,0x190(%RSP)

(326) 0x447328 MOV	0x10(%R9),%R13

(326) 0x44732c IMUL	%RAX,%RDX

(326) 0x447330 MOV	%RCX,0x178(%RSP)

(326) 0x447338 MOV	%RDX,0x180(%RSP)

(326) 0x447340 MOV	%R13,0x168(%RSP)

(326) 0x447348 MOV	(%R9),%R10

(326) 0x44734b IMUL	%RAX,%R10

(326) 0x44734f LEA	-0x1(%RSI),%EAX

(326) 0x447352 MOV	%R10,0x170(%RSP)

(326) 0x44735a CMP	$0x6,%EAX

(326) 0x44735d JBE	447d90

(326) 0x447363 MOVSXD	0x1a0(%RSP),%RAX

(326) 0x44736b MOV	0x108(%RSP),%R9

(326) 0x447373 MOV	0x100(%RSP),%R13

(326) 0x44737b MOV	%ESI,0xc0(%RSP)

(326) 0x447382 LEA	(%R8,%RAX,1),%R10

(326) 0x447386 VMOVQ	%XMM28,%R8

(326) 0x44738c ADD	%RAX,%R9

(326) 0x44738f ADD	%RAX,%R11

(326) 0x447392 SAL	$0x3,%R10

(326) 0x447396 LEA	(%R8,%R10,1),%RDX

(326) 0x44739a VMOVQ	%RDX,%XMM4

(326) 0x44739f MOV	0x110(%RSP),%RDX

(326) 0x4473a7 SAL	$0x3,%R9

(326) 0x4473ab SAL	$0x3,%R11

(326) 0x4473af ADD	%RAX,%RDX

(326) 0x4473b2 ADD	%R9,%R8

(326) 0x4473b5 LEA	(%R13,%R11,1),%RCX

(326) 0x4473ba LEA	0x8(%R13,%R11,1),%R11

(326) 0x4473bf SAL	$0x3,%RDX

(326) 0x4473c3 VMOVQ	%R8,%XMM19

(326) 0x4473c9 VMOVQ	%XMM30,%R8

(326) 0x4473cf ADD	%RDX,%R8

(326) 0x4473d2 VMOVQ	%RCX,%XMM21

(326) 0x4473d8 LEA	(%R14,%RAX,1),%RCX

(326) 0x4473dc VMOVQ	%R11,%XMM16

(326) 0x4473e2 SAL	$0x3,%RCX

(326) 0x4473e6 VMOVQ	%R8,%XMM17

(326) 0x4473ec VMOVQ	%XMM28,%R8

(326) 0x4473f2 LEA	0x8(%R8,%R10,1),%R13

(326) 0x4473f7 LEA	0x8(%R8,%R9,1),%R10

(326) 0x4473fc VMOVQ	%XMM30,%R9

(326) 0x447402 LEA	(%R12,%RAX,1),%R8

(326) 0x447406 LEA	0x8(%R9,%RCX,1),%R11

(326) 0x44740b LEA	0x8(%R9,%RDX,1),%RDX

(326) 0x447410 LEA	(%R15,%RAX,1),%R9

(326) 0x447414 MOV	0x118(%RSP),%R12

(326) 0x44741c VMOVQ	%XMM30,%R14

(326) 0x447422 VMOVQ	%RDX,%XMM10

(326) 0x447427 SAL	$0x3,%R9

(326) 0x44742b VMOVQ	%R10,%XMM14

(326) 0x447430 VMOVQ	%XMM31,%R15

(326) 0x447436 ADD	%RCX,%R14

(326) 0x447439 VMOVQ	%XMM31,%RCX

(326) 0x44743f ADD	%R9,%R15

(326) 0x447442 LEA	0x8(%RCX,%R9,1),%RDX

(326) 0x447447 MOV	0x120(%RSP),%RCX

(326) 0x44744f LEA	(%R12,%R8,8),%R10

(326) 0x447453 LEA	(%RDI,%RAX,1),%R8

(326) 0x447457 VMOVQ	%RDX,%XMM24

(326) 0x44745d VMOVQ	%XMM26,%RDI

(326) 0x447463 SAL	$0x3,%R8

(326) 0x447467 VMOVQ	%R10,%XMM9

(326) 0x44746c LEA	0x8(%RDI,%R8,1),%R9

(326) 0x447471 LEA	(%RDI,%R8,1),%R10

(326) 0x447475 MOV	0x128(%RSP),%R8

(326) 0x44747d LEA	(%RCX,%RAX,1),%RDX

(326) 0x447481 VMOVQ	%XMM31,%RCX

(326) 0x447487 VMOVQ	%R9,%XMM23

(326) 0x44748d LEA	(%R12,%RDX,8),%R12

(326) 0x447491 VMOVQ	%R12,%XMM22

(326) 0x447497 MOV	0x130(%RSP),%R12

(326) 0x44749f LEA	(%R8,%RAX,1),%RDI

(326) 0x4474a3 SAL	$0x3,%RDI

(326) 0x4474a7 LEA	(%R12,%RAX,1),%R8

(326) 0x4474ab LEA	(%RCX,%RDI,1),%R9

(326) 0x4474af LEA	0x8(%RCX,%RDI,1),%RDX

(326) 0x4474b4 VMOVQ	%XMM26,%RCX

(326) 0x4474ba SAL	$0x3,%R8

(326) 0x4474be VMOVQ	%XMM26,%RDI

(326) 0x4474c4 VMOVQ	%RDX,%XMM25

(326) 0x4474ca ADD	%R8,%RDI

(326) 0x4474cd LEA	0x8(%RCX,%R8,1),%RDX

(326) 0x4474d2 MOV	0x140(%RSP),%R8

(326) 0x4474da LEA	(%RBX,%RAX,1),%R12

(326) 0x4474de VMOVQ	%RDX,%XMM29

(326) 0x4474e4 MOV	0x138(%RSP),%RBX

(326) 0x4474ec MOV	0x148(%RSP),%RDX

(326) 0x4474f4 LEA	(%R8,%RAX,1),%RCX

(326) 0x4474f8 MOV	0x150(%RSP),%R8

(326) 0x447500 LEA	(%RBX,%R12,8),%R12

(326) 0x447504 LEA	(%RDX,%RCX,8),%RBX

(326) 0x447508 MOV	0x158(%RSP),%RCX

(326) 0x447510 ADD	%RAX,%R8

(326) 0x447513 LEA	(%RCX,%R8,8),%RDX

(326) 0x447517 MOV	0x160(%RSP),%RCX

(326) 0x44751f MOV	0x198(%RSP),%R8

(326) 0x447527 ADD	%RAX,%RCX

(326) 0x44752a LEA	(%R8,%RCX,8),%RCX

(326) 0x44752e MOV	0x188(%RSP),%R8

(326) 0x447536 VMOVQ	%RCX,%XMM20

(326) 0x44753c MOV	0x190(%RSP),%RCX

(326) 0x447544 ADD	%RAX,%RCX

(326) 0x447547 LEA	(%R8,%RCX,8),%RCX

(326) 0x44754b MOV	0x178(%RSP),%R8

(326) 0x447553 VMOVQ	%RCX,%XMM18

(326) 0x447559 MOV	0x180(%RSP),%RCX

(326) 0x447561 ADD	%RAX,%RCX

(326) 0x447564 LEA	(%R8,%RCX,8),%RCX

(326) 0x447568 MOV	0x170(%RSP),%R8

(326) 0x447570 VMOVQ	%RCX,%XMM15

(326) 0x447575 MOV	0x168(%RSP),%RCX

(326) 0x44757d ADD	%R8,%RAX

(326) 0x447580 MOV	%ESI,%R8D

(326) 0x447583 MOV	%R10,%RSI

(326) 0x447586 MOV	%R14,%R10

(326) 0x447589 SHR	$0x3,%R8D

(326) 0x44758d SAL	$0x6,%R8

(326) 0x447591 LEA	(%RCX,%RAX,8),%RAX

(326) 0x447595 MOV	%R9,%R14

(326) 0x447598 MOV	%R8,0x1b8(%RSP)

(326) 0x4475a0 MOV	%R13,%R9

(326) 0x4475a3 VMOVQ	%RAX,%XMM13

(326) 0x4475a8 MOV	%R11,%R8

(326) 0x4475ab XOR	%EAX,%EAX

(326) 0x4475ad MOV	%RDI,%R11

(326) 0x4475b0 VMOVQ	%XMM4,%R13

(326) 0x4475b5 MOV	%R15,%RDI

(326) 0x4475b8 VMOVQ	%XMM22,%R15

(326) 0x4475be XCHG	%AX,%AX

  (328) 0x4475c0 VMOVQ	%XMM19,%RCX

  (328) 0x4475c6 VMOVUPD	(%R13,%RAX,1),%ZMM1

  (328) 0x4475ce VMOVUPD	(%R10,%RAX,1),%ZMM3

  (328) 0x4475d5 VMOVUPD	(%RDI,%RAX,1),%ZMM4

  (328) 0x4475dc VADDPD	(%RCX,%RAX,1),%ZMM1,%ZMM5

  (328) 0x4475e3 VMOVQ	%XMM17,%RCX

  (328) 0x4475e9 VADDPD	(%RCX,%RAX,1),%ZMM3,%ZMM8

  (328) 0x4475f0 VMOVQ	%XMM24,%RCX

  (328) 0x4475f6 VADDPD	(%RCX,%RAX,1),%ZMM4,%ZMM3

  (328) 0x4475fd VMOVQ	%XMM23,%RCX

  (328) 0x447603 VADDPD	%ZMM8,%ZMM5,%ZMM1

  (328) 0x447609 VMOVUPD	(%RSI,%RAX,1),%ZMM5

  (328) 0x447610 VADDPD	(%RCX,%RAX,1),%ZMM5,%ZMM8

  (328) 0x447617 VMOVQ	%XMM9,%RCX

  (328) 0x44761c VMOVUPD	(%R9,%RAX,1),%ZMM5

  (328) 0x447623 VADDPD	%ZMM8,%ZMM3,%ZMM4

  (328) 0x447629 VMULPD	(%RCX,%RAX,1),%ZMM4,%ZMM3

  (328) 0x447630 VMOVQ	%XMM14,%RCX

  (328) 0x447635 VMOVUPD	(%R8,%RAX,1),%ZMM8

  (328) 0x44763c VADDPD	(%RCX,%RAX,1),%ZMM5,%ZMM4

  (328) 0x447643 VMOVQ	%XMM10,%RCX

  (328) 0x447648 VADDPD	(%RCX,%RAX,1),%ZMM8,%ZMM5

  (328) 0x44764f VMOVQ	%XMM25,%RCX

  (328) 0x447655 VADDPD	%ZMM5,%ZMM4,%ZMM8

  (328) 0x44765b VMOVUPD	(%R14,%RAX,1),%ZMM4

  (328) 0x447662 VADDPD	(%RCX,%RAX,1),%ZMM4,%ZMM5

  (328) 0x447669 VMOVQ	%XMM29,%RCX

  (328) 0x44766f VMOVUPD	(%R11,%RAX,1),%ZMM4

  (328) 0x447676 VADDPD	(%RCX,%RAX,1),%ZMM4,%ZMM4

  (328) 0x44767d VMOVQ	%XMM16,%RCX

  (328) 0x447683 VADDPD	%ZMM4,%ZMM5,%ZMM5

  (328) 0x447689 VMULPD	(%R15,%RAX,1),%ZMM5,%ZMM4

  (328) 0x447690 VFMADD231PD	(%RCX,%RAX,1),%ZMM8,%ZMM4

  (328) 0x447697 VMOVQ	%XMM21,%RCX

  (328) 0x44769d VMOVUPD	(%RBX,%RAX,1),%ZMM8

  (328) 0x4476a4 VFMADD132PD	(%RCX,%RAX,1),%ZMM3,%ZMM1

  (328) 0x4476ab VSUBPD	%ZMM1,%ZMM4,%ZMM1

  (328) 0x4476b1 VMOVQ	%XMM20,%RCX

  (328) 0x4476b7 VMOVUPD	(%R12,%RAX,1),%ZMM4

  (328) 0x4476be VMULPD	%ZMM7,%ZMM1,%ZMM5

  (328) 0x4476c4 VADDPD	(%RCX,%RAX,1),%ZMM8,%ZMM1

  (328) 0x4476cb VMOVQ	%XMM18,%RCX

  (328) 0x4476d1 VDIVPD	(%RDX,%RAX,1),%ZMM1,%ZMM8

  (328) 0x4476d8 VADDPD	%ZMM5,%ZMM4,%ZMM3

  (328) 0x4476de VDIVPD	%ZMM3,%ZMM4,%ZMM3

  (328) 0x4476e4 VDIVPD	%ZMM4,%ZMM6,%ZMM4

  (328) 0x4476ea VMULPD	%ZMM4,%ZMM8,%ZMM1

  (328) 0x4476f0 VFNMADD213PD	(%RCX,%RAX,1),%ZMM1,%ZMM5

  (328) 0x4476f7 VMOVQ	%XMM15,%RCX

  (328) 0x4476fc VMOVUPD	%ZMM5,(%RCX,%RAX,1)

  (328) 0x447703 VMULPD	(%RDX,%RAX,1),%ZMM3,%ZMM5

  (328) 0x44770a VMOVQ	%XMM13,%RCX

  (328) 0x44770f VMOVUPD	%ZMM5,(%RCX,%RAX,1)

  (328) 0x447716 MOV	0x1b8(%RSP),%RCX

  (328) 0x44771e ADD	$0x40,%RAX

  (328) 0x447722 CMP	%RCX,%RAX

  (328) 0x447725 JNE	4475c0

(326) 0x44772b MOV	0xc0(%RSP),%ESI

(326) 0x447732 MOV	0x1a0(%RSP),%R12D

(326) 0x44773a MOV	%ESI,%EAX

(326) 0x44773c AND	$-0x8,%EAX

(326) 0x44773f ADD	%EAX,0x1b4(%RSP)

(326) 0x447746 ADD	%EAX,%R12D

(326) 0x447749 MOV	%R12D,0x1b8(%RSP)

(326) 0x447751 TEST	$0x7,%SIL

(326) 0x447755 JE	447d13

(326) 0x44775b SUB	%EAX,%ESI

(326) 0x44775d LEA	-0x1(%RSI),%EBX

(326) 0x447760 MOV	%ESI,%R15D

(326) 0x447763 CMP	$0x2,%EBX

(326) 0x447766 JBE	447a65

(326) 0x44776c MOVSXD	0x1a0(%RSP),%RDX

(326) 0x447774 MOV	0xd8(%RSP),%R14

(326) 0x44777c MOV	0x110(%RSP),%R13

(326) 0x447784 MOV	0xe8(%RSP),%R11

(326) 0x44778c MOV	0xc8(%RSP),%RSI

(326) 0x447794 MOV	0xf0(%RSP),%RCX

(326) 0x44779c MOV	0x128(%RSP),%R12

(326) 0x4477a4 MOV	0xd0(%RSP),%RBX

(326) 0x4477ac MOV	0x108(%RSP),%RDI

(326) 0x4477b4 LEA	(%R14,%RDX,1),%R9

(326) 0x4477b8 MOV	0x130(%RSP),%R14

(326) 0x4477c0 ADD	%RDX,%R13

(326) 0x4477c3 ADD	%RAX,%R13

(326) 0x4477c6 LEA	(%R9,%RAX,1),%R8

(326) 0x4477ca LEA	(%RSI,%RDX,1),%R10

(326) 0x4477ce LEA	(%R12,%RDX,1),%R12

(326) 0x4477d2 SAL	$0x3,%R13

(326) 0x4477d6 MOV	%R13,0x1a0(%RSP)

(326) 0x4477de LEA	(%R11,%RDX,1),%R13

(326) 0x4477e2 MOV	0xf8(%RSP),%R11

(326) 0x4477ea LEA	(%R10,%RAX,1),%RSI

(326) 0x4477ee LEA	(%R14,%RDX,1),%R9

(326) 0x4477f2 MOV	0x140(%RSP),%R14

(326) 0x4477fa LEA	(%RCX,%RDX,1),%R10

(326) 0x4477fe ADD	%RAX,%R13

(326) 0x447801 ADD	%RAX,%R10

(326) 0x447804 ADD	%RAX,%R9

(326) 0x447807 ADD	%RAX,%R12

(326) 0x44780a ADD	%RDX,%RBX

(326) 0x44780d SAL	$0x3,%R10

(326) 0x447811 LEA	(%R11,%RDX,1),%RCX

(326) 0x447815 ADD	%RDX,%RDI

(326) 0x447818 ADD	%RAX,%RBX

(326) 0x44781b LEA	(%R14,%RDX,1),%R11

(326) 0x44781f MOV	0x150(%RSP),%R14

(326) 0x447827 ADD	%RAX,%RCX

(326) 0x44782a ADD	%RAX,%RDI

(326) 0x44782d MOV	%RCX,0xc0(%RSP)

(326) 0x447835 LEA	(%R11,%RAX,1),%RCX

(326) 0x447839 MOV	0x158(%RSP),%R11

(326) 0x447841 MOV	%RCX,0xb0(%RSP)

(326) 0x447849 SAL	$0x3,%R9

(326) 0x44784d LEA	(%R14,%RDX,1),%RCX

(326) 0x447851 MOV	0x160(%RSP),%R14

(326) 0x447859 ADD	%RAX,%RCX

(326) 0x44785c LEA	(%R11,%RCX,8),%R11

(326) 0x447860 MOV	0x190(%RSP),%RCX

(326) 0x447868 SAL	$0x3,%RDI

(326) 0x44786c ADD	%RDX,%R14

(326) 0x44786f ADD	%RDX,%RCX

(326) 0x447872 ADD	%RAX,%R14

(326) 0x447875 ADD	%RAX,%RCX

(326) 0x447878 MOV	%R14,0xa8(%RSP)

(326) 0x447880 MOV	0x180(%RSP),%R14

(326) 0x447888 MOV	%RCX,0xa0(%RSP)

(326) 0x447890 MOV	0x170(%RSP),%RCX

(326) 0x447898 ADD	%RDX,%R14

(326) 0x44789b ADD	%RDX,%RCX

(326) 0x44789e ADD	%RAX,%R14

(326) 0x4478a1 ADD	%RAX,%RCX

(326) 0x4478a4 MOV	%R14,0x98(%RSP)

(326) 0x4478ac MOV	0xe0(%RSP),%R14

(326) 0x4478b4 MOV	%RCX,0x90(%RSP)

(326) 0x4478bc VMOVQ	%XMM26,%RCX

(326) 0x4478c2 VMOVUPD	0x8(%RCX,%R10,1),%YMM14

(326) 0x4478c9 VMOVQ	%XMM31,%RCX

(326) 0x4478cf VADDPD	0x8(%RCX,%R13,8),%YMM14,%YMM10

(326) 0x4478d6 VMOVQ	%XMM26,%RCX

(326) 0x4478dc VMOVUPD	(%RCX,%R10,1),%YMM9

(326) 0x4478e2 VMOVQ	%XMM31,%R10

(326) 0x4478e8 VMOVUPD	0x8(%RCX,%R9,1),%YMM3

(326) 0x4478ef VADDPD	(%R10,%R13,8),%YMM9,%YMM15

(326) 0x4478f5 VADDPD	0x8(%R10,%R12,8),%YMM3,%YMM4

(326) 0x4478fc VMOVUPD	(%RCX,%R9,1),%YMM8

(326) 0x447902 ADD	%RDX,%R14

(326) 0x447905 VADDPD	(%R10,%R12,8),%YMM8,%YMM1

(326) 0x44790b MOV	0x120(%RSP),%R12

(326) 0x447913 ADD	%RAX,%R14

(326) 0x447916 MOV	0x1a0(%RSP),%RCX

(326) 0x44791e VMOVQ	%XMM30,%R13

(326) 0x447924 MOV	0x198(%RSP),%R9

(326) 0x44792c MOV	0x178(%RSP),%R10

(326) 0x447934 ADD	%R12,%RDX

(326) 0x447937 MOV	0xa8(%RSP),%R12

(326) 0x44793f ADD	%RAX,%RDX

(326) 0x447942 MOV	0x118(%RSP),%RAX

(326) 0x44794a VADDPD	%YMM15,%YMM10,%YMM13

(326) 0x44794f VMOVUPD	(%R13,%RCX,1),%YMM15

(326) 0x447956 VADDPD	(%R13,%R8,8),%YMM15,%YMM3

(326) 0x44795d VADDPD	%YMM1,%YMM4,%YMM5

(326) 0x447961 VMULPD	(%RAX,%RDX,8),%YMM5,%YMM14

(326) 0x447966 VMOVQ	%XMM28,%RDX

(326) 0x44796c VMOVUPD	0x8(%R13,%RCX,1),%YMM5

(326) 0x447973 MOV	0xa0(%RSP),%RCX

(326) 0x44797b VMOVUPD	(%RDX,%RDI,1),%YMM10

(326) 0x447980 VMOVUPD	0x8(%RDX,%RDI,1),%YMM8

(326) 0x447986 VADDPD	(%RDX,%RBX,8),%YMM10,%YMM9

(326) 0x44798b VADDPD	0x8(%RDX,%RBX,8),%YMM8,%YMM1

(326) 0x447991 VADDPD	0x8(%R13,%R8,8),%YMM5,%YMM10

(326) 0x447998 MOV	0x100(%RSP),%R8

(326) 0x4479a0 VFNMADD132PD	(%RAX,%R14,8),%YMM14,%YMM13

(326) 0x4479a6 MOV	0x148(%RSP),%RDX

(326) 0x4479ae MOV	0xc0(%RSP),%R14

(326) 0x4479b6 MOV	0xb0(%RSP),%RAX

(326) 0x4479be VMOVUPD	(%R9,%R12,8),%YMM8

(326) 0x4479c4 MOV	0x188(%RSP),%R13

(326) 0x4479cc VADDPD	(%RDX,%RAX,8),%YMM8,%YMM5

(326) 0x4479d1 VADDPD	%YMM3,%YMM9,%YMM4

(326) 0x4479d5 VADDPD	%YMM10,%YMM1,%YMM9

(326) 0x4479da VMULPD	0x8(%R8,%RSI,8),%YMM9,%YMM15

(326) 0x4479e1 VDIVPD	(%R11),%YMM5,%YMM10

(326) 0x4479e6 VFNMADD132PD	(%R8,%RSI,8),%YMM15,%YMM4

(326) 0x4479ec MOV	0x138(%RSP),%RSI

(326) 0x4479f4 VADDPD	%YMM13,%YMM4,%YMM13

(326) 0x4479f9 MOV	%R15D,%R8D

(326) 0x4479fc AND	$-0x4,%R8D

(326) 0x447a00 VMULPD	%YMM0,%YMM13,%YMM14

(326) 0x447a04 VMOVUPD	(%RSI,%R14,8),%YMM3

(326) 0x447a0a VDIVPD	%YMM3,%YMM11,%YMM9

(326) 0x447a0e VADDPD	%YMM3,%YMM14,%YMM4

(326) 0x447a12 VDIVPD	%YMM4,%YMM3,%YMM1

(326) 0x447a16 VMULPD	%YMM9,%YMM10,%YMM15

(326) 0x447a1b VFNMADD213PD	(%R13,%RCX,8),%YMM15,%YMM14

(326) 0x447a22 MOV	0x98(%RSP),%RDI

(326) 0x447a2a MOV	0x90(%RSP),%RBX

(326) 0x447a32 ADD	%R8D,0x1b8(%RSP)

(326) 0x447a3a ADD	%R8D,0x1b4(%RSP)

(326) 0x447a42 AND	$0x3,%R15D

(326) 0x447a46 VMOVUPD	%YMM14,(%R10,%RDI,8)

(326) 0x447a4c VMULPD	(%R11),%YMM1,%YMM13

(326) 0x447a51 MOV	0x168(%RSP),%R11

(326) 0x447a59 VMOVUPD	%YMM13,(%R11,%RBX,8)

(326) 0x447a5f JE	447d13

(326) 0x447a65 MOVSXD	0x1b8(%RSP),%R15

(326) 0x447a6d MOV	0x100(%RSP),%R14

(326) 0x447a75 MOV	0xc8(%RSP),%R9

(326) 0x447a7d MOV	0x118(%RSP),%R8

(326) 0x447a85 MOV	0xd0(%RSP),%RDX

(326) 0x447a8d MOV	0x110(%RSP),%R11

(326) 0x447a95 MOV	0xd8(%RSP),%R10

(326) 0x447a9d VMOVQ	%XMM28,%R12

(326) 0x447aa3 VMOVQ	%XMM30,%R13

(326) 0x447aa9 MOV	0x108(%RSP),%RAX

(326) 0x447ab1 MOV	%R15,%RSI

(326) 0x447ab4 MOV	%R15,0x1a0(%RSP)

(326) 0x447abc MOV	0xe0(%RSP),%R15

(326) 0x447ac4 LEA	(%R14,%R9,8),%RDI

(326) 0x447ac8 LEA	(%R12,%RDX,8),%RCX

(326) 0x447acc LEA	(%R13,%R11,8),%RBX

(326) 0x447ad1 MOV	0xe8(%RSP),%RDX

(326) 0x447ad9 LEA	(%R13,%R10,8),%R10

(326) 0x447ade MOV	0xf0(%RSP),%R13

(326) 0x447ae6 LEA	(%R12,%RAX,8),%R9

(326) 0x447aea VMOVQ	%XMM31,%R12

(326) 0x447af0 VMOVQ	%XMM26,%RAX

(326) 0x447af6 LEA	(%R8,%R15,8),%R14

(326) 0x447afa VMOVQ	%R14,%XMM10

(326) 0x447aff MOV	0x120(%RSP),%R14

(326) 0x447b07 LEA	(%R12,%RDX,8),%R11

(326) 0x447b0b MOV	0x128(%RSP),%RDX

(326) 0x447b13 LEA	(%RAX,%R13,8),%R15

(326) 0x447b17 MOV	0x130(%RSP),%R13

(326) 0x447b1f VMOVQ	%R15,%XMM3

(326) 0x447b24 LEA	(%R8,%R14,8),%R8

(326) 0x447b28 MOV	0x138(%RSP),%R14

(326) 0x447b30 LEA	(%R12,%RDX,8),%R15

(326) 0x447b34 MOV	0x140(%RSP),%RDX

(326) 0x447b3c VMOVQ	%R8,%XMM8

(326) 0x447b41 MOV	0xf8(%RSP),%R8

(326) 0x447b49 MOV	0x148(%RSP),%R12

(326) 0x447b51 LEA	(%RAX,%R13,8),%R13

(326) 0x447b55 MOV	0x158(%RSP),%RAX

(326) 0x447b5d LEA	(%R14,%R8,8),%R14

(326) 0x447b61 MOV	0x150(%RSP),%R8

(326) 0x447b69 LEA	(%R12,%RDX,8),%R12

(326) 0x447b6d MOV	0x160(%RSP),%RDX

(326) 0x447b75 VMOVQ	%R12,%XMM28

(326) 0x447b7b LEA	(%RAX,%R8,8),%R8

(326) 0x447b7f MOV	0x198(%RSP),%RAX

(326) 0x447b87 LEA	(%RAX,%RDX,8),%RAX

(326) 0x447b8b MOV	0x190(%RSP),%RDX

(326) 0x447b93 VMOVQ	%RAX,%XMM14

(326) 0x447b98 MOV	0x188(%RSP),%RAX

(326) 0x447ba0 LEA	(%RAX,%RDX,8),%RAX

(326) 0x447ba4 MOV	0x180(%RSP),%RDX

(326) 0x447bac VMOVQ	%RAX,%XMM15

(326) 0x447bb1 MOV	0x178(%RSP),%RAX

(326) 0x447bb9 LEA	(%RAX,%RDX,8),%RAX

(326) 0x447bbd MOV	0x170(%RSP),%RDX

(326) 0x447bc5 VMOVQ	%RAX,%XMM27

(326) 0x447bcb MOV	0x168(%RSP),%RAX

(326) 0x447bd3 LEA	(%RAX,%RDX,8),%RAX

(326) 0x447bd7 MOV	0x1b4(%RSP),%EDX

(326) 0x447bde VMOVQ	%RAX,%XMM4

(326) 0x447be3 MOV	0x1a0(%RSP),%RAX

(326) 0x447beb SUB	%ESI,%EDX

(326) 0x447bed MOV	%EDX,0x1b8(%RSP)

(326) 0x447bf4 VMOVQ	%XMM3,%RDX

  (327) 0x447bf9 VMOVQ	%XMM10,%RSI

  (327) 0x447bfe VMOVQ	%XMM8,%R12

  (327) 0x447c03 VMOVSD	(%R9,%RAX,8),%XMM1

  (327) 0x447c09 VMOVSD	(%RBX,%RAX,8),%XMM9

  (327) 0x447c0e VADDSD	(%RCX,%RAX,8),%XMM1,%XMM5

  (327) 0x447c13 VADDSD	(%R10,%RAX,8),%XMM9,%XMM13

  (327) 0x447c19 VMOVSD	0x8(%R11,%RAX,8),%XMM3

  (327) 0x447c20 VMOVSD	0x8(%RDX,%RAX,8),%XMM1

  (327) 0x447c26 VADDSD	%XMM13,%XMM5,%XMM13

  (327) 0x447c2b VADDSD	(%RDX,%RAX,8),%XMM1,%XMM9

  (327) 0x447c30 VADDSD	(%R11,%RAX,8),%XMM3,%XMM5

  (327) 0x447c36 VADDSD	%XMM9,%XMM5,%XMM3

  (327) 0x447c3b VMOVSD	0x8(%R9,%RAX,8),%XMM5

  (327) 0x447c42 VMULSD	(%RSI,%RAX,8),%XMM3,%XMM3

  (327) 0x447c47 VADDSD	0x8(%RCX,%RAX,8),%XMM5,%XMM1

  (327) 0x447c4d VMOVSD	0x8(%R10,%RAX,8),%XMM9

  (327) 0x447c54 VMOVQ	%XMM28,%RSI

  (327) 0x447c5a VADDSD	0x8(%RBX,%RAX,8),%XMM9,%XMM5

  (327) 0x447c60 VADDSD	%XMM5,%XMM1,%XMM9

  (327) 0x447c64 VMOVSD	(%R15,%RAX,8),%XMM1

  (327) 0x447c6a VMOVSD	(%R13,%RAX,8),%XMM5

  (327) 0x447c71 VADDSD	0x8(%R15,%RAX,8),%XMM1,%XMM1

  (327) 0x447c78 VADDSD	0x8(%R13,%RAX,8),%XMM5,%XMM5

  (327) 0x447c7f VADDSD	%XMM5,%XMM1,%XMM1

  (327) 0x447c83 VMULSD	(%R12,%RAX,8),%XMM1,%XMM1

  (327) 0x447c89 VMOVQ	%XMM14,%R12

  (327) 0x447c8e VFMADD231SD	0x8(%RDI,%RAX,8),%XMM9,%XMM1

  (327) 0x447c95 VFMADD132SD	(%RDI,%RAX,8),%XMM3,%XMM13

  (327) 0x447c9b VMOVSD	(%R14,%RAX,8),%XMM9

  (327) 0x447ca1 VSUBSD	%XMM13,%XMM1,%XMM3

  (327) 0x447ca6 VMOVSD	(%RSI,%RAX,8),%XMM1

  (327) 0x447cab VMULSD	%XMM2,%XMM3,%XMM13

  (327) 0x447caf VMOVQ	%XMM15,%RSI

  (327) 0x447cb4 VADDSD	%XMM9,%XMM13,%XMM5

  (327) 0x447cb9 VDIVSD	%XMM5,%XMM9,%XMM3

  (327) 0x447cbd VADDSD	(%R12,%RAX,8),%XMM1,%XMM5

  (327) 0x447cc3 VMOVQ	%XMM27,%R12

  (327) 0x447cc9 VDIVSD	(%R8,%RAX,8),%XMM5,%XMM1

  (327) 0x447ccf VDIVSD	%XMM9,%XMM12,%XMM9

  (327) 0x447cd4 VMULSD	%XMM9,%XMM1,%XMM5

  (327) 0x447cd9 VFNMADD213SD	(%RSI,%RAX,8),%XMM5,%XMM13

  (327) 0x447cdf VMOVQ	%XMM4,%RSI

  (327) 0x447ce4 VMOVSD	%XMM13,(%R12,%RAX,8)

  (327) 0x447cea MOV	0x1b8(%RSP),%R12D

  (327) 0x447cf2 VMULSD	(%R8,%RAX,8),%XMM3,%XMM13

  (327) 0x447cf8 VMOVSD	%XMM13,(%RSI,%RAX,8)

  (327) 0x447cfd MOV	0x1b0(%RSP),%ESI

  (327) 0x447d04 INC	%RAX

  (327) 0x447d07 ADD	%EAX,%R12D

  (327) 0x447d0a CMP	%ESI,%R12D

  (327) 0x447d0d JB	447bf9

(326) 0x447d13 MOV	0x1b0(%RSP),%EDI

(326) 0x447d1a MOV	%EDI,0x1b4(%RSP)

(326) 0x447d21 INCQ	0x1a8(%RSP)

(326) 0x447d29 MOV	0x1a8(%RSP),%RCX

(326) 0x447d31 CMP	%ECX,0xb8(%RSP)

(326) 0x447d38 JLE	447d70

(326) 0x447d3a MOV	0x88(%RSP),%ECX

(326) 0x447d41 MOV	0x1b4(%RSP),%R9D

(326) 0x447d49 MOV	0x8c(%RSP),%R10D

(326) 0x447d51 MOV	0xbc(%RSP),%EDX

(326) 0x447d58 SUB	%R9D,%ECX

(326) 0x447d5b MOV	%R10D,0x1a0(%RSP)

(326) 0x447d63 JMP	447150

0x447d68 NOPL	(%RAX,%RAX,1)

0x447d70 VZEROUPPER

0x447d73 LEA	-0x28(%RBP),%RSP

0x447d77 POP	%RBX

0x447d78 POP	%R12

0x447d7a POP	%R13

0x447d7c POP	%R14

0x447d7e POP	%R15

0x447d80 POP	%RBP

0x447d81 RET

0x447d82 NOPW	%CS:(%RAX,%RAX,1)

0x447d8d NOPL	(%RAX)

(326) 0x447d90 MOV	0x1a0(%RSP),%EBX

(326) 0x447d97 XOR	%EAX,%EAX

(326) 0x447d99 MOV	%EBX,0x1b8(%RSP)

(326) 0x447da0 JMP	44775b

0x447da5 INC	%ECX

0x447da7 XOR	%EDX,%EDX

0x447da9 JMP	447051

0x447dae XCHG	%AX,%AX

Coverage (%)	Name	Source Location	Module
►96.57+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.26+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	PdV(global_variables&, bool)	PdV.cpp:103	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.13 to 2.50 cycles (5.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 13.13 to 1.11 cycles (11.83x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:72

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:83

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 156 bytes (19 double precision FP elements). The binary function is storing 136 bytes (17 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	107
nb uops	105
loop length	451
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	2
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.13 cycles
front end	13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	11.25	11.25	11.25	11.25	0.50	2.50	2.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	11.25	11.25	11.25	11.25	0.50	2.50	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	13.13
Dispatch	11.25
DIV/SQRT	12.00
Overall L1	13.13

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	10%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.13 cycles. At this rate:

4% of peak load performance is reached (11.89 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 446fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x1c0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x7c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x74(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %ESI,0x8c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 447d73 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xdb3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R12D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 447d73 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xdb3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,0xbc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xbc(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 447da5 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xde5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%RAX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x1b4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R9D,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R9D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 447d73 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xdb3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x8c(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x8(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x50(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
DIVL 0xbc(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV 0x58(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x68(%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVSD 0x1d5f6(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%RBX),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %R11,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x30(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R14,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10D,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x20(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTQ																				scal (12.5%)
MOV %R15,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x1a8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x1c855(%RIP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM12,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM12,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 447051 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x91>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	PdV.cpp:69-83
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:69-83
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.13 to 2.50 cycles (5.25x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:71
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:72

Conversion instructions

Detected expensive conversion instructions.

Details

CLTQ: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:83

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 156 bytes (19 double precision FP elements). The binary function is storing 136 bytes (17 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	107
nb uops	105
loop length	451
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	2
nb stack references	21

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.13 cycles
front end	13.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	11.25	11.25	11.25	11.25	0.50	2.50	2.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	11.25	11.25	11.25	11.25	0.50	2.50	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	13.13
Dispatch	11.25
DIV/SQRT	12.00
Overall L1	13.13

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	10%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	10%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.13 cycles. At this rate:

4% of peak load performance is reached (11.89 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (10.36 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 446fc0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x1c0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x78(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x7c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x74(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %ESI,0x8c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 447d73 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xdb3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RDI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R12D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 447d73 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xdb3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %ECX,0xbc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0xbc(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 447da5 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xde5>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%RAX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x1b4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %R9D,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R9D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 447d73 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0xdb3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x8c(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x8(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x50(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
DIVL 0xbc(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV 0x58(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x60(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x68(%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVSD 0x1d5f6(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMULSD (%RBX),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
MOV %R11,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x30(%RBX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %RDI,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R14,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R10D,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
SUB %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x20(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CLTQ																				scal (12.5%)
MOV %R15,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x1a8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVSD 0x1c855(%RIP),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM12,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM12,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 447051 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.1+0x91>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	6.59	2.42
▼Loop 326 - PdV.cpp:71-83 - exec–	0.01	0.01
○Loop 328 - PdV.cpp:72-83 - exec	6.59	2.41
○Loop 327 - PdV.cpp:72-83 - exec	0.00	0.00

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