OV - exec - Function PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: PdV.cpp:48-63 [...]	Coverage (incl. loops): 5.62% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp: 48 - 63

--------------------------------------------------------------------------------

48: #pragma omp parallel for simd collapse(2)

49:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

50:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

51:         double left_flux = (xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel0(i, j) + xvel0(i + 0, j + 1))) * 0.25 * dt * 0.5;

52:         double right_flux =

53:             (xarea(i + 1, j + 0) * (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1) + xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1))) * 0.25 * dt *

54:             0.5;

55:         double bottom_flux = (yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel0(i, j) + yvel0(i + 1, j + 0))) * 0.25 * dt * 0.5;

56:         double top_flux = (yarea(i + 0, j + 1) * (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1) + yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1))) *

57:                           0.25 * dt * 0.5;

58:         double total_flux = right_flux - left_flux + top_flux - bottom_flux;

59:         double volume_change_s = volume(i, j) / (volume(i, j) + total_flux);

60:         double recip_volume = 1.0 / volume(i, j);

61:         double energy_change = (pressure(i, j) / density0(i, j) + viscosity(i, j) / density0(i, j)) * total_flux * recip_volume;

62:         energy1(i, j) = energy0(i, j) - energy_change;

63:         density1(i, j) = density0(i, j) * volume_change_s;

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x446440 PUSH	%RBP

0x446441 MOV	%RSP,%RBP

0x446444 PUSH	%R15

0x446446 PUSH	%R14

0x446448 PUSH	%R13

0x44644a PUSH	%R12

0x44644c PUSH	%RBX

0x44644d MOV	%RDI,%RBX

0x446450 AND	$-0x40,%RSP

0x446454 SUB	$0x140,%RSP

0x44645b MOV	0x68(%RDI),%EAX

0x44645e MOV	0x6c(%RDI),%EDX

0x446461 MOV	0x60(%RDI),%ESI

0x446464 MOV	0x64(%RBX),%ECX

0x446467 ADD	$0x2,%EDX

0x44646a LEA	0x1(%RSI),%EDI

0x44646d LEA	0x1(%RAX),%R12D

0x446471 MOV	%EDX,0x94(%RSP)

0x446478 MOV	%EDI,0x90(%RSP)

0x44647f CMP	%EDX,%R12D

0x446482 JGE	446f83

0x446488 MOV	%EDX,%R14D

0x44648b LEA	0x2(%RCX),%R15D

0x44648f SUB	%R12D,%R14D

0x446492 CMP	%R15D,%EDI

0x446495 JGE	446f83

0x44649b MOV	%R15D,%R8D

0x44649e SUB	%EDI,%R8D

0x4464a1 MOV	%R8D,0x120(%RSP)

0x4464a9 CALL	404630 <omp_get_num_threads@plt>

0x4464ae MOV	%EAX,%R13D

0x4464b1 CALL	404520 <omp_get_thread_num@plt>

0x4464b6 XOR	%EDX,%EDX

0x4464b8 MOV	%EAX,%R9D

0x4464bb MOV	0x120(%RSP),%EAX

0x4464c2 IMUL	%R14D,%EAX

0x4464c6 DIV	%R13D

0x4464c9 MOV	%EAX,%ESI

0x4464cb CMP	%EDX,%R9D

0x4464ce JB	446fb7

0x4464d4 IMUL	%ESI,%R9D

0x4464d8 LEA	(%R9,%RDX,1),%EAX

0x4464dc LEA	(%RSI,%RAX,1),%R10D

0x4464e0 MOV	%EAX,0x130(%RSP)

0x4464e7 MOV	%R10D,0x8c(%RSP)

0x4464ef CMP	%R10D,%EAX

0x4464f2 JAE	446f83

0x4464f8 XOR	%EDX,%EDX

0x4464fa MOV	0x90(%RSP),%R11D

0x446502 MOV	0x8(%RBX),%RDI

0x446506 MOV	0x10(%RBX),%R14

0x44650a DIVL	0x120(%RSP)

0x446511 MOV	%R15D,%ECX

0x446514 MOV	0x58(%RBX),%R8

0x446518 MOV	0x50(%RBX),%R15

0x44651c MOV	0x18(%RBX),%R13

0x446520 MOV	0x40(%RBX),%R9

0x446524 MOV	0x20(%RBX),%R10

0x446528 VMOVSD	0x1e390(%RIP),%XMM0

0x446530 VMULSD	(%RBX),%XMM0,%XMM2

0x446534 VMOVSD	0x1d452(%RIP),%XMM16

0x44653e VBROADCASTSD	%XMM2,%YMM0

0x446543 VBROADCASTSD	%XMM16,%YMM13

0x446549 VBROADCASTSD	%XMM2,%ZMM15

0x44654f VBROADCASTSD	%XMM16,%ZMM14

0x446555 MOV	%RDI,0x80(%RSP)

0x44655d MOV	0x38(%RBX),%RDI

0x446561 MOV	%R14,0x70(%RSP)

0x446566 MOV	%R15,0x78(%RSP)

0x44656b MOV	%R8,0x68(%RSP)

0x446570 MOV	%R13,0x60(%RSP)

0x446575 MOV	%R9,0x58(%RSP)

0x44657a MOV	%R10,0x50(%RSP)

0x44657f MOV	%RDI,0x38(%RSP)

0x446584 ADD	%EDX,%R11D

0x446587 MOV	0x48(%RBX),%RDX

0x44658b ADD	%R12D,%EAX

0x44658e SUB	%R11D,%ECX

0x446591 MOV	%R11D,0x118(%RSP)

0x446599 MOV	0x30(%RBX),%R11

0x44659d MOV	0x28(%RBX),%RBX

0x4465a1 MOVSXD	%EAX,%R14

0x4465a4 MOV	%RDX,0x48(%RSP)

0x4465a9 MOV	%R11,0x40(%RSP)

0x4465ae MOV	%RBX,0x30(%RSP)

0x4465b3 NOPW	%CS:(%RAX,%RAX,1)

0x4465be XCHG	%AX,%AX

(323) 0x4465c0 MOV	0x130(%RSP),%R12D

(323) 0x4465c8 CMP	%ECX,%ESI

(323) 0x4465ca CMOVBE	%ESI,%ECX

(323) 0x4465cd MOV	%ECX,0x128(%RSP)

(323) 0x4465d4 LEA	(%R12,%RCX,1),%ESI

(323) 0x4465d8 MOV	%ESI,0x124(%RSP)

(323) 0x4465df CMP	%ESI,%R12D

(323) 0x4465e2 JAE	446f3a

(323) 0x4465e8 MOV	0x70(%RSP),%R10

(323) 0x4465ed MOV	0x68(%RSP),%RBX

(323) 0x4465f2 MOV	0x80(%RSP),%RCX

(323) 0x4465fa MOV	%R14,%RDI

(323) 0x4465fd MOV	0x78(%RSP),%R15

(323) 0x446602 MOV	%R14,%RSI

(323) 0x446605 MOV	%R14,%R13

(323) 0x446608 MOV	(%R10),%RDX

(323) 0x44660b MOV	(%RBX),%R12

(323) 0x44660e MOV	(%RCX),%RAX

(323) 0x446611 VMOVQ	0x10(%RCX),%XMM20

(323) 0x446618 MOV	(%R15),%R8

(323) 0x44661b VMOVQ	0x10(%R15),%XMM18

(323) 0x446622 MOV	0x60(%RSP),%R15

(323) 0x446627 VMOVQ	0x10(%R10),%XMM19

(323) 0x44662e VMOVQ	0x10(%RBX),%XMM17

(323) 0x446635 IMUL	%RDX,%RDI

(323) 0x446639 IMUL	%R12,%RSI

(323) 0x44663d VMOVQ	0x10(%R15),%XMM30

(323) 0x446644 IMUL	%R8,%R13

(323) 0x446648 MOV	%RDI,%RCX

(323) 0x44664b VMOVQ	%RDI,%XMM22

(323) 0x446651 IMUL	%R14,%RAX

(323) 0x446655 ADD	%RDX,%RCX

(323) 0x446658 MOV	0x50(%RSP),%RDX

(323) 0x44665d ADD	%RSI,%R12

(323) 0x446660 VMOVQ	%RSI,%XMM21

(323) 0x446666 MOV	%R12,0xc0(%RSP)

(323) 0x44666e MOV	0x48(%RSP),%RSI

(323) 0x446673 LEA	(%R8,%R13,1),%R11

(323) 0x446677 VMOVQ	%R13,%XMM23

(323) 0x44667d MOV	0x58(%RSP),%R13

(323) 0x446682 MOV	%RCX,0xb8(%RSP)

(323) 0x44668a MOV	(%R15),%R8

(323) 0x44668d VMOVQ	%RAX,%XMM28

(323) 0x446693 MOV	%R11,0xa8(%RSP)

(323) 0x44669b MOV	(%RDX),%R12

(323) 0x44669e MOV	0x10(%RDX),%RDI

(323) 0x4466a2 MOV	0x10(%RSI),%RCX

(323) 0x4466a6 MOV	0x10(%R13),%R9

(323) 0x4466aa MOV	(%R13),%R10

(323) 0x4466ae IMUL	%R14,%R8

(323) 0x4466b2 IMUL	%R14,%R12

(323) 0x4466b6 MOV	%RDI,0xd8(%RSP)

(323) 0x4466be VMOVQ	%R8,%XMM29

(323) 0x4466c4 MOV	%RCX,0x110(%RSP)

(323) 0x4466cc MOV	%R9,0xc8(%RSP)

(323) 0x4466d4 IMUL	%R14,%R10

(323) 0x4466d8 MOV	%R12,0xd0(%RSP)

(323) 0x4466e0 MOV	(%RSI),%R12

(323) 0x4466e3 VMOVQ	%R10,%XMM31

(323) 0x4466e9 IMUL	%R14,%R12

(323) 0x4466ed MOV	%R12,0xb0(%RSP)

(323) 0x4466f5 MOV	0x40(%RSP),%RAX

(323) 0x4466fa MOV	0x30(%RSP),%R10

(323) 0x4466ff MOV	0x128(%RSP),%EBX

(323) 0x446706 MOV	0x10(%RAX),%R15

(323) 0x44670a MOV	(%RAX),%R8

(323) 0x44670d MOV	(%R10),%RDI

(323) 0x446710 MOV	0x10(%R10),%RDX

(323) 0x446714 LEA	-0x1(%RBX),%ESI

(323) 0x446717 MOV	%R15,0x100(%RSP)

(323) 0x44671f MOV	0x38(%RSP),%R15

(323) 0x446724 IMUL	%R14,%R8

(323) 0x446728 MOV	%RDX,0xe0(%RSP)

(323) 0x446730 IMUL	%R14,%RDI

(323) 0x446734 MOV	%R8,0x108(%RSP)

(323) 0x44673c MOV	%RDI,0xe8(%RSP)

(323) 0x446744 MOV	(%R15),%R9

(323) 0x446747 MOV	0x10(%R15),%R13

(323) 0x44674b IMUL	%R14,%R9

(323) 0x44674f MOV	%R13,0xf0(%RSP)

(323) 0x446757 MOV	%R9,0xf8(%RSP)

(323) 0x44675f CMP	$0x6,%ESI

(323) 0x446762 JBE	446fa0

(323) 0x446768 MOVSXD	0x118(%RSP),%RAX

(323) 0x446770 VMOVQ	%XMM28,%RCX

(323) 0x446776 VMOVQ	%XMM23,%R15

(323) 0x44677c MOV	%R14,0xa0(%RSP)

(323) 0x446784 VMOVQ	%XMM20,%RSI

(323) 0x44678a VMOVQ	%XMM18,%RDX

(323) 0x446790 VMOVAPD	%XMM2,%XMM26

(323) 0x446796 VMOVQ	%XMM20,%R8

(323) 0x44679c VMOVQ	%XMM18,%RBX

(323) 0x4467a2 LEA	(%RCX,%RAX,1),%R13

(323) 0x4467a6 LEA	(%R15,%RAX,1),%R10

(323) 0x4467aa LEA	(%R11,%RAX,1),%RDI

(323) 0x4467ae VMOVQ	%XMM17,%R11

(323) 0x4467b4 SAL	$0x3,%R13

(323) 0x4467b8 SAL	$0x3,%R10

(323) 0x4467bc LEA	0x8(%RSI,%R13,1),%R15

(323) 0x4467c1 VMOVQ	%XMM21,%RSI

(323) 0x4467c7 LEA	(%R8,%R13,1),%R9

(323) 0x4467cb LEA	(%RDX,%R10,1),%R8

(323) 0x4467cf SAL	$0x3,%RDI

(323) 0x4467d3 ADD	%RAX,%RSI

(323) 0x4467d6 LEA	0x8(%RDX,%R10,1),%R13

(323) 0x4467db LEA	0x8(%RDX,%RDI,1),%R10

(323) 0x4467e0 VMOVQ	%XMM22,%RDX

(323) 0x4467e6 SAL	$0x3,%RSI

(323) 0x4467ea VMOVQ	%R10,%XMM11

(323) 0x4467ef ADD	%RDI,%RBX

(323) 0x4467f2 ADD	%RAX,%RDX

(323) 0x4467f5 VMOVQ	%XMM19,%RDI

(323) 0x4467fb LEA	0x8(%R11,%RSI,1),%RCX

(323) 0x446800 VMOVQ	%RBX,%XMM8

(323) 0x446805 LEA	(%RDI,%RDX,8),%RBX

(323) 0x446809 LEA	(%R11,%RSI,1),%RDI

(323) 0x44680d MOV	0xc0(%RSP),%RSI

(323) 0x446815 MOV	0xb8(%RSP),%R10

(323) 0x44681d VMOVQ	%RCX,%XMM24

(323) 0x446823 VMOVQ	%RBX,%XMM6

(323) 0x446828 VMOVQ	%XMM19,%RBX

(323) 0x44682e LEA	(%RSI,%RAX,1),%RCX

(323) 0x446832 SAL	$0x3,%RCX

(323) 0x446836 LEA	(%R10,%RAX,1),%RDX

(323) 0x44683a LEA	0x8(%R11,%RCX,1),%R10

(323) 0x44683f LEA	(%R11,%RCX,1),%RSI

(323) 0x446843 VMOVQ	%XMM30,%R11

(323) 0x446849 VMOVQ	%R10,%XMM27

(323) 0x44684f MOV	0xc8(%RSP),%R10

(323) 0x446857 LEA	(%RBX,%RDX,8),%RBX

(323) 0x44685b VMOVQ	%XMM29,%RDX

(323) 0x446861 LEA	(%RDX,%RAX,1),%RCX

(323) 0x446865 VMOVQ	%XMM31,%RDX

(323) 0x44686b ADD	%RAX,%RDX

(323) 0x44686e LEA	(%R11,%RCX,8),%R11

(323) 0x446872 MOV	0xd8(%RSP),%RCX

(323) 0x44687a LEA	(%R10,%RDX,8),%R10

(323) 0x44687e MOV	0xd0(%RSP),%RDX

(323) 0x446886 ADD	%RAX,%RDX

(323) 0x446889 LEA	(%RCX,%RDX,8),%RDX

(323) 0x44688d MOV	%R12,%RCX

(323) 0x446890 MOV	0x110(%RSP),%R12

(323) 0x446898 ADD	%RAX,%RCX

(323) 0x44689b LEA	(%R12,%RCX,8),%RCX

(323) 0x44689f MOV	0x100(%RSP),%R12

(323) 0x4468a7 VMOVQ	%RCX,%XMM25

(323) 0x4468ad MOV	0x108(%RSP),%RCX

(323) 0x4468b5 ADD	%RAX,%RCX

(323) 0x4468b8 LEA	(%R12,%RCX,8),%RCX

(323) 0x4468bc MOV	0xf0(%RSP),%R12

(323) 0x4468c4 VMOVQ	%RCX,%XMM12

(323) 0x4468c9 MOV	0xf8(%RSP),%RCX

(323) 0x4468d1 ADD	%RAX,%RCX

(323) 0x4468d4 LEA	(%R12,%RCX,8),%RCX

(323) 0x4468d8 MOV	0xe8(%RSP),%R12

(323) 0x4468e0 VMOVQ	%RCX,%XMM10

(323) 0x4468e5 MOV	0xe0(%RSP),%RCX

(323) 0x4468ed ADD	%R12,%RAX

(323) 0x4468f0 MOV	0x128(%RSP),%R12D

(323) 0x4468f8 LEA	(%RCX,%RAX,8),%RAX

(323) 0x4468fc VMOVQ	%XMM6,%RCX

(323) 0x446901 VMOVQ	%RAX,%XMM9

(323) 0x446906 XOR	%EAX,%EAX

(323) 0x446908 VMOVQ	%XMM9,%R14

(323) 0x44690d VMOVDQA64	%XMM25,%XMM9

(323) 0x446913 SHR	$0x3,%R12D

(323) 0x446917 SAL	$0x6,%R12

(323) 0x44691b MOV	%R12,0x138(%RSP)

(323) 0x446923 MOV	%RBX,%R12

(323) 0x446926 MOV	%RSI,%RBX

(323) 0x446929 MOV	%R9,%RSI

(323) 0x44692c MOV	%R8,%R9

(323) 0x44692f MOV	%R15,%R8

(323) 0x446932 MOV	%RDI,%R15

(323) 0x446935 MOV	%R13,%RDI

(323) 0x446938 MOV	%RSI,%R13

(323) 0x44693b MOV	%RCX,%RSI

(323) 0x44693e XCHG	%AX,%AX

  (325) 0x446940 VMOVQ	%XMM8,%RCX

  (325) 0x446945 VMOVUPD	(%R9,%RAX,1),%ZMM4

  (325) 0x44694c VMOVUPD	(%R15,%RAX,1),%ZMM2

  (325) 0x446953 VMOVUPD	(%RSI,%RAX,1),%ZMM7

  (325) 0x44695a VADDPD	(%RCX,%RAX,1),%ZMM4,%ZMM4

  (325) 0x446961 VMOVUPD	(%R8,%RAX,1),%ZMM5

  (325) 0x446968 VMOVUPD	(%RDI,%RAX,1),%ZMM6

  (325) 0x44696f VMOVQ	%XMM24,%RCX

  (325) 0x446975 VADDPD	(%RCX,%RAX,1),%ZMM2,%ZMM1

  (325) 0x44697c VMOVQ	%XMM11,%RCX

  (325) 0x446981 VADDPD	%ZMM7,%ZMM7,%ZMM3

  (325) 0x446987 VMOVUPD	(%R12,%RAX,1),%ZMM7

  (325) 0x44698e VMULPD	%ZMM3,%ZMM1,%ZMM2

  (325) 0x446994 VADDPD	%ZMM5,%ZMM5,%ZMM3

  (325) 0x44699a VADDPD	(%RCX,%RAX,1),%ZMM6,%ZMM5

  (325) 0x4469a1 VMOVQ	%XMM27,%RCX

  (325) 0x4469a7 VMOVUPD	(%RBX,%RAX,1),%ZMM1

  (325) 0x4469ae VADDPD	(%RCX,%RAX,1),%ZMM1,%ZMM6

  (325) 0x4469b5 VADDPD	%ZMM7,%ZMM7,%ZMM1

  (325) 0x4469bb VMOVQ	%XMM9,%RCX

  (325) 0x4469c0 VMOVUPD	(%R10,%RAX,1),%ZMM7

  (325) 0x4469c7 VMULPD	%ZMM1,%ZMM6,%ZMM6

  (325) 0x4469cd VFMADD231PD	%ZMM5,%ZMM3,%ZMM6

  (325) 0x4469d3 VMOVUPD	(%R13,%RAX,1),%ZMM3

  (325) 0x4469db VADDPD	%ZMM3,%ZMM3,%ZMM5

  (325) 0x4469e1 VADDPD	(%RCX,%RAX,1),%ZMM7,%ZMM3

  (325) 0x4469e8 VMOVQ	%XMM12,%RCX

  (325) 0x4469ed VFMADD132PD	%ZMM4,%ZMM2,%ZMM5

  (325) 0x4469f3 VSUBPD	%ZMM5,%ZMM6,%ZMM4

  (325) 0x4469f9 VMOVUPD	(%R11,%RAX,1),%ZMM6

  (325) 0x446a00 VMULPD	%ZMM15,%ZMM4,%ZMM1

  (325) 0x446a06 VDIVPD	(%RDX,%RAX,1),%ZMM3,%ZMM4

  (325) 0x446a0d VADDPD	%ZMM1,%ZMM6,%ZMM2

  (325) 0x446a13 VDIVPD	%ZMM2,%ZMM6,%ZMM5

  (325) 0x446a19 VDIVPD	%ZMM6,%ZMM14,%ZMM6

  (325) 0x446a1f VMULPD	%ZMM6,%ZMM4,%ZMM2

  (325) 0x446a25 VFNMADD213PD	(%RCX,%RAX,1),%ZMM1,%ZMM2

  (325) 0x446a2c VMOVQ	%XMM10,%RCX

  (325) 0x446a31 VMOVUPD	%ZMM2,(%RCX,%RAX,1)

  (325) 0x446a38 VMULPD	(%RDX,%RAX,1),%ZMM5,%ZMM1

  (325) 0x446a3f MOV	0x138(%RSP),%RCX

  (325) 0x446a47 VMOVUPD	%ZMM1,(%R14,%RAX,1)

  (325) 0x446a4e ADD	$0x40,%RAX

  (325) 0x446a52 CMP	%RCX,%RAX

  (325) 0x446a55 JNE	446940

(323) 0x446a5b MOV	0x128(%RSP),%R11D

(323) 0x446a63 MOV	0x118(%RSP),%R10D

(323) 0x446a6b MOV	0xa0(%RSP),%R14

(323) 0x446a73 VMOVAPD	%XMM26,%XMM2

(323) 0x446a79 MOV	%R11D,%EAX

(323) 0x446a7c AND	$-0x8,%EAX

(323) 0x446a7f ADD	%EAX,0x130(%RSP)

(323) 0x446a86 AND	$0x7,%R11D

(323) 0x446a8a LEA	(%RAX,%R10,1),%EDX

(323) 0x446a8e MOV	%EDX,0x138(%RSP)

(323) 0x446a95 JE	446f2c

(323) 0x446a9b MOV	0x128(%RSP),%R12D

(323) 0x446aa3 SUB	%EAX,%R12D

(323) 0x446aa6 LEA	-0x1(%R12),%EBX

(323) 0x446aab MOV	%R12D,%R10D

(323) 0x446aae CMP	$0x2,%EBX

(323) 0x446ab1 JBE	446d07

(323) 0x446ab7 MOVSXD	0x118(%RSP),%RDX

(323) 0x446abf VMOVQ	%XMM21,%R13

(323) 0x446ac5 MOV	0xa8(%RSP),%RDI

(323) 0x446acd VMOVQ	%XMM28,%R9

(323) 0x446ad3 VMOVQ	%XMM29,%RBX

(323) 0x446ad9 VMOVQ	%XMM23,%R8

(323) 0x446adf LEA	(%R13,%RDX,1),%R11

(323) 0x446ae4 LEA	(%R9,%RDX,1),%RCX

(323) 0x446ae8 LEA	(%RBX,%RDX,1),%R9

(323) 0x446aec LEA	(%R8,%RDX,1),%R15

(323) 0x446af0 LEA	(%R11,%RAX,1),%R12

(323) 0x446af4 MOV	0xd0(%RSP),%R11

(323) 0x446afc LEA	(%R9,%RAX,1),%R8

(323) 0x446b00 MOV	0xd8(%RSP),%RBX

(323) 0x446b08 MOV	0xf8(%RSP),%R9

(323) 0x446b10 LEA	(%RDI,%RDX,1),%RSI

(323) 0x446b14 MOV	%R12,0x118(%RSP)

(323) 0x446b1c LEA	(%R15,%RAX,1),%R15

(323) 0x446b20 ADD	%RAX,%RSI

(323) 0x446b23 MOV	%R8,0xa0(%RSP)

(323) 0x446b2b MOV	%R15,0x128(%RSP)

(323) 0x446b33 ADD	%RAX,%RCX

(323) 0x446b36 SAL	$0x3,%RSI

(323) 0x446b3a VMOVQ	%XMM31,%R13

(323) 0x446b40 LEA	(%R11,%RDX,1),%R12

(323) 0x446b44 ADD	%RDX,%R13

(323) 0x446b47 MOV	0xc0(%RSP),%RDI

(323) 0x446b4f MOV	0xe8(%RSP),%R11

(323) 0x446b57 ADD	%RAX,%R12

(323) 0x446b5a ADD	%RAX,%R13

(323) 0x446b5d LEA	(%RBX,%R12,8),%R8

(323) 0x446b61 LEA	(%R9,%RDX,1),%RBX

(323) 0x446b65 VMOVQ	%XMM18,%R9

(323) 0x446b6b MOV	0x108(%RSP),%R12

(323) 0x446b73 VMOVUPD	(%R9,%RSI,1),%YMM8

(323) 0x446b79 VADDPD	(%R9,%R15,8),%YMM8,%YMM10

(323) 0x446b7f VMOVQ	%XMM22,%R15

(323) 0x446b85 VMOVQ	%XMM19,%R9

(323) 0x446b8b LEA	(%R15,%RDX,1),%R15

(323) 0x446b8f MOV	%R13,0x98(%RSP)

(323) 0x446b97 MOV	0xb0(%RSP),%R13

(323) 0x446b9f ADD	%RAX,%RBX

(323) 0x446ba2 ADD	%RAX,%R15

(323) 0x446ba5 ADD	%RDX,%RDI

(323) 0x446ba8 ADD	%RDX,%R11

(323) 0x446bab VMOVUPD	(%R9,%R15,8),%YMM11

(323) 0x446bb1 MOV	0x118(%RSP),%R15

(323) 0x446bb9 VMOVQ	%XMM17,%R9

(323) 0x446bbf ADD	%RAX,%RDI

(323) 0x446bc2 ADD	%RDX,%R12

(323) 0x446bc5 ADD	%RAX,%R11

(323) 0x446bc8 SAL	$0x3,%RCX

(323) 0x446bcc ADD	%RDX,%R13

(323) 0x446bcf ADD	%RAX,%R12

(323) 0x446bd2 VMOVUPD	0x8(%R9,%R15,8),%YMM9

(323) 0x446bd9 VADDPD	(%R9,%R15,8),%YMM9,%YMM5

(323) 0x446bdf VMOVQ	%XMM20,%R9

(323) 0x446be5 VMOVQ	%XMM18,%R15

(323) 0x446beb VMOVUPD	0x8(%R9,%RCX,1),%YMM7

(323) 0x446bf2 MOV	0x128(%RSP),%R9

(323) 0x446bfa VMOVUPD	0x8(%R15,%RSI,1),%YMM6

(323) 0x446c01 VADDPD	%YMM11,%YMM11,%YMM12

(323) 0x446c06 ADD	%RAX,%R13

(323) 0x446c09 MOV	0xa0(%RSP),%RSI

(323) 0x446c11 VADDPD	0x8(%R15,%R9,8),%YMM6,%YMM1

(323) 0x446c18 MOV	0xb8(%RSP),%R15

(323) 0x446c20 MOV	0x110(%RSP),%R9

(323) 0x446c28 VADDPD	%YMM7,%YMM7,%YMM4

(323) 0x446c2c VMULPD	%YMM5,%YMM12,%YMM3

(323) 0x446c30 ADD	%R15,%RDX

(323) 0x446c33 ADD	%RAX,%RDX

(323) 0x446c36 VMOVQ	%XMM19,%RAX

(323) 0x446c3c VMOVUPD	(%RAX,%RDX,8),%YMM8

(323) 0x446c41 VMOVQ	%XMM17,%RDX

(323) 0x446c47 VMOVUPD	0x8(%RDX,%RDI,8),%YMM12

(323) 0x446c4d VADDPD	(%RDX,%RDI,8),%YMM12,%YMM9

(323) 0x446c52 VMOVQ	%XMM20,%RDI

(323) 0x446c58 VMOVUPD	(%RDI,%RCX,1),%YMM7

(323) 0x446c5d VMOVQ	%XMM30,%RCX

(323) 0x446c63 VMOVUPD	(%RCX,%RSI,8),%YMM6

(323) 0x446c68 VADDPD	%YMM8,%YMM8,%YMM11

(323) 0x446c6d VMOVUPD	(%R9,%R13,8),%YMM8

(323) 0x446c73 MOV	0xc8(%RSP),%R13

(323) 0x446c7b MOV	0x98(%RSP),%R15

(323) 0x446c83 MOV	0x100(%RSP),%RAX

(323) 0x446c8b VMULPD	%YMM9,%YMM11,%YMM5

(323) 0x446c90 VADDPD	(%R13,%R15,8),%YMM8,%YMM12

(323) 0x446c97 VFMADD231PD	%YMM1,%YMM4,%YMM5

(323) 0x446c9c VADDPD	%YMM7,%YMM7,%YMM4

(323) 0x446ca0 VDIVPD	(%R8),%YMM12,%YMM9

(323) 0x446ca5 VFMADD132PD	%YMM10,%YMM3,%YMM4

(323) 0x446caa VSUBPD	%YMM4,%YMM5,%YMM10

(323) 0x446cae VDIVPD	%YMM6,%YMM13,%YMM5

(323) 0x446cb2 VMULPD	%YMM0,%YMM10,%YMM3

(323) 0x446cb6 VADDPD	%YMM6,%YMM3,%YMM1

(323) 0x446cba VDIVPD	%YMM1,%YMM6,%YMM11

(323) 0x446cbe VMULPD	%YMM5,%YMM9,%YMM7

(323) 0x446cc2 VFNMADD213PD	(%RAX,%R12,8),%YMM7,%YMM3

(323) 0x446cc8 MOV	0xf0(%RSP),%R12

(323) 0x446cd0 VMOVUPD	%YMM3,(%R12,%RBX,8)

(323) 0x446cd6 VMULPD	(%R8),%YMM11,%YMM4

(323) 0x446cdb MOV	0xe0(%RSP),%R8

(323) 0x446ce3 MOV	%R10D,%EBX

(323) 0x446ce6 AND	$-0x4,%EBX

(323) 0x446ce9 ADD	%EBX,0x138(%RSP)

(323) 0x446cf0 ADD	%EBX,0x130(%RSP)

(323) 0x446cf7 AND	$0x3,%R10D

(323) 0x446cfb VMOVUPD	%YMM4,(%R8,%R11,8)

(323) 0x446d01 JE	446f2c

(323) 0x446d07 MOV	0xb8(%RSP),%R10

(323) 0x446d0f VMOVQ	%XMM19,%R13

(323) 0x446d15 MOV	0xa8(%RSP),%R9

(323) 0x446d1d VMOVQ	%XMM20,%R11

(323) 0x446d23 VMOVQ	%XMM28,%RDX

(323) 0x446d29 VMOVQ	%XMM22,%R15

(323) 0x446d2f MOVSXD	0x138(%RSP),%RAX

(323) 0x446d37 LEA	(%R11,%RDX,8),%RDI

(323) 0x446d3b LEA	(%R13,%R15,8),%R11

(323) 0x446d40 VMOVQ	%XMM18,%RCX

(323) 0x446d46 VMOVQ	%XMM17,%R12

(323) 0x446d4c VMOVQ	%XMM21,%R8

(323) 0x446d52 VMOVQ	%XMM23,%RSI

(323) 0x446d58 LEA	(%R12,%R8,8),%RDX

(323) 0x446d5c VMOVQ	%XMM29,%R15

(323) 0x446d62 VMOVQ	%XMM30,%R8

(323) 0x446d68 LEA	(%RCX,%RSI,8),%RSI

(323) 0x446d6c LEA	(%R13,%R10,8),%RBX

(323) 0x446d71 MOV	0xc0(%RSP),%R13

(323) 0x446d79 MOV	0xc8(%RSP),%R10

(323) 0x446d81 LEA	(%RCX,%R9,8),%RCX

(323) 0x446d85 VMOVQ	%XMM31,%R9

(323) 0x446d8b LEA	(%R12,%R13,8),%R12

(323) 0x446d8f LEA	(%R8,%R15,8),%R13

(323) 0x446d93 LEA	(%R10,%R9,8),%R15

(323) 0x446d97 MOV	0xd8(%RSP),%R8

(323) 0x446d9f MOV	0xd0(%RSP),%R10

(323) 0x446da7 MOV	0x110(%RSP),%R9

(323) 0x446daf LEA	(%R8,%R10,8),%R8

(323) 0x446db3 MOV	0xb0(%RSP),%R10

(323) 0x446dbb LEA	(%R9,%R10,8),%R9

(323) 0x446dbf MOV	0x100(%RSP),%R10

(323) 0x446dc7 VMOVQ	%R9,%XMM12

(323) 0x446dcc MOV	0x108(%RSP),%R9

(323) 0x446dd4 LEA	(%R10,%R9,8),%R10

(323) 0x446dd8 MOV	0xf8(%RSP),%R9

(323) 0x446de0 VMOVQ	%R10,%XMM10

(323) 0x446de5 MOV	0xf0(%RSP),%R10

(323) 0x446ded LEA	(%R10,%R9,8),%R10

(323) 0x446df1 MOV	0xe8(%RSP),%R9

(323) 0x446df9 VMOVQ	%R10,%XMM11

(323) 0x446dfe MOV	0xe0(%RSP),%R10

(323) 0x446e06 LEA	(%R10,%R9,8),%R10

(323) 0x446e0a MOV	0x130(%RSP),%R9D

(323) 0x446e12 MOV	%R14,0x130(%RSP)

(323) 0x446e1a VMOVQ	%R10,%XMM3

(323) 0x446e1f MOV	0x138(%RSP),%R10D

(323) 0x446e27 SUB	%R10D,%R9D

(323) 0x446e2a MOV	%R15,%R10

(323) 0x446e2d MOV	%R13,%R15

(323) 0x446e30 MOV	%RBX,%R13

(323) 0x446e33 MOV	%R9D,0x138(%RSP)

(323) 0x446e3b MOV	%R11,%RBX

(323) 0x446e3e VMOVQ	%XMM3,%R9

  (324) 0x446e43 VMOVSD	(%RCX,%RAX,8),%XMM6

  (324) 0x446e48 VMOVSD	0x8(%RDX,%RAX,8),%XMM1

  (324) 0x446e4e VADDSD	(%RSI,%RAX,8),%XMM6,%XMM8

  (324) 0x446e53 VADDSD	(%RDX,%RAX,8),%XMM1,%XMM9

  (324) 0x446e58 VMOVSD	(%RBX,%RAX,8),%XMM5

  (324) 0x446e5d VMOVSD	0x8(%RCX,%RAX,8),%XMM4

  (324) 0x446e63 VMOVSD	0x8(%RDI,%RAX,8),%XMM6

  (324) 0x446e69 VMOVSD	(%R12,%RAX,8),%XMM1

  (324) 0x446e6f VADDSD	%XMM5,%XMM5,%XMM7

  (324) 0x446e73 VADDSD	%XMM6,%XMM6,%XMM5

  (324) 0x446e77 VMULSD	%XMM7,%XMM9,%XMM3

  (324) 0x446e7b VADDSD	0x8(%RSI,%RAX,8),%XMM4,%XMM9

  (324) 0x446e81 VADDSD	0x8(%R12,%RAX,8),%XMM1,%XMM7

  (324) 0x446e88 VMOVSD	(%R13,%RAX,8),%XMM4

  (324) 0x446e8f VADDSD	%XMM4,%XMM4,%XMM6

  (324) 0x446e93 VMULSD	%XMM6,%XMM7,%XMM1

  (324) 0x446e97 VFMADD132SD	%XMM9,%XMM1,%XMM5

  (324) 0x446e9c VMOVSD	(%RDI,%RAX,8),%XMM9

  (324) 0x446ea1 VADDSD	%XMM9,%XMM9,%XMM7

  (324) 0x446ea6 VFMADD132SD	%XMM8,%XMM3,%XMM7

  (324) 0x446eab VMOVQ	%XMM12,%R14

  (324) 0x446eb0 VMOVQ	%XMM10,%R11

  (324) 0x446eb5 VMOVSD	(%R15,%RAX,8),%XMM3

  (324) 0x446ebb VMOVSD	(%R10,%RAX,8),%XMM1

  (324) 0x446ec1 VADDSD	(%R14,%RAX,8),%XMM1,%XMM9

  (324) 0x446ec7 VMOVQ	%XMM11,%R14

  (324) 0x446ecc VSUBSD	%XMM7,%XMM5,%XMM8

  (324) 0x446ed0 VDIVSD	(%R8,%RAX,8),%XMM9,%XMM7

  (324) 0x446ed6 VMULSD	%XMM2,%XMM8,%XMM4

  (324) 0x446eda VDIVSD	%XMM3,%XMM16,%XMM8

  (324) 0x446ee0 VADDSD	%XMM3,%XMM4,%XMM5

  (324) 0x446ee4 VDIVSD	%XMM5,%XMM3,%XMM6

  (324) 0x446ee8 VMULSD	%XMM8,%XMM7,%XMM3

  (324) 0x446eed VFNMADD213SD	(%R11,%RAX,8),%XMM3,%XMM4

  (324) 0x446ef3 MOV	0x138(%RSP),%R11D

  (324) 0x446efb VMOVSD	%XMM4,(%R14,%RAX,8)

  (324) 0x446f01 MOV	0x124(%RSP),%R14D

  (324) 0x446f09 VMULSD	(%R8,%RAX,8),%XMM6,%XMM4

  (324) 0x446f0f VMOVSD	%XMM4,(%R9,%RAX,8)

  (324) 0x446f15 INC	%RAX

  (324) 0x446f18 ADD	%EAX,%R11D

  (324) 0x446f1b CMP	%R14D,%R11D

  (324) 0x446f1e JB	446e43

(323) 0x446f24 MOV	0x130(%RSP),%R14

(323) 0x446f2c MOV	0x124(%RSP),%EAX

(323) 0x446f33 MOV	%EAX,0x130(%RSP)

(323) 0x446f3a INC	%R14

(323) 0x446f3d CMP	%R14D,0x94(%RSP)

(323) 0x446f45 JLE	446f80

(323) 0x446f47 MOV	0x8c(%RSP),%ESI

(323) 0x446f4e MOV	0x130(%RSP),%EDI

(323) 0x446f55 MOV	0x90(%RSP),%EDX

(323) 0x446f5c MOV	0x120(%RSP),%ECX

(323) 0x446f63 SUB	%EDI,%ESI

(323) 0x446f65 MOV	%EDX,0x118(%RSP)

(323) 0x446f6c JMP	4465c0

0x446f71 NOPW	%CS:(%RAX,%RAX,1)

0x446f7c NOPL	(%RAX)

0x446f80 VZEROUPPER

0x446f83 LEA	-0x28(%RBP),%RSP

0x446f87 POP	%RBX

0x446f88 POP	%R12

0x446f8a POP	%R13

0x446f8c POP	%R14

0x446f8e POP	%R15

0x446f90 POP	%RBP

0x446f91 RET

0x446f92 NOPW	%CS:(%RAX,%RAX,1)

0x446f9d NOPL	(%RAX)

(323) 0x446fa0 MOV	0x118(%RSP),%R11D

(323) 0x446fa8 XOR	%EAX,%EAX

(323) 0x446faa MOV	%R11D,0x138(%RSP)

(323) 0x446fb2 JMP	446a9b

0x446fb7 INC	%ESI

0x446fb9 XOR	%EDX,%EDX

0x446fbb JMP	4464d4

Coverage (%)	Name	Source Location	Module
►96.72+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.26+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	PdV(global_variables&, bool)	PdV.cpp:99	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:64	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.63 to 2.50 cycles (5.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.63 to 1.00 cycles (12.68x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:55

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 140 bytes (17 double precision FP elements). The binary function is storing 112 bytes (14 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	103
nb uops	101
loop length	440
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	2
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	10.00	10.00	10.00	10.00	0.50	2.50	2.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	10.00	10.00	10.00	10.00	0.50	2.50	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.63
Dispatch	10.00
DIV/SQRT	12.00
Overall L1	12.63

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	10%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.63 cycles. At this rate:

4% of peak load performance is reached (11.09 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.87 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 446440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x140,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x6c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x60(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x64(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
ADD $0x2,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0x94(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV %EDI,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 446f83 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RCX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R12D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 446f83 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x120(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 446fb7 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb77>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R9,%RDX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RSI,%RAX,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV %R10D,0x8c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CMP %R10D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 446f83 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x90(%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x10(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
DIVL 0x120(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	10-17	6	scal (6.3%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x58(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
MOV 0x50(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
MOV 0x40(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x20(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
VMOVSD 0x1e390(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMULSD (%RBX),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	3	0.50	scal (12.5%)
VMOVSD 0x1d452(%RIP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM16,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM16,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RDI,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV %R14,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R13,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x48(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11D,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV 0x30(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4464d4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	PdV.cpp:48-63
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:48-63
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.63 to 2.50 cycles (5.05x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:50
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/PdV.cpp:55

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 140 bytes (17 double precision FP elements). The binary function is storing 112 bytes (14 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	103
nb uops	101
loop length	440
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	2
used zmm registers	2
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.63 cycles
front end	12.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	10.00	10.00	10.00	10.00	0.50	2.50	2.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	10.00	10.00	10.00	10.00	0.50	2.50	2.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.63
Dispatch	10.00
DIV/SQRT	12.00
Overall L1	12.63

Vectorization ratios

INT

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	9%
load	10%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	10%
load	11%
store	10%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.63 cycles. At this rate:

4% of peak load performance is reached (11.09 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.87 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 446440

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x140,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x68(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x6c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x60(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x64(%RBX),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
ADD $0x2,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RSI),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0x94(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV %EDI,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 446f83 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RCX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R12D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 446f83 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x120(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 446fb7 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb77>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ESI,%R9D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R9,%RDX,1),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RSI,%RAX,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV %R10D,0x8c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CMP %R10D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 446f83 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0xb43>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x90(%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (6.3%)
MOV 0x8(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x10(%RBX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
DIVL 0x120(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	10-17	6	scal (6.3%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x58(%RBX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
MOV 0x50(%RBX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
MOV 0x18(%RBX),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
MOV 0x40(%RBX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x20(%RBX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
VMOVSD 0x1e390(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMULSD (%RBX),%XMM0,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	3	0.50	scal (12.5%)
VMOVSD 0x1d452(%RIP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM16,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM2,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM16,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RDI,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV 0x38(%RBX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV %R14,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R13,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV 0x48(%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB %R11D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11D,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV 0x30(%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
MOV 0x28(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RDX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %R11,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 4464d4 <_Z10PdV_kernelbiiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x94>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	N/A

Name	Coverage (%)	Time (s)
▼PdV_kernel(bool, int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.62	2.07
▼Loop 323 - PdV.cpp:50-63 - exec–	0.00	0.01
○Loop 325 - PdV.cpp:51-63 - exec	5.62	2.06
○Loop 324 - PdV.cpp:55-63 - exec	0.00	0.00

Report Configuration

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Workaround

Execution units bottlenecks

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code