OV - exec - Function initialise_chunk(int, global_variables&) [clone ._omp

	Function: initialise_chunk(int, global_variables&) [clone ._omp_fn.4]	Module: exec	Source: initialise_chunk.cpp:77-82 [...]	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp: 77 - 82

--------------------------------------------------------------------------------

77: #pragma omp parallel for simd collapse(2)

78:   for (int j = (0); j < (yrange1); j++) {

79:     for (int i = (0); i < (xrange1); i++) {

80:       field.volume(i, j) = dx * dy;

81:       field.xarea(i, j) = field.celldy[j];

82:       field.yarea(i, j) = field.celldx[i];

0x43fdb0 PUSH	%RBP

0x43fdb1 MOV	%RSP,%RBP

0x43fdb4 PUSH	%R15

0x43fdb6 PUSH	%R14

0x43fdb8 PUSH	%R13

0x43fdba PUSH	%R12

0x43fdbc PUSH	%RBX

0x43fdbd AND	$-0x40,%RSP

0x43fdc1 SUB	$0x40,%RSP

0x43fdc5 MOV	0x1c(%RDI),%EBX

0x43fdc8 MOV	0x18(%RDI),%R15D

0x43fdcc MOV	%EBX,0x38(%RSP)

0x43fdd0 MOV	%R15D,0x1c(%RSP)

0x43fdd5 TEST	%EBX,%EBX

0x43fdd7 JLE	440333

0x43fddd TEST	%R15D,%R15D

0x43fde0 JLE	440333

0x43fde6 IMUL	%R15D,%EBX

0x43fdea MOV	%RDI,%R14

0x43fded CALL	404630 <omp_get_num_threads@plt>

0x43fdf2 MOV	%EAX,%R13D

0x43fdf5 CALL	404520 <omp_get_thread_num@plt>

0x43fdfa XOR	%EDX,%EDX

0x43fdfc MOV	%EAX,%ECX

0x43fdfe MOV	%EBX,%EAX

0x43fe00 DIV	%R13D

0x43fe03 MOV	%EAX,%EBX

0x43fe05 CMP	%EDX,%ECX

0x43fe07 JB	44035b

0x43fe0d IMUL	%EBX,%ECX

0x43fe10 LEA	(%RCX,%RDX,1),%ESI

0x43fe13 LEA	(%RBX,%RSI,1),%R8D

0x43fe17 MOV	%R8D,0x18(%RSP)

0x43fe1c CMP	%R8D,%ESI

0x43fe1f JAE	440333

0x43fe25 MOV	0x1c(%RSP),%ECX

0x43fe29 MOV	%ESI,%EAX

0x43fe2b XOR	%EDX,%EDX

0x43fe2d MOV	0x10(%R14),%R13

0x43fe31 VMOVSD	0x8(%R14),%XMM11

0x43fe37 VMULSD	(%R14),%XMM11,%XMM4

0x43fe3c VBROADCASTSD	%XMM4,%YMM13

0x43fe41 VBROADCASTSD	%XMM4,%ZMM5

0x43fe47 DIV	%ECX

0x43fe49 SUB	%EDX,%ECX

0x43fe4b MOV	%EDX,0x3c(%RSP)

0x43fe4f MOVSXD	%EAX,%R8

0x43fe52 MOV	%ECX,%EDX

0x43fe54 NOPW	%CS:(%RAX,%RAX,1)

0x43fe5f NOP

(290) 0x43fe60 CMP	%EDX,%EBX

(290) 0x43fe62 CMOVBE	%EBX,%EDX

(290) 0x43fe65 LEA	(%RSI,%RDX,1),%EBX

(290) 0x43fe68 CMP	%EBX,%ESI

(290) 0x43fe6a JAE	44030f

(290) 0x43fe70 MOV	0x248(%R13),%R9

(290) 0x43fe77 MOV	0x290(%R13),%RDI

(290) 0x43fe7e MOV	0x2a8(%R13),%R11

(290) 0x43fe85 LEA	-0x1(%RDX),%R12D

(290) 0x43fe89 VMOVQ	0x2a0(%R13),%XMM10

(290) 0x43fe92 VMOVQ	0x2b8(%R13),%XMM3

(290) 0x43fe9b MOV	0x228(%R13),%R14

(290) 0x43fea2 VMOVQ	0x2d0(%R13),%XMM2

(290) 0x43feab LEA	(%R9,%R8,8),%R10

(290) 0x43feaf MOV	0x2c0(%R13),%R9

(290) 0x43feb6 IMUL	%R8,%RDI

(290) 0x43feba IMUL	%R8,%R11

(290) 0x43febe MOV	%RDI,0x20(%RSP)

(290) 0x43fec3 MOV	%R11,0x28(%RSP)

(290) 0x43fec8 IMUL	%R8,%R9

(290) 0x43fecc MOV	%R9,0x30(%RSP)

(290) 0x43fed1 CMP	$0x6,%R12D

(290) 0x43fed5 JBE	440350

(290) 0x43fedb MOVSXD	0x3c(%RSP),%RAX

(290) 0x43fee0 VMOVQ	%XMM3,%R12

(290) 0x43fee5 LEA	(%RDI,%RAX,1),%R15

(290) 0x43fee9 VMOVQ	%XMM10,%RDI

(290) 0x43feee LEA	(%R11,%RAX,1),%R11

(290) 0x43fef2 LEA	(%RDI,%R15,8),%R15

(290) 0x43fef6 MOV	%EDX,%EDI

(290) 0x43fef8 LEA	(%R12,%R11,8),%R12

(290) 0x43fefc LEA	(%R14,%RAX,8),%R11

(290) 0x43ff00 SHR	$0x3,%EDI

(290) 0x43ff03 SAL	$0x6,%RDI

(290) 0x43ff07 LEA	-0x40(%RDI),%RCX

(290) 0x43ff0b ADD	%R9,%RAX

(290) 0x43ff0e VMOVQ	%XMM2,%R9

(290) 0x43ff13 SHR	$0x6,%RCX

(290) 0x43ff17 INC	%RCX

(290) 0x43ff1a LEA	(%R9,%RAX,8),%R9

(290) 0x43ff1e XOR	%EAX,%EAX

(290) 0x43ff20 AND	$0x7,%ECX

(290) 0x43ff23 JE	44006a

(290) 0x43ff29 CMP	$0x1,%RCX

(290) 0x43ff2d JE	44003b

(290) 0x43ff33 CMP	$0x2,%RCX

(290) 0x43ff37 JE	440015

(290) 0x43ff3d CMP	$0x3,%RCX

(290) 0x43ff41 JE	43ffef

(290) 0x43ff47 CMP	$0x4,%RCX

(290) 0x43ff4b JE	43ffc9

(290) 0x43ff4d CMP	$0x5,%RCX

(290) 0x43ff51 JE	43ffa3

(290) 0x43ff53 CMP	$0x6,%RCX

(290) 0x43ff57 JE	43ff7d

(290) 0x43ff59 VMOVUPD	%ZMM5,(%R15)

(290) 0x43ff5f VBROADCASTSD	(%R10),%ZMM12

(290) 0x43ff65 MOV	$0x40,%EAX

(290) 0x43ff6a VMOVUPD	%ZMM12,(%R12)

(290) 0x43ff71 VMOVUPD	(%R11),%ZMM0

(290) 0x43ff77 VMOVUPD	%ZMM0,(%R9)

(290) 0x43ff7d VMOVUPD	%ZMM5,(%R15,%RAX,1)

(290) 0x43ff84 VBROADCASTSD	(%R10),%ZMM1

(290) 0x43ff8a VMOVUPD	%ZMM1,(%R12,%RAX,1)

(290) 0x43ff91 VMOVUPD	(%R11,%RAX,1),%ZMM6

(290) 0x43ff98 VMOVUPD	%ZMM6,(%R9,%RAX,1)

(290) 0x43ff9f ADD	$0x40,%RAX

(290) 0x43ffa3 VMOVUPD	%ZMM5,(%R15,%RAX,1)

(290) 0x43ffaa VBROADCASTSD	(%R10),%ZMM7

(290) 0x43ffb0 VMOVUPD	%ZMM7,(%R12,%RAX,1)

(290) 0x43ffb7 VMOVUPD	(%R11,%RAX,1),%ZMM8

(290) 0x43ffbe VMOVUPD	%ZMM8,(%R9,%RAX,1)

(290) 0x43ffc5 ADD	$0x40,%RAX

(290) 0x43ffc9 VMOVUPD	%ZMM5,(%R15,%RAX,1)

(290) 0x43ffd0 VBROADCASTSD	(%R10),%ZMM9

(290) 0x43ffd6 VMOVUPD	%ZMM9,(%R12,%RAX,1)

(290) 0x43ffdd VMOVUPD	(%R11,%RAX,1),%ZMM14

(290) 0x43ffe4 VMOVUPD	%ZMM14,(%R9,%RAX,1)

(290) 0x43ffeb ADD	$0x40,%RAX

(290) 0x43ffef VMOVUPD	%ZMM5,(%R15,%RAX,1)

(290) 0x43fff6 VBROADCASTSD	(%R10),%ZMM15

(290) 0x43fffc VMOVUPD	%ZMM15,(%R12,%RAX,1)

(290) 0x440003 VMOVUPD	(%R11,%RAX,1),%ZMM11

(290) 0x44000a VMOVUPD	%ZMM11,(%R9,%RAX,1)

(290) 0x440011 ADD	$0x40,%RAX

(290) 0x440015 VMOVUPD	%ZMM5,(%R15,%RAX,1)

(290) 0x44001c VBROADCASTSD	(%R10),%ZMM12

(290) 0x440022 VMOVUPD	%ZMM12,(%R12,%RAX,1)

(290) 0x440029 VMOVUPD	(%R11,%RAX,1),%ZMM0

(290) 0x440030 VMOVUPD	%ZMM0,(%R9,%RAX,1)

(290) 0x440037 ADD	$0x40,%RAX

(290) 0x44003b VMOVUPD	%ZMM5,(%R15,%RAX,1)

(290) 0x440042 VBROADCASTSD	(%R10),%ZMM1

(290) 0x440048 VMOVUPD	%ZMM1,(%R12,%RAX,1)

(290) 0x44004f VMOVUPD	(%R11,%RAX,1),%ZMM6

(290) 0x440056 VMOVUPD	%ZMM6,(%R9,%RAX,1)

(290) 0x44005d ADD	$0x40,%RAX

(290) 0x440061 CMP	%RDI,%RAX

(290) 0x440064 JE	4401a5

  (291) 0x44006a VMOVUPD	%ZMM5,(%R15,%RAX,1)

  (291) 0x440071 VBROADCASTSD	(%R10),%ZMM7

  (291) 0x440077 VMOVUPD	%ZMM7,(%R12,%RAX,1)

  (291) 0x44007e VMOVUPD	(%R11,%RAX,1),%ZMM8

  (291) 0x440085 VMOVUPD	%ZMM8,(%R9,%RAX,1)

  (291) 0x44008c VMOVUPD	%ZMM5,0x40(%R15,%RAX,1)

  (291) 0x440094 VBROADCASTSD	(%R10),%ZMM9

  (291) 0x44009a VMOVUPD	%ZMM9,0x40(%R12,%RAX,1)

  (291) 0x4400a2 VMOVUPD	0x40(%R11,%RAX,1),%ZMM14

  (291) 0x4400aa VMOVUPD	%ZMM14,0x40(%R9,%RAX,1)

  (291) 0x4400b2 VMOVUPD	%ZMM5,0x80(%R15,%RAX,1)

  (291) 0x4400ba VBROADCASTSD	(%R10),%ZMM15

  (291) 0x4400c0 VMOVUPD	%ZMM15,0x80(%R12,%RAX,1)

  (291) 0x4400c8 VMOVUPD	0x80(%R11,%RAX,1),%ZMM11

  (291) 0x4400d0 VMOVUPD	%ZMM11,0x80(%R9,%RAX,1)

  (291) 0x4400d8 VMOVUPD	%ZMM5,0xc0(%R15,%RAX,1)

  (291) 0x4400e0 VBROADCASTSD	(%R10),%ZMM12

  (291) 0x4400e6 VMOVUPD	%ZMM12,0xc0(%R12,%RAX,1)

  (291) 0x4400ee VMOVUPD	0xc0(%R11,%RAX,1),%ZMM0

  (291) 0x4400f6 VMOVUPD	%ZMM0,0xc0(%R9,%RAX,1)

  (291) 0x4400fe VMOVUPD	%ZMM5,0x100(%R15,%RAX,1)

  (291) 0x440106 VBROADCASTSD	(%R10),%ZMM1

  (291) 0x44010c VMOVUPD	%ZMM1,0x100(%R12,%RAX,1)

  (291) 0x440114 VMOVUPD	0x100(%R11,%RAX,1),%ZMM6

  (291) 0x44011c VMOVUPD	%ZMM6,0x100(%R9,%RAX,1)

  (291) 0x440124 VMOVUPD	%ZMM5,0x140(%R15,%RAX,1)

  (291) 0x44012c VBROADCASTSD	(%R10),%ZMM7

  (291) 0x440132 VMOVUPD	%ZMM7,0x140(%R12,%RAX,1)

  (291) 0x44013a VMOVUPD	0x140(%R11,%RAX,1),%ZMM8

  (291) 0x440142 VMOVUPD	%ZMM8,0x140(%R9,%RAX,1)

  (291) 0x44014a VMOVUPD	%ZMM5,0x180(%R15,%RAX,1)

  (291) 0x440152 VBROADCASTSD	(%R10),%ZMM9

  (291) 0x440158 VMOVUPD	%ZMM9,0x180(%R12,%RAX,1)

  (291) 0x440160 VMOVUPD	0x180(%R11,%RAX,1),%ZMM14

  (291) 0x440168 VMOVUPD	%ZMM14,0x180(%R9,%RAX,1)

  (291) 0x440170 VMOVUPD	%ZMM5,0x1c0(%R15,%RAX,1)

  (291) 0x440178 VBROADCASTSD	(%R10),%ZMM15

  (291) 0x44017e VMOVUPD	%ZMM15,0x1c0(%R12,%RAX,1)

  (291) 0x440186 VMOVUPD	0x1c0(%R11,%RAX,1),%ZMM11

  (291) 0x44018e VMOVUPD	%ZMM11,0x1c0(%R9,%RAX,1)

  (291) 0x440196 ADD	$0x200,%RAX

  (291) 0x44019c CMP	%RDI,%RAX

  (291) 0x44019f JNE	44006a

(290) 0x4401a5 MOV	0x3c(%RSP),%R15D

(290) 0x4401aa MOV	%EDX,%EAX

(290) 0x4401ac AND	$-0x8,%EAX

(290) 0x4401af ADD	%EAX,%ESI

(290) 0x4401b1 LEA	(%RAX,%R15,1),%ECX

(290) 0x4401b5 TEST	$0x7,%DL

(290) 0x4401b8 JE	44030d

(290) 0x4401be SUB	%EAX,%EDX

(290) 0x4401c0 LEA	-0x1(%RDX),%R12D

(290) 0x4401c4 CMP	$0x2,%R12D

(290) 0x4401c8 JBE	44023b

(290) 0x4401ca MOVSXD	0x3c(%RSP),%R11

(290) 0x4401cf MOV	0x20(%RSP),%R9

(290) 0x4401d4 MOV	0x28(%RSP),%R12

(290) 0x4401d9 VMOVQ	%XMM10,%RDI

(290) 0x4401de VMOVSD	(%R10),%XMM12

(290) 0x4401e3 VMOVQ	%XMM3,%R15

(290) 0x4401e8 VBROADCASTSD	%XMM12,%YMM0

(290) 0x4401ed ADD	%R11,%R9

(290) 0x4401f0 ADD	%R11,%R12

(290) 0x4401f3 ADD	%RAX,%R9

(290) 0x4401f6 ADD	%RAX,%R12

(290) 0x4401f9 VMOVUPD	%YMM13,(%RDI,%R9,8)

(290) 0x4401ff LEA	(%R11,%RAX,1),%R9

(290) 0x440203 MOV	0x30(%RSP),%RDI

(290) 0x440208 VMOVUPD	%YMM0,(%R15,%R12,8)

(290) 0x44020e VMOVUPD	(%R14,%R9,8),%YMM1

(290) 0x440214 ADD	%RDI,%R11

(290) 0x440217 ADD	%RAX,%R11

(290) 0x44021a VMOVQ	%XMM2,%RAX

(290) 0x44021f VMOVUPD	%YMM1,(%RAX,%R11,8)

(290) 0x440225 MOV	%EDX,%R11D

(290) 0x440228 AND	$-0x4,%R11D

(290) 0x44022c ADD	%R11D,%ECX

(290) 0x44022f ADD	%R11D,%ESI

(290) 0x440232 AND	$0x3,%EDX

(290) 0x440235 JE	44030d

(290) 0x44023b MOV	0x20(%RSP),%R15

(290) 0x440240 MOVSXD	%ECX,%R12

(290) 0x440243 VMOVQ	%XMM10,%R9

(290) 0x440248 MOV	0x30(%RSP),%R11

(290) 0x44024d VMOVQ	%XMM3,%RDI

(290) 0x440252 LEA	(%R15,%R12,1),%RDX

(290) 0x440256 VMOVSD	%XMM4,(%R9,%RDX,8)

(290) 0x44025c MOV	0x28(%RSP),%R9

(290) 0x440261 LEA	(,%R12,8),%RDX

(290) 0x440269 VMOVSD	(%R10),%XMM6

(290) 0x44026e LEA	(%R9,%R12,1),%RAX

(290) 0x440272 ADD	%R11,%R12

(290) 0x440275 VMOVSD	%XMM6,(%RDI,%RAX,8)

(290) 0x44027a VMOVQ	%XMM2,%RAX

(290) 0x44027f VMOVSD	(%R14,%RDX,1),%XMM7

(290) 0x440285 VMOVSD	%XMM7,(%RAX,%R12,8)

(290) 0x44028b LEA	0x1(%RSI),%R12D

(290) 0x44028f CMP	%EBX,%R12D

(290) 0x440292 JAE	44030d

(290) 0x440294 LEA	0x1(%RCX),%EAX

(290) 0x440297 VMOVQ	%XMM10,%R12

(290) 0x44029c ADD	$0x2,%ESI

(290) 0x44029f CLTQ

(290) 0x4402a1 LEA	(%R15,%RAX,1),%RDI

(290) 0x4402a5 VMOVSD	%XMM4,(%R12,%RDI,8)

(290) 0x4402ab LEA	(%R9,%RAX,1),%RDI

(290) 0x4402af VMOVQ	%XMM3,%R12

(290) 0x4402b4 ADD	%R11,%RAX

(290) 0x4402b7 VMOVSD	(%R10),%XMM8

(290) 0x4402bc VMOVSD	%XMM8,(%R12,%RDI,8)

(290) 0x4402c2 MOV	%R11,%RDI

(290) 0x4402c5 VMOVQ	%XMM2,%R11

(290) 0x4402ca VMOVSD	0x8(%R14,%RDX,1),%XMM9

(290) 0x4402d1 VMOVSD	%XMM9,(%R11,%RAX,8)

(290) 0x4402d7 CMP	%EBX,%ESI

(290) 0x4402d9 JAE	44030d

(290) 0x4402db ADD	$0x2,%ECX

(290) 0x4402de MOVSXD	%ECX,%RSI

(290) 0x4402e1 VMOVQ	%XMM10,%RCX

(290) 0x4402e6 ADD	%RSI,%R15

(290) 0x4402e9 ADD	%RSI,%R9

(290) 0x4402ec ADD	%RSI,%RDI

(290) 0x4402ef VMOVSD	%XMM4,(%RCX,%R15,8)

(290) 0x4402f5 VMOVSD	(%R10),%XMM10

(290) 0x4402fa VMOVSD	%XMM10,(%R12,%R9,8)

(290) 0x440300 VMOVSD	0x10(%R14,%RDX,1),%XMM3

(290) 0x440307 VMOVSD	%XMM3,(%R11,%RDI,8)

(290) 0x44030d MOV	%EBX,%ESI

(290) 0x44030f INC	%R8

(290) 0x440312 CMP	%R8D,0x38(%RSP)

(290) 0x440317 JLE	440330

(290) 0x440319 MOV	0x18(%RSP),%EBX

(290) 0x44031d MOV	0x1c(%RSP),%EDX

(290) 0x440321 MOVL	$0,0x3c(%RSP)

(290) 0x440329 SUB	%ESI,%EBX

(290) 0x44032b JMP	43fe60

0x440330 VZEROUPPER

0x440333 LEA	-0x28(%RBP),%RSP

0x440337 POP	%RBX

0x440338 POP	%R12

0x44033a POP	%R13

0x44033c POP	%R14

0x44033e POP	%R15

0x440340 POP	%RBP

0x440341 RET

0x440342 NOPW	%CS:(%RAX,%RAX,1)

0x44034d NOPL	(%RAX)

(290) 0x440350 MOV	0x3c(%RSP),%ECX

(290) 0x440354 XOR	%EAX,%EAX

(290) 0x440356 JMP	4401be

0x44035b INC	%EBX

0x44035d XOR	%EDX,%EDX

0x44035f JMP	43fe0d

0x440364 NOPW	%CS:(%RAX,%RAX,1)

0x44036f NOP

Coverage (%)	Name	Source Location	Module
►96.71+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.29+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	initialise_chunk(int, global_v[...]	initialise_chunk.cpp:85	exec
○	start(parallel_&, global_confi[...]	start.cpp:83	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	initialise_chunk.cpp:77-82
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-82

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.75 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 8.00 cycles (1.50x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.75 cycles (1.55x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:80

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 36 bytes (4 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	66
nb uops	64
loop length	229
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	3.00	3.00	3.00	3.00	0.50	1.50	1.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	3.00	3.00	3.00	3.00	0.50	1.50	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	8.00
Dispatch	4.33
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	7%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	10%
store	6%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (3.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43fdb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1c(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x18(%RDI),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (6.3%)
MOV %EBX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV %R15D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
TEST %EBX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 440333 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R15D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 440333 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R15D,%EBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 44035b <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EBX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8D,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CMP %R8D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 440333 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x1c(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%R14),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
VMOVSD 0x8(%R14),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R14),%XMM11,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
DIV %ECX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
SUB %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43fe0d <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	initialise_chunk.cpp:77-82
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77-82

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.75 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.75 cycles (1.55x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:77
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/initialise_chunk.cpp:80

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 36 bytes (4 double precision FP elements). The binary function is storing 16 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.02 FP operations per loaded or stored byte.

General properties

nb instructions	66
nb uops	64
loop length	229
used x86 registers	13
used mmx registers	0
used xmm registers	2
used ymm registers	1
used zmm registers	1
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	3.00	3.00	3.00	3.00	0.50	1.50	1.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	3.00	3.00	3.00	3.00	0.50	1.50	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	8.00
Dispatch	4.33
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	6%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	0%
store	0%
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	7%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	10%
store	6%
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (3.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43fdb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x1c(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x18(%RDI),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (6.3%)
MOV %EBX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV %R15D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
TEST %EBX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 440333 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
TEST %R15D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 440333 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R15D,%EBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 44035b <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5ab>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %EBX,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RDX,1),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RBX,%RSI,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R8D,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CMP %R8D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 440333 <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x583>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x1c(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%R14),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (12.5%)
VMOVSD 0x8(%R14),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMULSD (%R14),%XMM11,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	3	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM4,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
DIV %ECX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
SUB %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43fe0d <_Z16initialise_chunkiR16global_variables._omp_fn.4+0x5d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼initialise_chunk(int, global_variables&) [clone ._omp_fn.4]–	0.03	0.01
▼Loop 290 - initialise_chunk.cpp:77-82 - exec–	0.00	0.00
○Loop 291 - initialise_chunk.cpp:80-82 - exec	0.03	0.01

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Matching between your function (in the source code) and the binary function

Arithmetic intensity

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Vectorization ratios

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Cycles and memory resources usage

Front-end bottlenecks

ASM code