OV - exec - Function ideal_gas_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: ideal_gas_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: ideal_gas.cpp:37-45 [...]	Coverage (incl. loops): 5.55% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp: 37 - 45

--------------------------------------------------------------------------------

37: #pragma omp parallel for simd collapse(2)

38:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

39:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

40:       double v = 1.0 / density(i, j);

41:       pressure(i, j) = (1.4 - 1.0) * density(i, j) * energy(i, j);

42:       double pressurebyenergy = (1.4 - 1.0) * density(i, j);

43:       double pressurebyvolume = -density(i, j) * pressure(i, j);

44:       double sound_speed_squared = v * v * (pressure(i, j) * pressurebyenergy - pressurebyvolume);

45:       soundspeed(i, j) = std::sqrt(sound_speed_squared);

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x43e270 PUSH	%RBP

0x43e271 MOV	%RSP,%RBP

0x43e274 PUSH	%R15

0x43e276 PUSH	%R14

0x43e278 PUSH	%R13

0x43e27a PUSH	%R12

0x43e27c PUSH	%RBX

0x43e27d MOV	%RDI,%R14

0x43e280 AND	$-0x40,%RSP

0x43e284 SUB	$0x40,%RSP

0x43e288 MOV	0x28(%RDI),%EAX

0x43e28b MOV	0x2c(%RDI),%EDX

0x43e28e MOV	0x20(%RDI),%EBX

0x43e291 MOV	0x24(%R14),%ECX

0x43e295 ADD	$0x2,%EDX

0x43e298 LEA	0x1(%RBX),%EDI

0x43e29b LEA	0x1(%RAX),%R15D

0x43e29f MOV	%EDX,0x14(%RSP)

0x43e2a3 MOV	%EDI,0x10(%RSP)

0x43e2a7 CMP	%EDX,%R15D

0x43e2aa JGE	43e893

0x43e2b0 MOV	%EDX,%EBX

0x43e2b2 LEA	0x2(%RCX),%R12D

0x43e2b6 SUB	%R15D,%EBX

0x43e2b9 CMP	%R12D,%EDI

0x43e2bc JGE	43e893

0x43e2c2 MOV	%R12D,%ESI

0x43e2c5 SUB	%EDI,%ESI

0x43e2c7 MOV	%ESI,0x38(%RSP)

0x43e2cb CALL	404630 <omp_get_num_threads@plt>

0x43e2d0 MOV	%EAX,%R13D

0x43e2d3 CALL	404520 <omp_get_thread_num@plt>

0x43e2d8 XOR	%EDX,%EDX

0x43e2da MOV	%EAX,%ECX

0x43e2dc MOV	0x38(%RSP),%EAX

0x43e2e0 IMUL	%EBX,%EAX

0x43e2e3 DIV	%R13D

0x43e2e6 MOV	%EAX,%R9D

0x43e2e9 CMP	%EDX,%ECX

0x43e2eb JB	43e8bc

0x43e2f1 IMUL	%R9D,%ECX

0x43e2f5 ADD	%EDX,%ECX

0x43e2f7 LEA	(%R9,%RCX,1),%R8D

0x43e2fb MOV	%R8D,0xc(%RSP)

0x43e300 CMP	%R8D,%ECX

0x43e303 JAE	43e893

0x43e309 MOV	%ECX,%EAX

0x43e30b XOR	%EDX,%EDX

0x43e30d VMOVQ	0x18(%R14),%XMM1

0x43e313 MOV	0x10(%RSP),%R10D

0x43e318 DIVL	0x38(%RSP)

0x43e31c VMOVQ	(%R14),%XMM4

0x43e321 VMOVQ	0x8(%R14),%XMM13

0x43e327 VMOVSD	0x2565f(%RIP),%XMM17

0x43e331 VMOVQ	0x10(%R14),%XMM12

0x43e337 VMOVSD	0x26587(%RIP),%XMM16

0x43e341 VMOVSD	0x26587(%RIP),%XMM15

0x43e349 VBROADCASTSD	%XMM17,%YMM20

0x43e34f VBROADCASTSD	%XMM16,%YMM19

0x43e355 VBROADCASTSD	%XMM15,%YMM18

0x43e35b VBROADCASTSD	%XMM17,%ZMM7

0x43e361 VBROADCASTSD	%XMM16,%ZMM6

0x43e367 VBROADCASTSD	%XMM15,%ZMM5

0x43e36d VMOVDQA64	%XMM1,%XMM23

0x43e373 ADD	%EDX,%R10D

0x43e376 ADD	%R15D,%EAX

0x43e379 MOVSXD	%EAX,%RDI

0x43e37c SUB	%R10D,%R12D

0x43e37f MOV	%R9D,%EAX

0x43e382 MOV	%R10D,0x3c(%RSP)

0x43e387 NOPW	(%RAX,%RAX,1)

(284) 0x43e390 CMP	%R12D,%EAX

(284) 0x43e393 CMOVA	%R12D,%EAX

(284) 0x43e397 LEA	(%RCX,%RAX,1),%EBX

(284) 0x43e39a CMP	%EBX,%ECX

(284) 0x43e39c JAE	43e865

(284) 0x43e3a2 VMOVQ	%XMM13,%R15

(284) 0x43e3a7 VMOVQ	%XMM12,%RSI

(284) 0x43e3ac VMOVQ	%XMM4,%R11

(284) 0x43e3b1 VMOVQ	%XMM23,%R9

(284) 0x43e3b7 MOV	(%R15),%RDX

(284) 0x43e3ba MOV	(%RSI),%R13

(284) 0x43e3bd MOV	(%R11),%R8

(284) 0x43e3c0 MOV	(%R9),%R14

(284) 0x43e3c3 MOV	0x10(%RSI),%R12

(284) 0x43e3c7 LEA	-0x1(%RAX),%ESI

(284) 0x43e3ca VMOVQ	0x10(%R15),%XMM8

(284) 0x43e3d0 MOV	0x10(%R11),%R10

(284) 0x43e3d4 MOV	0x10(%R9),%R15

(284) 0x43e3d8 IMUL	%RDI,%RDX

(284) 0x43e3dc IMUL	%RDI,%R8

(284) 0x43e3e0 IMUL	%RDI,%R13

(284) 0x43e3e4 IMUL	%RDI,%R14

(284) 0x43e3e8 MOV	%RDX,0x18(%RSP)

(284) 0x43e3ed MOV	%R8,0x30(%RSP)

(284) 0x43e3f2 MOV	%R13,0x20(%RSP)

(284) 0x43e3f7 MOV	%R14,0x28(%RSP)

(284) 0x43e3fc CMP	$0x6,%ESI

(284) 0x43e3ff JBE	43e8b0

(284) 0x43e405 MOVSXD	0x3c(%RSP),%RSI

(284) 0x43e40a VMOVQ	%XMM8,%R11

(284) 0x43e40f LEA	(%R8,%RSI,1),%R9

(284) 0x43e413 LEA	(%RDX,%RSI,1),%RDX

(284) 0x43e417 LEA	(%R13,%RSI,1),%R13

(284) 0x43e41c MOV	0x28(%RSP),%R8

(284) 0x43e421 LEA	(%R10,%R9,8),%R14

(284) 0x43e425 LEA	(%R11,%RDX,8),%R9

(284) 0x43e429 LEA	(%R12,%R13,8),%R11

(284) 0x43e42d MOV	%EAX,%R13D

(284) 0x43e430 SHR	$0x3,%R13D

(284) 0x43e434 SAL	$0x6,%R13

(284) 0x43e438 ADD	%R8,%RSI

(284) 0x43e43b LEA	-0x40(%R13),%R8

(284) 0x43e43f SHR	$0x6,%R8

(284) 0x43e443 INC	%R8

(284) 0x43e446 LEA	(%R15,%RSI,8),%RDX

(284) 0x43e44a XOR	%ESI,%ESI

(284) 0x43e44c AND	$0x3,%R8D

(284) 0x43e450 JE	43e54c

(284) 0x43e456 CMP	$0x1,%R8

(284) 0x43e45a JE	43e4f8

(284) 0x43e460 CMP	$0x2,%R8

(284) 0x43e464 JE	43e4ad

(284) 0x43e466 VMOVUPD	(%R14),%ZMM21

(284) 0x43e46c VMULPD	(%R9),%ZMM21,%ZMM24

(284) 0x43e472 MOV	$0x40,%ESI

(284) 0x43e477 VDIVPD	%ZMM21,%ZMM7,%ZMM22

(284) 0x43e47d VMULPD	%ZMM6,%ZMM24,%ZMM25

(284) 0x43e483 VMOVUPD	%ZMM25,(%R11)

(284) 0x43e489 VMULPD	(%R14),%ZMM5,%ZMM0

(284) 0x43e48f VMULPD	%ZMM22,%ZMM22,%ZMM26

(284) 0x43e495 VMULPD	%ZMM25,%ZMM0,%ZMM2

(284) 0x43e49b VMULPD	%ZMM26,%ZMM2,%ZMM3

(284) 0x43e4a1 VSQRTPD	%ZMM3,%ZMM9

(284) 0x43e4a7 VMOVUPD	%ZMM9,(%RDX)

(284) 0x43e4ad VMOVUPD	(%R14,%RSI,1),%ZMM27

(284) 0x43e4b4 VMULPD	(%R9,%RSI,1),%ZMM27,%ZMM29

(284) 0x43e4bb VDIVPD	%ZMM27,%ZMM7,%ZMM28

(284) 0x43e4c1 VMULPD	%ZMM6,%ZMM29,%ZMM30

(284) 0x43e4c7 VMOVUPD	%ZMM30,(%R11,%RSI,1)

(284) 0x43e4ce VMULPD	(%R14,%RSI,1),%ZMM5,%ZMM10

(284) 0x43e4d5 VMULPD	%ZMM28,%ZMM28,%ZMM31

(284) 0x43e4db VMULPD	%ZMM30,%ZMM10,%ZMM11

(284) 0x43e4e1 VMULPD	%ZMM31,%ZMM11,%ZMM14

(284) 0x43e4e7 VSQRTPD	%ZMM14,%ZMM1

(284) 0x43e4ed VMOVUPD	%ZMM1,(%RDX,%RSI,1)

(284) 0x43e4f4 ADD	$0x40,%RSI

(284) 0x43e4f8 VMOVUPD	(%R14,%RSI,1),%ZMM21

(284) 0x43e4ff VMULPD	(%R9,%RSI,1),%ZMM21,%ZMM24

(284) 0x43e506 VDIVPD	%ZMM21,%ZMM7,%ZMM22

(284) 0x43e50c VMULPD	%ZMM6,%ZMM24,%ZMM25

(284) 0x43e512 VMOVUPD	%ZMM25,(%R11,%RSI,1)

(284) 0x43e519 VMULPD	(%R14,%RSI,1),%ZMM5,%ZMM0

(284) 0x43e520 VMULPD	%ZMM22,%ZMM22,%ZMM26

(284) 0x43e526 VMULPD	%ZMM25,%ZMM0,%ZMM2

(284) 0x43e52c VMULPD	%ZMM26,%ZMM2,%ZMM3

(284) 0x43e532 VSQRTPD	%ZMM3,%ZMM9

(284) 0x43e538 VMOVUPD	%ZMM9,(%RDX,%RSI,1)

(284) 0x43e53f ADD	$0x40,%RSI

(284) 0x43e543 CMP	%R13,%RSI

(284) 0x43e546 JE	43e687

  (285) 0x43e54c VMOVUPD	(%R14,%RSI,1),%ZMM27

  (285) 0x43e553 VMULPD	(%R9,%RSI,1),%ZMM27,%ZMM29

  (285) 0x43e55a VDIVPD	%ZMM27,%ZMM7,%ZMM28

  (285) 0x43e560 VMULPD	%ZMM6,%ZMM29,%ZMM30

  (285) 0x43e566 VMOVUPD	%ZMM30,(%R11,%RSI,1)

  (285) 0x43e56d VMULPD	(%R14,%RSI,1),%ZMM5,%ZMM10

  (285) 0x43e574 VMULPD	%ZMM28,%ZMM28,%ZMM31

  (285) 0x43e57a VMULPD	%ZMM30,%ZMM10,%ZMM11

  (285) 0x43e580 VMULPD	%ZMM31,%ZMM11,%ZMM14

  (285) 0x43e586 VSQRTPD	%ZMM14,%ZMM1

  (285) 0x43e58c VMOVUPD	%ZMM1,(%RDX,%RSI,1)

  (285) 0x43e593 VMOVUPD	0x40(%R14,%RSI,1),%ZMM21

  (285) 0x43e59b VMULPD	0x40(%R9,%RSI,1),%ZMM21,%ZMM24

  (285) 0x43e5a3 VDIVPD	%ZMM21,%ZMM7,%ZMM22

  (285) 0x43e5a9 VMULPD	%ZMM6,%ZMM24,%ZMM25

  (285) 0x43e5af VMOVUPD	%ZMM25,0x40(%R11,%RSI,1)

  (285) 0x43e5b7 VMULPD	0x40(%R14,%RSI,1),%ZMM5,%ZMM0

  (285) 0x43e5bf VMULPD	%ZMM22,%ZMM22,%ZMM26

  (285) 0x43e5c5 VMULPD	%ZMM25,%ZMM0,%ZMM2

  (285) 0x43e5cb VMULPD	%ZMM26,%ZMM2,%ZMM3

  (285) 0x43e5d1 VSQRTPD	%ZMM3,%ZMM9

  (285) 0x43e5d7 VMOVUPD	%ZMM9,0x40(%RDX,%RSI,1)

  (285) 0x43e5df VMOVUPD	0x80(%R14,%RSI,1),%ZMM27

  (285) 0x43e5e7 VMULPD	0x80(%R9,%RSI,1),%ZMM27,%ZMM29

  (285) 0x43e5ef VDIVPD	%ZMM27,%ZMM7,%ZMM28

  (285) 0x43e5f5 VMULPD	%ZMM6,%ZMM29,%ZMM30

  (285) 0x43e5fb VMOVUPD	%ZMM30,0x80(%R11,%RSI,1)

  (285) 0x43e603 VMULPD	0x80(%R14,%RSI,1),%ZMM5,%ZMM10

  (285) 0x43e60b VMULPD	%ZMM28,%ZMM28,%ZMM31

  (285) 0x43e611 VMULPD	%ZMM30,%ZMM10,%ZMM11

  (285) 0x43e617 VMULPD	%ZMM31,%ZMM11,%ZMM14

  (285) 0x43e61d VSQRTPD	%ZMM14,%ZMM1

  (285) 0x43e623 VMOVUPD	%ZMM1,0x80(%RDX,%RSI,1)

  (285) 0x43e62b VMOVUPD	0xc0(%R14,%RSI,1),%ZMM0

  (285) 0x43e633 VMULPD	0xc0(%R9,%RSI,1),%ZMM0,%ZMM2

  (285) 0x43e63b VDIVPD	%ZMM0,%ZMM7,%ZMM21

  (285) 0x43e641 VMULPD	%ZMM6,%ZMM2,%ZMM3

  (285) 0x43e647 VMOVUPD	%ZMM3,0xc0(%R11,%RSI,1)

  (285) 0x43e64f VMULPD	0xc0(%R14,%RSI,1),%ZMM5,%ZMM9

  (285) 0x43e657 VMULPD	%ZMM21,%ZMM21,%ZMM22

  (285) 0x43e65d VMULPD	%ZMM3,%ZMM9,%ZMM10

  (285) 0x43e663 VMULPD	%ZMM22,%ZMM10,%ZMM11

  (285) 0x43e669 VSQRTPD	%ZMM11,%ZMM14

  (285) 0x43e66f VMOVUPD	%ZMM14,0xc0(%RDX,%RSI,1)

  (285) 0x43e677 ADD	$0x100,%RSI

  (285) 0x43e67e CMP	%R13,%RSI

  (285) 0x43e681 JNE	43e54c

(284) 0x43e687 MOV	0x3c(%RSP),%R14D

(284) 0x43e68c MOV	%EAX,%ESI

(284) 0x43e68e AND	$-0x8,%ESI

(284) 0x43e691 ADD	%ESI,%ECX

(284) 0x43e693 LEA	(%RSI,%R14,1),%R8D

(284) 0x43e697 TEST	$0x7,%AL

(284) 0x43e699 JE	43e863

(284) 0x43e69f SUB	%ESI,%EAX

(284) 0x43e6a1 LEA	-0x1(%RAX),%R9D

(284) 0x43e6a5 CMP	$0x2,%R9D

(284) 0x43e6a9 JBE	43e739

(284) 0x43e6af MOVSXD	0x3c(%RSP),%RDX

(284) 0x43e6b4 MOV	0x30(%RSP),%R11

(284) 0x43e6b9 MOV	0x28(%RSP),%R14

(284) 0x43e6be LEA	(%R11,%RDX,1),%R13

(284) 0x43e6c2 MOV	0x18(%RSP),%R11

(284) 0x43e6c7 ADD	%RSI,%R13

(284) 0x43e6ca LEA	(%R10,%R13,8),%R9

(284) 0x43e6ce LEA	(%R14,%RDX,1),%R13

(284) 0x43e6d2 VMOVUPD	(%R9),%YMM1

(284) 0x43e6d7 ADD	%RSI,%R13

(284) 0x43e6da LEA	(%R11,%RDX,1),%R14

(284) 0x43e6de VMOVQ	%XMM8,%R11

(284) 0x43e6e3 ADD	%RSI,%R14

(284) 0x43e6e6 VMULPD	(%R11,%R14,8),%YMM1,%YMM0

(284) 0x43e6ec MOV	0x20(%RSP),%R14

(284) 0x43e6f1 VDIVPD	%YMM1,%YMM20,%YMM3

(284) 0x43e6f7 ADD	%R14,%RDX

(284) 0x43e6fa ADD	%RSI,%RDX

(284) 0x43e6fd MOV	%EAX,%ESI

(284) 0x43e6ff AND	$-0x4,%ESI

(284) 0x43e702 VMULPD	%YMM19,%YMM0,%YMM2

(284) 0x43e708 ADD	%ESI,%R8D

(284) 0x43e70b ADD	%ESI,%ECX

(284) 0x43e70d VMOVUPD	%YMM2,(%R12,%RDX,8)

(284) 0x43e713 VMULPD	(%R9),%YMM18,%YMM9

(284) 0x43e719 VMULPD	%YMM3,%YMM3,%YMM11

(284) 0x43e71d VMULPD	%YMM2,%YMM9,%YMM10

(284) 0x43e721 VMULPD	%YMM11,%YMM10,%YMM14

(284) 0x43e726 VSQRTPD	%YMM14,%YMM1

(284) 0x43e72b VMOVUPD	%YMM1,(%R15,%R13,8)

(284) 0x43e731 TEST	$0x3,%AL

(284) 0x43e733 JE	43e863

(284) 0x43e739 MOV	0x30(%RSP),%R9

(284) 0x43e73e MOV	0x18(%RSP),%R14

(284) 0x43e743 MOVSXD	%R8D,%RAX

(284) 0x43e746 VMOVQ	%XMM8,%R11

(284) 0x43e74b LEA	(%R9,%RAX,1),%RDX

(284) 0x43e74f LEA	(%R14,%RAX,1),%R13

(284) 0x43e753 LEA	(%R10,%RDX,8),%RDX

(284) 0x43e757 VMOVSD	(%RDX),%XMM0

(284) 0x43e75b VMULSD	(%R11,%R13,8),%XMM0,%XMM2

(284) 0x43e761 MOV	0x20(%RSP),%R13

(284) 0x43e766 MOV	0x28(%RSP),%R11

(284) 0x43e76b VMULSD	%XMM16,%XMM2,%XMM9

(284) 0x43e771 VDIVSD	%XMM0,%XMM17,%XMM3

(284) 0x43e777 VMULSD	%XMM3,%XMM3,%XMM14

(284) 0x43e77b LEA	(%R13,%RAX,1),%RSI

(284) 0x43e780 ADD	%R11,%RAX

(284) 0x43e783 VMOVSD	%XMM9,(%R12,%RSI,8)

(284) 0x43e789 VMULSD	(%RDX),%XMM15,%XMM10

(284) 0x43e78d VMULSD	%XMM9,%XMM10,%XMM11

(284) 0x43e792 VMULSD	%XMM14,%XMM11,%XMM1

(284) 0x43e797 VSQRTSD	%XMM1,%XMM1,%XMM1

(284) 0x43e79b VMOVSD	%XMM1,(%R15,%RAX,8)

(284) 0x43e7a1 LEA	0x1(%RCX),%EAX

(284) 0x43e7a4 CMP	%EBX,%EAX

(284) 0x43e7a6 JAE	43e863

(284) 0x43e7ac LEA	0x1(%R8),%EAX

(284) 0x43e7b0 ADD	$0x2,%ECX

(284) 0x43e7b3 CLTQ

(284) 0x43e7b5 LEA	(%R9,%RAX,1),%R9

(284) 0x43e7b9 LEA	(%R14,%RAX,1),%RSI

(284) 0x43e7bd LEA	(%R10,%R9,8),%RDX

(284) 0x43e7c1 VMOVQ	%XMM8,%R9

(284) 0x43e7c6 VMOVSD	(%RDX),%XMM0

(284) 0x43e7ca VMULSD	(%R9,%RSI,8),%XMM0,%XMM2

(284) 0x43e7d0 LEA	(%R13,%RAX,1),%RSI

(284) 0x43e7d5 ADD	%R11,%RAX

(284) 0x43e7d8 VMULSD	%XMM16,%XMM2,%XMM9

(284) 0x43e7de VDIVSD	%XMM0,%XMM17,%XMM3

(284) 0x43e7e4 VMOVSD	%XMM9,(%R12,%RSI,8)

(284) 0x43e7ea VMULSD	%XMM3,%XMM3,%XMM14

(284) 0x43e7ee VMULSD	(%RDX),%XMM15,%XMM10

(284) 0x43e7f2 MOV	%R11,%RDX

(284) 0x43e7f5 VMULSD	%XMM9,%XMM10,%XMM11

(284) 0x43e7fa VMULSD	%XMM14,%XMM11,%XMM1

(284) 0x43e7ff VSQRTSD	%XMM1,%XMM1,%XMM1

(284) 0x43e803 VMOVSD	%XMM1,(%R15,%RAX,8)

(284) 0x43e809 CMP	%EBX,%ECX

(284) 0x43e80b JAE	43e863

(284) 0x43e80d MOV	0x30(%RSP),%RCX

(284) 0x43e812 ADD	$0x2,%R8D

(284) 0x43e816 MOVSXD	%R8D,%R8

(284) 0x43e819 ADD	%R8,%R14

(284) 0x43e81c ADD	%R8,%R13

(284) 0x43e81f ADD	%R8,%RDX

(284) 0x43e822 ADD	%R8,%RCX

(284) 0x43e825 LEA	(%R10,%RCX,8),%R11

(284) 0x43e829 VMOVSD	(%R11),%XMM0

(284) 0x43e82e VMULSD	(%R9,%R14,8),%XMM0,%XMM8

(284) 0x43e834 VDIVSD	%XMM0,%XMM17,%XMM3

(284) 0x43e83a VMULSD	%XMM16,%XMM8,%XMM2

(284) 0x43e840 VMULSD	%XMM3,%XMM3,%XMM11

(284) 0x43e844 VMOVSD	%XMM2,(%R12,%R13,8)

(284) 0x43e84a VMULSD	(%R11),%XMM15,%XMM9

(284) 0x43e84f VMULSD	%XMM2,%XMM9,%XMM10

(284) 0x43e853 VMULSD	%XMM11,%XMM10,%XMM14

(284) 0x43e858 VSQRTSD	%XMM14,%XMM14,%XMM14

(284) 0x43e85d VMOVSD	%XMM14,(%R15,%RDX,8)

(284) 0x43e863 MOV	%EBX,%ECX

(284) 0x43e865 INC	%RDI

(284) 0x43e868 CMP	%EDI,0x14(%RSP)

(284) 0x43e86c JLE	43e890

(284) 0x43e86e MOV	0xc(%RSP),%EAX

(284) 0x43e872 MOV	0x10(%RSP),%EBX

(284) 0x43e876 MOV	0x38(%RSP),%R12D

(284) 0x43e87b SUB	%ECX,%EAX

(284) 0x43e87d MOV	%EBX,0x3c(%RSP)

(284) 0x43e881 JMP	43e390

0x43e886 NOPW	%CS:(%RAX,%RAX,1)

0x43e890 VZEROUPPER

0x43e893 LEA	-0x28(%RBP),%RSP

0x43e897 POP	%RBX

0x43e898 POP	%R12

0x43e89a POP	%R13

0x43e89c POP	%R14

0x43e89e POP	%R15

0x43e8a0 POP	%RBP

0x43e8a1 RET

0x43e8a2 NOPW	%CS:(%RAX,%RAX,1)

0x43e8ad NOPL	(%RAX)

(284) 0x43e8b0 MOV	0x3c(%RSP),%R8D

(284) 0x43e8b5 XOR	%ESI,%ESI

(284) 0x43e8b7 JMP	43e69f

0x43e8bc INC	%R9D

0x43e8bf XOR	%EDX,%EDX

0x43e8c1 JMP	43e2f1

0x43e8c6 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.78+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.08+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	ideal_gas(global_variables&, i[...]	ideal_gas.cpp:47	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:47	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:60	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.05+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	ideal_gas(global_variables&, i[...]	ideal_gas.cpp:47	exec
○	PdV(global_variables&, bool)	PdV.cpp:115	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:64	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	ideal_gas.cpp:37-45
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:37-45
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 3.00 cycles (4.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.80 cycles (15.09x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.75 cycles (1.12x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.50 cycles (1.14x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:45

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 84 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	87
nb uops	86
loop length	350
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	3
used zmm registers	3
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	5.25	5.25	5.25	5.25	0.00	3.00	3.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	5.25	5.25	5.25	5.25	0.00	3.00	3.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	8%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (7.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43e270

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x24(%R14),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x2,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RBX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %EDI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43e893 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x2(%RCX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
SUB %R15D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R12D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43e893 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 43e8bc <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x64c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R8D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 43e893 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVQ 0x18(%R14),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
DIVL 0x38(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ (%R14),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x8(%R14),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x2565f(%RIP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x10(%R14),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x26587(%RIP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x26587(%RIP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM17,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM16,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM15,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM17,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM16,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM15,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVDQA64 %XMM1,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB %R10D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10D,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 43e2f1 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x81>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	ideal_gas.cpp:37-45
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:37-45
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 3.00 cycles (4.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.50 cycles (1.14x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:39
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/ideal_gas.cpp:45

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 84 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	87
nb uops	86
loop length	350
used x86 registers	15
used mmx registers	0
used xmm registers	8
used ymm registers	3
used zmm registers	3
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.75 cycles
front end	10.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	5.25	5.25	5.25	5.25	0.00	3.00	3.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	5.25	5.25	5.25	5.25	0.00	3.00	3.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	7%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	15%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	5%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	11%

Vector efficiency ratios

INT

all	8%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	9%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (7.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43e270

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x24(%R14),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x2,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RBX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA 0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %EDI,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43e893 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x2(%RCX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
SUB %R15D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R12D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43e893 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R12D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 43e8bc <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x64c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R8D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 43e893 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x623>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVQ 0x18(%R14),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x10(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
DIVL 0x38(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ (%R14),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x8(%R14),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x2565f(%RIP),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x10(%R14),%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x26587(%RIP),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x26587(%RIP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM17,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM16,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM15,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM17,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM16,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM15,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVDQA64 %XMM1,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB %R10D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10D,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 43e2f1 <_Z16ideal_gas_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_._omp_fn.0+0x81>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼ideal_gas_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone ._omp_fn.0]–	5.55	2.04
▼Loop 284 - ideal_gas.cpp:39-45 - exec–	0.01	0.01
○Loop 285 - ideal_gas.cpp:40-45 - exec	5.55	2.03

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code