OV - exec - Function generate_chunk(int, global_variables&) [clone ._omp

	Function: generate_chunk(int, global_variables&) [clone ._omp_fn.0]	Module: exec	Source: generate_chunk.cpp:74-80 [...]	Coverage (incl. loops): 0.04% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp: 74 - 80

--------------------------------------------------------------------------------

74: #pragma omp parallel for simd collapse(2)

75:   for (int j = (0); j < (yrange); j++) {

76:     for (int i = (0); i < (xrange); i++) {

77:       field.energy0(i, j) = state_energy[0];

78:       field.density0(i, j) = state_density[0];

79:       field.xvel0(i, j) = state_xvel[0];

80:       field.yvel0(i, j) = state_yvel[0];

0x43c3e0 PUSH	%RBP

0x43c3e1 MOV	%RSP,%RBP

0x43c3e4 PUSH	%R15

0x43c3e6 PUSH	%R14

0x43c3e8 PUSH	%R13

0x43c3ea PUSH	%R12

0x43c3ec PUSH	%RBX

0x43c3ed AND	$-0x40,%RSP

0x43c3f1 SUB	$0x40,%RSP

0x43c3f5 MOV	0x2c(%RDI),%EBX

0x43c3f8 MOV	0x28(%RDI),%R15D

0x43c3fc MOV	%EBX,0xc(%RSP)

0x43c400 MOV	%R15D,0x8(%RSP)

0x43c405 TEST	%EBX,%EBX

0x43c407 JLE	43c973

0x43c40d TEST	%R15D,%R15D

0x43c410 JLE	43c973

0x43c416 IMUL	%R15D,%EBX

0x43c41a MOV	%RDI,%R13

0x43c41d CALL	404630 <omp_get_num_threads@plt>

0x43c422 MOV	%EAX,%R14D

0x43c425 CALL	404520 <omp_get_thread_num@plt>

0x43c42a XOR	%EDX,%EDX

0x43c42c MOV	%EAX,%ESI

0x43c42e MOV	%EBX,%EAX

0x43c430 DIV	%R14D

0x43c433 MOV	%EAX,%EBX

0x43c435 CMP	%EDX,%ESI

0x43c437 JB	43c99c

0x43c43d IMUL	%EBX,%ESI

0x43c440 ADD	%EDX,%ESI

0x43c442 LEA	(%RBX,%RSI,1),%EDI

0x43c445 MOV	%EDI,0x4(%RSP)

0x43c449 CMP	%EDI,%ESI

0x43c44b JAE	43c973

0x43c451 MOV	0x8(%RSP),%R12D

0x43c456 MOV	%ESI,%EAX

0x43c458 XOR	%EDX,%EDX

0x43c45a VMOVQ	0x8(%R13),%XMM17

0x43c461 VMOVQ	(%R13),%XMM16

0x43c468 VMOVQ	0x10(%R13),%XMM15

0x43c46e MOV	0x20(%R13),%R14

0x43c472 VMOVQ	0x18(%R13),%XMM14

0x43c478 DIV	%R12D

0x43c47b VMOVDQA64	%XMM17,%XMM8

0x43c481 SUB	%EDX,%R12D

0x43c484 MOVSXD	%EAX,%R8

0x43c487 MOV	%EDX,0x3c(%RSP)

0x43c48b NOPL	(%RAX,%RAX,1)

(276) 0x43c490 CMP	%R12D,%EBX

(276) 0x43c493 CMOVBE	%EBX,%R12D

(276) 0x43c497 LEA	(%RSI,%R12,1),%ECX

(276) 0x43c49b MOV	%R12D,%EDX

(276) 0x43c49e MOV	%ECX,0x38(%RSP)

(276) 0x43c4a2 CMP	%ECX,%ESI

(276) 0x43c4a4 JAE	43c948

(276) 0x43c4aa VMOVQ	%XMM15,%R12

(276) 0x43c4af MOV	0x30(%R14),%RBX

(276) 0x43c4b3 MOV	(%R14),%R13

(276) 0x43c4b6 MOV	0xd8(%R14),%RAX

(276) 0x43c4bd MOV	0x8(%R12),%RDI

(276) 0x43c4c2 MOV	0xa8(%R14),%R12

(276) 0x43c4c9 VMOVQ	%XMM8,%R9

(276) 0x43c4ce VMOVQ	%XMM16,%R10

(276) 0x43c4d4 VMOVQ	%XMM14,%R15

(276) 0x43c4d9 LEA	-0x1(%RDX),%ECX

(276) 0x43c4dc VMOVQ	0x40(%R14),%XMM12

(276) 0x43c4e2 VMOVQ	0x10(%R14),%XMM11

(276) 0x43c4e8 VMOVQ	0xb8(%R14),%XMM10

(276) 0x43c4f1 VMOVQ	0xe8(%R14),%XMM9

(276) 0x43c4fa MOV	0x8(%R9),%R11

(276) 0x43c4fe MOV	0x8(%R10),%R10

(276) 0x43c502 MOV	0x8(%R15),%R15

(276) 0x43c506 IMUL	%R8,%RBX

(276) 0x43c50a IMUL	%R8,%R13

(276) 0x43c50e IMUL	%R8,%R12

(276) 0x43c512 IMUL	%R8,%RAX

(276) 0x43c516 MOV	%RBX,0x30(%RSP)

(276) 0x43c51b MOV	%R13,0x10(%RSP)

(276) 0x43c520 MOV	%R12,0x18(%RSP)

(276) 0x43c525 MOV	%RAX,0x28(%RSP)

(276) 0x43c52a CMP	$0x6,%ECX

(276) 0x43c52d JBE	43c990

(276) 0x43c533 MOVSXD	0x3c(%RSP),%RAX

(276) 0x43c538 LEA	(%R13,%RAX,1),%RCX

(276) 0x43c53d VMOVQ	%XMM11,%R13

(276) 0x43c542 LEA	(%RBX,%RAX,1),%R9

(276) 0x43c546 LEA	(%R12,%RAX,1),%R12

(276) 0x43c54a LEA	(%R13,%RCX,8),%R13

(276) 0x43c54f MOV	0x28(%RSP),%RCX

(276) 0x43c554 VMOVQ	%XMM12,%RBX

(276) 0x43c559 LEA	(%RBX,%R9,8),%RBX

(276) 0x43c55d VMOVQ	%XMM10,%R9

(276) 0x43c562 LEA	(%R9,%R12,8),%R12

(276) 0x43c566 VMOVQ	%XMM9,%R9

(276) 0x43c56b ADD	%RCX,%RAX

(276) 0x43c56e MOV	%EDX,%ECX

(276) 0x43c570 SHR	$0x3,%ECX

(276) 0x43c573 SAL	$0x6,%RCX

(276) 0x43c577 MOV	%RCX,0x20(%RSP)

(276) 0x43c57c SUB	$0x40,%RCX

(276) 0x43c580 LEA	(%R9,%RAX,8),%R9

(276) 0x43c584 XOR	%EAX,%EAX

(276) 0x43c586 SHR	$0x6,%RCX

(276) 0x43c58a INC	%RCX

(276) 0x43c58d AND	$0x3,%ECX

(276) 0x43c590 JE	43c659

(276) 0x43c596 CMP	$0x1,%RCX

(276) 0x43c59a JE	43c612

(276) 0x43c59c CMP	$0x2,%RCX

(276) 0x43c5a0 JE	43c5d9

(276) 0x43c5a2 VBROADCASTSD	(%R11),%ZMM13

(276) 0x43c5a8 MOV	$0x40,%EAX

(276) 0x43c5ad VMOVUPD	%ZMM13,(%RBX)

(276) 0x43c5b3 VBROADCASTSD	(%R10),%ZMM0

(276) 0x43c5b9 VMOVUPD	%ZMM0,(%R13)

(276) 0x43c5c0 VBROADCASTSD	(%RDI),%ZMM1

(276) 0x43c5c6 VMOVUPD	%ZMM1,(%R12)

(276) 0x43c5cd VBROADCASTSD	(%R15),%ZMM2

(276) 0x43c5d3 VMOVUPD	%ZMM2,(%R9)

(276) 0x43c5d9 VBROADCASTSD	(%R11),%ZMM3

(276) 0x43c5df VMOVUPD	%ZMM3,(%RBX,%RAX,1)

(276) 0x43c5e6 VBROADCASTSD	(%R10),%ZMM4

(276) 0x43c5ec VMOVUPD	%ZMM4,(%R13,%RAX,1)

(276) 0x43c5f4 VBROADCASTSD	(%RDI),%ZMM5

(276) 0x43c5fa VMOVUPD	%ZMM5,(%R12,%RAX,1)

(276) 0x43c601 VBROADCASTSD	(%R15),%ZMM6

(276) 0x43c607 VMOVUPD	%ZMM6,(%R9,%RAX,1)

(276) 0x43c60e ADD	$0x40,%RAX

(276) 0x43c612 VBROADCASTSD	(%R11),%ZMM7

(276) 0x43c618 MOV	0x20(%RSP),%RCX

(276) 0x43c61d VMOVUPD	%ZMM7,(%RBX,%RAX,1)

(276) 0x43c624 VBROADCASTSD	(%R10),%ZMM13

(276) 0x43c62a VMOVUPD	%ZMM13,(%R13,%RAX,1)

(276) 0x43c632 VBROADCASTSD	(%RDI),%ZMM0

(276) 0x43c638 VMOVUPD	%ZMM0,(%R12,%RAX,1)

(276) 0x43c63f VBROADCASTSD	(%R15),%ZMM1

(276) 0x43c645 VMOVUPD	%ZMM1,(%R9,%RAX,1)

(276) 0x43c64c ADD	$0x40,%RAX

(276) 0x43c650 CMP	%RCX,%RAX

(276) 0x43c653 JE	43c75c

(276) 0x43c659 MOV	%R8,%RCX

(276) 0x43c65c MOV	%EDX,%R8D

(276) 0x43c65f MOV	%RCX,%RDX

  (277) 0x43c662 VBROADCASTSD	(%R11),%ZMM2

  (277) 0x43c668 VMOVUPD	%ZMM2,(%RBX,%RAX,1)

  (277) 0x43c66f VBROADCASTSD	(%R10),%ZMM3

  (277) 0x43c675 VMOVUPD	%ZMM3,(%R13,%RAX,1)

  (277) 0x43c67d VBROADCASTSD	(%RDI),%ZMM4

  (277) 0x43c683 VMOVUPD	%ZMM4,(%R12,%RAX,1)

  (277) 0x43c68a VBROADCASTSD	(%R15),%ZMM5

  (277) 0x43c690 VMOVUPD	%ZMM5,(%R9,%RAX,1)

  (277) 0x43c697 VBROADCASTSD	(%R11),%ZMM6

  (277) 0x43c69d VMOVUPD	%ZMM6,0x40(%RBX,%RAX,1)

  (277) 0x43c6a5 VBROADCASTSD	(%R10),%ZMM7

  (277) 0x43c6ab VMOVUPD	%ZMM7,0x40(%R13,%RAX,1)

  (277) 0x43c6b3 VBROADCASTSD	(%RDI),%ZMM13

  (277) 0x43c6b9 VMOVUPD	%ZMM13,0x40(%R12,%RAX,1)

  (277) 0x43c6c1 VBROADCASTSD	(%R15),%ZMM0

  (277) 0x43c6c7 VMOVUPD	%ZMM0,0x40(%R9,%RAX,1)

  (277) 0x43c6cf VBROADCASTSD	(%R11),%ZMM1

  (277) 0x43c6d5 VMOVUPD	%ZMM1,0x80(%RBX,%RAX,1)

  (277) 0x43c6dd VBROADCASTSD	(%R10),%ZMM2

  (277) 0x43c6e3 VMOVUPD	%ZMM2,0x80(%R13,%RAX,1)

  (277) 0x43c6eb VBROADCASTSD	(%RDI),%ZMM3

  (277) 0x43c6f1 VMOVUPD	%ZMM3,0x80(%R12,%RAX,1)

  (277) 0x43c6f9 VBROADCASTSD	(%R15),%ZMM4

  (277) 0x43c6ff VMOVUPD	%ZMM4,0x80(%R9,%RAX,1)

  (277) 0x43c707 VBROADCASTSD	(%R11),%ZMM5

  (277) 0x43c70d VMOVUPD	%ZMM5,0xc0(%RBX,%RAX,1)

  (277) 0x43c715 VBROADCASTSD	(%R10),%ZMM6

  (277) 0x43c71b VMOVUPD	%ZMM6,0xc0(%R13,%RAX,1)

  (277) 0x43c723 VBROADCASTSD	(%RDI),%ZMM7

  (277) 0x43c729 VMOVUPD	%ZMM7,0xc0(%R12,%RAX,1)

  (277) 0x43c731 VBROADCASTSD	(%R15),%ZMM13

  (277) 0x43c737 VMOVUPD	%ZMM13,0xc0(%R9,%RAX,1)

  (277) 0x43c73f MOV	0x20(%RSP),%RCX

  (277) 0x43c744 ADD	$0x100,%RAX

  (277) 0x43c74a CMP	%RCX,%RAX

  (277) 0x43c74d JNE	43c662

(276) 0x43c753 MOV	%RDX,%RBX

(276) 0x43c756 MOV	%R8D,%EDX

(276) 0x43c759 MOV	%RBX,%R8

(276) 0x43c75c MOV	0x3c(%RSP),%R12D

(276) 0x43c761 MOV	%EDX,%R13D

(276) 0x43c764 AND	$-0x8,%R13D

(276) 0x43c768 ADD	%R13D,%ESI

(276) 0x43c76b LEA	(%R13,%R12,1),%ECX

(276) 0x43c770 TEST	$0x7,%DL

(276) 0x43c773 JE	43c944

(276) 0x43c779 SUB	%R13D,%EDX

(276) 0x43c77c LEA	-0x1(%RDX),%R9D

(276) 0x43c780 CMP	$0x2,%R9D

(276) 0x43c784 JBE	43c823

(276) 0x43c78a MOVSXD	0x3c(%RSP),%R9

(276) 0x43c78f MOV	0x30(%RSP),%RAX

(276) 0x43c794 VBROADCASTSD	(%R11),%YMM3

(276) 0x43c799 VMOVQ	%XMM12,%RBX

(276) 0x43c79e VMOVSD	(%R10),%XMM0

(276) 0x43c7a3 VMOVSD	(%RDI),%XMM1

(276) 0x43c7a7 VMOVSD	(%R15),%XMM2

(276) 0x43c7ac VBROADCASTSD	%XMM0,%YMM4

(276) 0x43c7b1 VBROADCASTSD	%XMM1,%YMM5

(276) 0x43c7b6 VBROADCASTSD	%XMM2,%YMM6

(276) 0x43c7bb LEA	(%RAX,%R9,1),%R12

(276) 0x43c7bf MOV	0x10(%RSP),%RAX

(276) 0x43c7c4 ADD	%R13,%R12

(276) 0x43c7c7 VMOVUPD	%YMM3,(%RBX,%R12,8)

(276) 0x43c7cd VMOVQ	%XMM11,%RBX

(276) 0x43c7d2 LEA	(%RAX,%R9,1),%R12

(276) 0x43c7d6 MOV	0x18(%RSP),%RAX

(276) 0x43c7db ADD	%R13,%R12

(276) 0x43c7de VMOVUPD	%YMM4,(%RBX,%R12,8)

(276) 0x43c7e4 VMOVQ	%XMM10,%RBX

(276) 0x43c7e9 LEA	(%RAX,%R9,1),%R12

(276) 0x43c7ed MOV	0x28(%RSP),%RAX

(276) 0x43c7f2 ADD	%R13,%R12

(276) 0x43c7f5 VMOVUPD	%YMM5,(%RBX,%R12,8)

(276) 0x43c7fb ADD	%RAX,%R9

(276) 0x43c7fe ADD	%R13,%R9

(276) 0x43c801 VMOVQ	%XMM9,%R13

(276) 0x43c806 VMOVUPD	%YMM6,(%R13,%R9,8)

(276) 0x43c80d MOV	%EDX,%R9D

(276) 0x43c810 AND	$-0x4,%R9D

(276) 0x43c814 ADD	%R9D,%ECX

(276) 0x43c817 ADD	%R9D,%ESI

(276) 0x43c81a AND	$0x3,%EDX

(276) 0x43c81d JE	43c944

(276) 0x43c823 MOV	0x30(%RSP),%RBX

(276) 0x43c828 MOV	0x10(%RSP),%R9

(276) 0x43c82d MOVSXD	%ECX,%RAX

(276) 0x43c830 VMOVQ	%XMM12,%R12

(276) 0x43c835 VMOVSD	(%R11),%XMM7

(276) 0x43c83a VMOVQ	%XMM11,%R13

(276) 0x43c83f LEA	(%RBX,%RAX,1),%RDX

(276) 0x43c843 VMOVSD	%XMM7,(%R12,%RDX,8)

(276) 0x43c849 LEA	(%R9,%RAX,1),%RDX

(276) 0x43c84d VMOVSD	(%R10),%XMM13

(276) 0x43c852 VMOVQ	%XMM10,%R12

(276) 0x43c857 VMOVSD	%XMM13,(%R13,%RDX,8)

(276) 0x43c85e MOV	0x18(%RSP),%R13

(276) 0x43c863 VMOVSD	(%RDI),%XMM0

(276) 0x43c867 LEA	(%R13,%RAX,1),%RDX

(276) 0x43c86c VMOVSD	%XMM0,(%R12,%RDX,8)

(276) 0x43c872 MOV	0x28(%RSP),%R12

(276) 0x43c877 VMOVQ	%XMM9,%RDX

(276) 0x43c87c VMOVSD	(%R15),%XMM1

(276) 0x43c881 ADD	%R12,%RAX

(276) 0x43c884 VMOVSD	%XMM1,(%RDX,%RAX,8)

(276) 0x43c889 MOV	0x38(%RSP),%EDX

(276) 0x43c88d LEA	0x1(%RSI),%EAX

(276) 0x43c890 CMP	%EDX,%EAX

(276) 0x43c892 JAE	43c944

(276) 0x43c898 LEA	0x1(%RCX),%EAX

(276) 0x43c89b VMOVSD	(%R11),%XMM2

(276) 0x43c8a0 ADD	$0x2,%ESI

(276) 0x43c8a3 CLTQ

(276) 0x43c8a5 LEA	(%RBX,%RAX,1),%RDX

(276) 0x43c8a9 VMOVQ	%XMM12,%RBX

(276) 0x43c8ae VMOVSD	%XMM2,(%RBX,%RDX,8)

(276) 0x43c8b3 LEA	(%R9,%RAX,1),%RDX

(276) 0x43c8b7 VMOVQ	%XMM11,%RBX

(276) 0x43c8bc VMOVSD	(%R10),%XMM3

(276) 0x43c8c1 VMOVSD	%XMM3,(%RBX,%RDX,8)

(276) 0x43c8c6 LEA	(%R13,%RAX,1),%RDX

(276) 0x43c8cb VMOVQ	%XMM10,%RBX

(276) 0x43c8d0 ADD	%R12,%RAX

(276) 0x43c8d3 VMOVSD	(%RDI),%XMM4

(276) 0x43c8d7 VMOVSD	%XMM4,(%RBX,%RDX,8)

(276) 0x43c8dc VMOVQ	%XMM9,%RDX

(276) 0x43c8e1 VMOVSD	(%R15),%XMM5

(276) 0x43c8e6 VMOVSD	%XMM5,(%RDX,%RAX,8)

(276) 0x43c8eb MOV	0x38(%RSP),%EAX

(276) 0x43c8ef CMP	%EAX,%ESI

(276) 0x43c8f1 JAE	43c944

(276) 0x43c8f3 VMOVSD	(%R11),%XMM6

(276) 0x43c8f8 MOV	0x30(%RSP),%R11

(276) 0x43c8fd ADD	$0x2,%ECX

(276) 0x43c900 MOVSXD	%ECX,%RSI

(276) 0x43c903 VMOVQ	%XMM12,%RCX

(276) 0x43c908 ADD	%RSI,%R9

(276) 0x43c90b ADD	%RSI,%R13

(276) 0x43c90e ADD	%RSI,%R12

(276) 0x43c911 ADD	%RSI,%R11

(276) 0x43c914 VMOVSD	%XMM6,(%RCX,%R11,8)

(276) 0x43c91a VMOVSD	(%R10),%XMM12

(276) 0x43c91f VMOVQ	%XMM11,%R10

(276) 0x43c924 VMOVSD	%XMM12,(%R10,%R9,8)

(276) 0x43c92a VMOVSD	(%RDI),%XMM11

(276) 0x43c92e VMOVSD	%XMM11,(%RBX,%R13,8)

(276) 0x43c934 VMOVSD	(%R15),%XMM10

(276) 0x43c939 VMOVQ	%XMM9,%R15

(276) 0x43c93e VMOVSD	%XMM10,(%R15,%R12,8)

(276) 0x43c944 MOV	0x38(%RSP),%ESI

(276) 0x43c948 INC	%R8

(276) 0x43c94b CMP	%R8D,0xc(%RSP)

(276) 0x43c950 JLE	43c970

(276) 0x43c952 MOV	0x4(%RSP),%EBX

(276) 0x43c956 MOV	0x8(%RSP),%R12D

(276) 0x43c95b MOVL	$0,0x3c(%RSP)

(276) 0x43c963 SUB	%ESI,%EBX

(276) 0x43c965 JMP	43c490

0x43c96a NOPW	(%RAX,%RAX,1)

0x43c970 VZEROUPPER

0x43c973 LEA	-0x28(%RBP),%RSP

0x43c977 POP	%RBX

0x43c978 POP	%R12

0x43c97a POP	%R13

0x43c97c POP	%R14

0x43c97e POP	%R15

0x43c980 POP	%RBP

0x43c981 RET

0x43c982 NOPW	%CS:(%RAX,%RAX,1)

0x43c98d NOPL	(%RAX)

(276) 0x43c990 MOV	0x3c(%RSP),%ECX

(276) 0x43c994 XOR	%R13D,%R13D

(276) 0x43c997 JMP	43c779

0x43c99c INC	%EBX

0x43c99e XOR	%EDX,%EDX

0x43c9a0 JMP	43c43d

0x43c9a5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.83+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►3.17+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	generate_chunk(int, global_var[...]	generate_chunk.cpp:84	exec
○	start(parallel_&, global_confi[...]	start.cpp:81	exec
○	initialise(parallel_&, std::ve[...]	clover_leaf.cpp:192	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74-80

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.88 cycles (6.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 8.00 cycles (1.50x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.75 cycles (1.55x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:80

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	65
nb uops	64
loop length	234
used x86 registers	12
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	8.00
Dispatch	4.33
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	18%

Vector efficiency ratios

all	9%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (4.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43c3e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x2c(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %EBX,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R15D,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
TEST %EBX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 43c973 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x593>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
TEST %R15D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 43c973 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x593>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R15D,%EBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 43c99c <_Z14generate_chunkiR16global_variables._omp_fn.0+0x5bc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EBX,%ESI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RBX,%RSI,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDI,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 43c973 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x593>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%RSP),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVQ 0x8(%R13),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ (%R13),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x20(%R13),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
VMOVQ 0x18(%R13),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
VMOVDQA64 %XMM17,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SUB %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 43c43d <_Z14generate_chunkiR16global_variables._omp_fn.0+0x5d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	generate_chunk.cpp:74-80
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74-80

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.88 cycles (6.40x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 7.75 cycles (1.55x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:74
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/generate_chunk.cpp:80

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	65
nb uops	64
loop length	234
used x86 registers	12
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	5

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	8.00 cycles
front end	8.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	4.33	4.33	4.33	4.33	4.33	4.33	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	4.33	4.33	4.33	4.33	4.33	4.33	3.50	3.50	3.50	3.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	8.00
Dispatch	4.33
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	8%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	18%

Vector efficiency ratios

all	9%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (4.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43c3e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x2c(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %EBX,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %R15D,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
TEST %EBX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 43c973 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x593>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
TEST %R15D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JLE 43c973 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x593>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R15D,%EBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EBX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R14D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 43c99c <_Z14generate_chunkiR16global_variables._omp_fn.0+0x5bc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %EBX,%ESI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%RBX,%RSI,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDI,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 43c973 <_Z14generate_chunkiR16global_variables._omp_fn.0+0x593>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV 0x8(%RSP),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
VMOVQ 0x8(%R13),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ (%R13),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x20(%R13),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
VMOVQ 0x18(%R13),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
VMOVDQA64 %XMM17,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
SUB %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 43c43d <_Z14generate_chunkiR16global_variables._omp_fn.0+0x5d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼generate_chunk(int, global_variables&) [clone ._omp_fn.0]–	0.04	0.02
▼Loop 276 - generate_chunk.cpp:74-80 - exec–	0.00	0.00
○Loop 277 - generate_chunk.cpp:77-80 - exec	0.04	0.02

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