OV - exec - Function flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone ._omp

	Function: flux_calc_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<d ...	Module: exec	Source: flux_calc.cpp:36-40 [...]	Coverage (incl. loops): 4.33% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp: 36 - 40

--------------------------------------------------------------------------------

36: #pragma omp parallel for simd collapse(2)

37:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

38:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

39:       vol_flux_x(i, j) = 0.25 * dt * xarea(i, j) * (xvel0(i, j) + xvel0(i + 0, j + 1) + xvel1(i, j) + xvel1(i + 0, j + 1));

40:       vol_flux_y(i, j) = 0.25 * dt * yarea(i, j) * (yvel0(i, j) + yvel0(i + 1, j + 0) + yvel1(i, j) + yvel1(i + 1, j + 0));

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x43b910 PUSH	%RBP

0x43b911 MOV	%RSP,%RBP

0x43b914 PUSH	%R15

0x43b916 PUSH	%R14

0x43b918 PUSH	%R13

0x43b91a PUSH	%R12

0x43b91c PUSH	%RBX

0x43b91d MOV	%RDI,%RBX

0x43b920 AND	$-0x40,%RSP

0x43b924 ADD	$-0x80,%RSP

0x43b928 MOV	0x50(%RDI),%EAX

0x43b92b MOV	0x54(%RDI),%ECX

0x43b92e MOV	0x48(%RDI),%EDX

0x43b931 MOV	0x4c(%RDI),%EDI

0x43b934 ADD	$0x3,%ECX

0x43b937 INC	%EDX

0x43b939 LEA	0x1(%RAX),%R12D

0x43b93d MOV	%ECX,0x14(%RSP)

0x43b941 MOV	%EDX,0x10(%RSP)

0x43b945 CMP	%ECX,%R12D

0x43b948 JGE	43c1e3

0x43b94e MOV	%ECX,%R14D

0x43b951 LEA	0x3(%RDI),%R15D

0x43b955 SUB	%R12D,%R14D

0x43b958 CMP	%R15D,%EDX

0x43b95b JGE	43c1e3

0x43b961 MOV	%R15D,%ESI

0x43b964 SUB	%EDX,%ESI

0x43b966 MOV	%ESI,0x60(%RSP)

0x43b96a CALL	404630 <omp_get_num_threads@plt>

0x43b96f MOV	%EAX,%R13D

0x43b972 CALL	404520 <omp_get_thread_num@plt>

0x43b977 XOR	%EDX,%EDX

0x43b979 MOV	%EAX,%R8D

0x43b97c MOV	0x60(%RSP),%EAX

0x43b980 IMUL	%R14D,%EAX

0x43b984 DIV	%R13D

0x43b987 MOV	%EAX,%R9D

0x43b98a CMP	%EDX,%R8D

0x43b98d JB	43c20c

0x43b993 IMUL	%R9D,%R8D

0x43b997 LEA	(%R8,%RDX,1),%R10D

0x43b99b LEA	(%R9,%R10,1),%R11D

0x43b99f MOV	%R11D,0xc(%RSP)

0x43b9a4 CMP	%R11D,%R10D

0x43b9a7 JAE	43c1e3

0x43b9ad MOV	%R10D,%EAX

0x43b9b0 XOR	%EDX,%EDX

0x43b9b2 MOV	0x10(%RSP),%ECX

0x43b9b6 VMOVQ	0x8(%RBX),%XMM28

0x43b9bd DIVL	0x60(%RSP)

0x43b9c1 VMOVQ	0x18(%RBX),%XMM27

0x43b9c8 VMOVQ	0x28(%RBX),%XMM26

0x43b9cf VMOVSD	0x28cc7(%RIP),%XMM22

0x43b9d9 VMOVQ	0x38(%RBX),%XMM25

0x43b9e0 VMULSD	(%RBX),%XMM22,%XMM22

0x43b9e6 VMOVQ	0x10(%RBX),%XMM24

0x43b9ed MOV	%R15D,%EDI

0x43b9f0 VMOVQ	0x20(%RBX),%XMM23

0x43b9f7 VMOVQ	0x30(%RBX),%XMM31

0x43b9fe MOV	0x40(%RBX),%RBX

0x43ba02 VBROADCASTSD	%XMM22,%YMM29

0x43ba08 VBROADCASTSD	%XMM22,%ZMM1

0x43ba0e MOV	%R9D,%R15D

0x43ba11 VMOVQ	%RBX,%XMM8

0x43ba16 ADD	%EDX,%ECX

0x43ba18 ADD	%R12D,%EAX

0x43ba1b SUB	%ECX,%EDI

0x43ba1d MOVSXD	%EAX,%R14

0x43ba20 MOV	%ECX,0x78(%RSP)

0x43ba24 MOV	%EDI,%R11D

0x43ba27 NOPW	(%RAX,%RAX,1)

(273) 0x43ba30 CMP	%R11D,%R15D

(273) 0x43ba33 CMOVBE	%R15D,%R11D

(273) 0x43ba37 LEA	(%R10,%R11,1),%R12D

(273) 0x43ba3b MOV	%R11D,0x7c(%RSP)

(273) 0x43ba40 MOV	%R12D,0x64(%RSP)

(273) 0x43ba45 CMP	%R12D,%R10D

(273) 0x43ba48 JAE	43c1bc

(273) 0x43ba4e VMOVQ	%XMM26,%R9

(273) 0x43ba54 VMOVQ	%XMM27,%RSI

(273) 0x43ba5a MOV	(%R9),%R11

(273) 0x43ba5d MOV	(%RSI),%R13

(273) 0x43ba60 VMOVQ	%XMM25,%RBX

(273) 0x43ba66 VMOVQ	%XMM28,%R15

(273) 0x43ba6c VMOVQ	%XMM24,%RCX

(273) 0x43ba72 VMOVQ	%XMM23,%R12

(273) 0x43ba78 VMOVQ	0x10(%RSI),%XMM6

(273) 0x43ba7d VMOVQ	0x10(%RBX),%XMM15

(273) 0x43ba82 MOV	(%R15),%R8

(273) 0x43ba85 VMOVQ	0x10(%R15),%XMM16

(273) 0x43ba8c VMOVQ	0x10(%R9),%XMM5

(273) 0x43ba92 MOV	(%R12),%R15

(273) 0x43ba96 VMOVQ	0x10(%R12),%XMM4

(273) 0x43ba9d VMOVQ	0x10(%RCX),%XMM14

(273) 0x43baa2 MOV	%R11,%RDI

(273) 0x43baa5 VMOVQ	%XMM31,%RSI

(273) 0x43baab MOV	%R13,%RAX

(273) 0x43baae IMUL	%R14,%RDI

(273) 0x43bab2 MOV	(%RSI),%R9

(273) 0x43bab5 VMOVQ	0x10(%RSI),%XMM7

(273) 0x43baba IMUL	%R14,%RAX

(273) 0x43babe IMUL	%R14,%R8

(273) 0x43bac2 LEA	(%R11,%RDI,1),%RDX

(273) 0x43bac6 MOV	(%RCX),%R11

(273) 0x43bac9 MOV	0x7c(%RSP),%ECX

(273) 0x43bacd IMUL	%R14,%R15

(273) 0x43bad1 MOV	%RDX,0x70(%RSP)

(273) 0x43bad6 MOV	(%RBX),%RDX

(273) 0x43bad9 VMOVQ	%XMM8,%RBX

(273) 0x43bade LEA	(%R13,%RAX,1),%R13

(273) 0x43bae3 MOV	(%RBX),%R12

(273) 0x43bae6 IMUL	%R14,%R9

(273) 0x43baea VMOVQ	0x10(%RBX),%XMM13

(273) 0x43baef MOV	%R8,0x40(%RSP)

(273) 0x43baf4 MOV	%RAX,0x48(%RSP)

(273) 0x43baf9 MOV	%R13,0x50(%RSP)

(273) 0x43bafe MOV	%RDI,0x18(%RSP)

(273) 0x43bb03 MOV	%R15,0x28(%RSP)

(273) 0x43bb08 IMUL	%R14,%R11

(273) 0x43bb0c LEA	-0x1(%RCX),%ESI

(273) 0x43bb0f MOV	%R9,0x30(%RSP)

(273) 0x43bb14 IMUL	%R14,%RDX

(273) 0x43bb18 IMUL	%R14,%R12

(273) 0x43bb1c MOV	%R11,0x38(%RSP)

(273) 0x43bb21 MOV	%RDX,0x20(%RSP)

(273) 0x43bb26 MOV	%R12,0x58(%RSP)

(273) 0x43bb2b CMP	$0x6,%ESI

(273) 0x43bb2e JBE	43c200

(273) 0x43bb34 MOVSXD	0x78(%RSP),%RCX

(273) 0x43bb39 VMOVQ	%XMM16,%RBX

(273) 0x43bb3f LEA	(%R8,%RCX,1),%RSI

(273) 0x43bb43 LEA	(%RAX,%RCX,1),%RAX

(273) 0x43bb47 LEA	(%R13,%RCX,1),%R13

(273) 0x43bb4c LEA	(%R15,%RCX,1),%R15

(273) 0x43bb50 LEA	(%RBX,%RSI,8),%R8

(273) 0x43bb54 VMOVQ	%XMM6,%RBX

(273) 0x43bb59 LEA	(%RDX,%RCX,1),%RDX

(273) 0x43bb5d LEA	(%R9,%RCX,1),%R9

(273) 0x43bb61 LEA	(%RBX,%R13,8),%RSI

(273) 0x43bb65 VMOVQ	%R8,%XMM3

(273) 0x43bb6a LEA	(%RBX,%RAX,8),%R8

(273) 0x43bb6e MOV	0x70(%RSP),%RBX

(273) 0x43bb73 LEA	(%RDI,%RCX,1),%RAX

(273) 0x43bb77 VMOVQ	%XMM5,%RDI

(273) 0x43bb7c VMOVQ	%RSI,%XMM17

(273) 0x43bb82 LEA	(%R11,%RCX,1),%R11

(273) 0x43bb86 SAL	$0x3,%R15

(273) 0x43bb8a VMOVQ	%XMM5,%RSI

(273) 0x43bb8f LEA	(%RDI,%RAX,8),%RDI

(273) 0x43bb93 VMOVQ	%XMM15,%RAX

(273) 0x43bb98 LEA	(%RBX,%RCX,1),%R13

(273) 0x43bb9c ADD	%R12,%RCX

(273) 0x43bb9f VMOVQ	%XMM13,%R12

(273) 0x43bba4 SAL	$0x3,%R9

(273) 0x43bba8 LEA	(%RSI,%R13,8),%RBX

(273) 0x43bbac LEA	(%RAX,%RDX,8),%R13

(273) 0x43bbb0 VMOVQ	%XMM14,%RSI

(273) 0x43bbb5 VMOVQ	%XMM4,%RAX

(273) 0x43bbba LEA	(%RAX,%R15,1),%RDX

(273) 0x43bbbe VMOVQ	%R13,%XMM2

(273) 0x43bbc3 LEA	(%RSI,%R11,8),%R13

(273) 0x43bbc7 LEA	0x8(%RAX,%R15,1),%R11

(273) 0x43bbcc VMOVQ	%XMM7,%RSI

(273) 0x43bbd1 VMOVQ	%XMM7,%RAX

(273) 0x43bbd6 LEA	(%R12,%RCX,8),%R12

(273) 0x43bbda XOR	%ECX,%ECX

(273) 0x43bbdc ADD	%R9,%RAX

(273) 0x43bbdf LEA	0x8(%RSI,%R9,1),%R15

(273) 0x43bbe4 MOV	0x7c(%RSP),%R9D

(273) 0x43bbe9 SHR	$0x3,%R9D

(273) 0x43bbed MOV	%R9,%RSI

(273) 0x43bbf0 SAL	$0x6,%RSI

(273) 0x43bbf4 AND	$0x1,%R9D

(273) 0x43bbf8 JE	43bc7e

(273) 0x43bbfe VMOVQ	%XMM17,%RCX

(273) 0x43bc04 VMOVUPD	(%R8),%ZMM30

(273) 0x43bc0a VMOVUPD	(%RDI),%ZMM0

(273) 0x43bc10 VMOVQ	%XMM3,%R9

(273) 0x43bc15 VADDPD	(%RCX),%ZMM30,%ZMM18

(273) 0x43bc1b VADDPD	(%RBX),%ZMM0,%ZMM9

(273) 0x43bc21 VMULPD	(%R9),%ZMM1,%ZMM19

(273) 0x43bc27 VMOVQ	%XMM2,%RCX

(273) 0x43bc2c VADDPD	%ZMM9,%ZMM18,%ZMM10

(273) 0x43bc32 VMULPD	%ZMM19,%ZMM10,%ZMM11

(273) 0x43bc38 VMOVUPD	%ZMM11,(%RCX)

(273) 0x43bc3e VMOVUPD	(%RDX),%ZMM20

(273) 0x43bc44 VMOVUPD	(%RAX),%ZMM12

(273) 0x43bc4a VADDPD	(%R11),%ZMM20,%ZMM21

(273) 0x43bc50 VADDPD	(%R15),%ZMM12,%ZMM0

(273) 0x43bc56 VMULPD	(%R13),%ZMM1,%ZMM30

(273) 0x43bc5d MOV	$0x40,%ECX

(273) 0x43bc62 VADDPD	%ZMM0,%ZMM21,%ZMM9

(273) 0x43bc68 VMULPD	%ZMM30,%ZMM9,%ZMM10

(273) 0x43bc6e VMOVUPD	%ZMM10,(%R12)

(273) 0x43bc75 CMP	%RSI,%RCX

(273) 0x43bc78 JE	43bd9f

(273) 0x43bc7e MOV	%R10D,0x8(%RSP)

(273) 0x43bc83 MOV	%R14,(%RSP)

(273) 0x43bc87 MOV	%RSI,0x68(%RSP)

(273) 0x43bc8c MOV	%R8,%R14

(273) 0x43bc8f VMOVQ	%XMM3,%R10

(273) 0x43bc94 VMOVQ	%XMM17,%R8

(273) 0x43bc9a VMOVQ	%XMM2,%RSI

  (274) 0x43bc9f VMOVUPD	(%R14,%RCX,1),%ZMM17

  (274) 0x43bca6 VMOVUPD	(%RDI,%RCX,1),%ZMM3

  (274) 0x43bcad VADDPD	(%R8,%RCX,1),%ZMM17,%ZMM18

  (274) 0x43bcb4 MOV	0x68(%RSP),%R9

  (274) 0x43bcb9 VADDPD	(%RBX,%RCX,1),%ZMM3,%ZMM2

  (274) 0x43bcc0 VMULPD	(%R10,%RCX,1),%ZMM1,%ZMM19

  (274) 0x43bcc7 VADDPD	%ZMM2,%ZMM18,%ZMM11

  (274) 0x43bccd VMULPD	%ZMM19,%ZMM11,%ZMM12

  (274) 0x43bcd3 VMOVUPD	%ZMM12,(%RSI,%RCX,1)

  (274) 0x43bcda VMOVUPD	(%RDX,%RCX,1),%ZMM20

  (274) 0x43bce1 VMOVUPD	(%RAX,%RCX,1),%ZMM0

  (274) 0x43bce8 VADDPD	(%R11,%RCX,1),%ZMM20,%ZMM21

  (274) 0x43bcef VADDPD	(%R15,%RCX,1),%ZMM0,%ZMM9

  (274) 0x43bcf6 VMULPD	(%R13,%RCX,1),%ZMM1,%ZMM30

  (274) 0x43bcfe VADDPD	%ZMM9,%ZMM21,%ZMM10

  (274) 0x43bd04 VMULPD	%ZMM30,%ZMM10,%ZMM3

  (274) 0x43bd0a VMOVUPD	%ZMM3,(%R12,%RCX,1)

  (274) 0x43bd11 VMOVUPD	0x40(%RDI,%RCX,1),%ZMM2

  (274) 0x43bd19 VMOVUPD	0x40(%R14,%RCX,1),%ZMM17

  (274) 0x43bd21 VADDPD	0x40(%RBX,%RCX,1),%ZMM2,%ZMM11

  (274) 0x43bd29 VADDPD	0x40(%R8,%RCX,1),%ZMM17,%ZMM18

  (274) 0x43bd31 VMULPD	0x40(%R10,%RCX,1),%ZMM1,%ZMM19

  (274) 0x43bd39 VADDPD	%ZMM11,%ZMM18,%ZMM12

  (274) 0x43bd3f VMULPD	%ZMM19,%ZMM12,%ZMM0

  (274) 0x43bd45 VMOVUPD	%ZMM0,0x40(%RSI,%RCX,1)

  (274) 0x43bd4d VMOVUPD	0x40(%RDX,%RCX,1),%ZMM20

  (274) 0x43bd55 VMOVUPD	0x40(%RAX,%RCX,1),%ZMM9

  (274) 0x43bd5d VADDPD	0x40(%R11,%RCX,1),%ZMM20,%ZMM21

  (274) 0x43bd65 VADDPD	0x40(%R15,%RCX,1),%ZMM9,%ZMM10

  (274) 0x43bd6d VMULPD	0x40(%R13,%RCX,1),%ZMM1,%ZMM30

  (274) 0x43bd75 VADDPD	%ZMM10,%ZMM21,%ZMM3

  (274) 0x43bd7b VMULPD	%ZMM30,%ZMM3,%ZMM2

  (274) 0x43bd81 VMOVUPD	%ZMM2,0x40(%R12,%RCX,1)

  (274) 0x43bd89 SUB	$-0x80,%RCX

  (274) 0x43bd8d CMP	%R9,%RCX

  (274) 0x43bd90 JNE	43bc9f

(273) 0x43bd96 MOV	0x8(%RSP),%R10D

(273) 0x43bd9b MOV	(%RSP),%R14

(273) 0x43bd9f MOV	0x7c(%RSP),%EBX

(273) 0x43bda3 MOV	0x78(%RSP),%EDI

(273) 0x43bda7 MOV	%EBX,%R8D

(273) 0x43bdaa AND	$-0x8,%R8D

(273) 0x43bdae LEA	(%R8,%RDI,1),%ESI

(273) 0x43bdb2 ADD	%R8D,%R10D

(273) 0x43bdb5 TEST	$0x7,%BL

(273) 0x43bdb8 JE	43c1b7

(273) 0x43bdbe MOV	0x7c(%RSP),%EDX

(273) 0x43bdc2 SUB	%R8D,%EDX

(273) 0x43bdc5 LEA	-0x1(%RDX),%R13D

(273) 0x43bdc9 CMP	$0x2,%R13D

(273) 0x43bdcd JBE	43beef

(273) 0x43bdd3 MOVSXD	0x78(%RSP),%R11

(273) 0x43bdd8 MOV	0x48(%RSP),%R9

(273) 0x43bddd MOV	0x28(%RSP),%RAX

(273) 0x43bde2 MOV	0x50(%RSP),%RBX

(273) 0x43bde7 VMOVQ	%XMM6,%RDI

(273) 0x43bdec MOV	0x30(%RSP),%R15

(273) 0x43bdf1 LEA	(%R9,%R11,1),%R13

(273) 0x43bdf5 MOV	0x18(%RSP),%R9

(273) 0x43bdfa LEA	(%RAX,%R11,1),%R12

(273) 0x43bdfe LEA	(%RBX,%R11,1),%RAX

(273) 0x43be02 MOV	0x70(%RSP),%RBX

(273) 0x43be07 ADD	%R8,%R13

(273) 0x43be0a ADD	%R8,%RAX

(273) 0x43be0d LEA	(%R15,%R11,1),%RCX

(273) 0x43be11 VMOVUPD	(%RDI,%RAX,8),%YMM11

(273) 0x43be16 VADDPD	(%RDI,%R13,8),%YMM11,%YMM12

(273) 0x43be1c VMOVQ	%XMM5,%RDI

(273) 0x43be21 ADD	%R8,%RCX

(273) 0x43be24 SAL	$0x3,%RCX

(273) 0x43be28 VMOVQ	%XMM15,%R15

(273) 0x43be2d LEA	(%R9,%R11,1),%R13

(273) 0x43be31 MOV	0x40(%RSP),%R9

(273) 0x43be36 ADD	%R8,%R12

(273) 0x43be39 LEA	(%RBX,%R11,1),%RAX

(273) 0x43be3d ADD	%R8,%R13

(273) 0x43be40 VMOVQ	%XMM16,%RBX

(273) 0x43be46 ADD	%R8,%RAX

(273) 0x43be49 VMOVUPD	(%RDI,%RAX,8),%YMM0

(273) 0x43be4e VADDPD	(%RDI,%R13,8),%YMM0,%YMM9

(273) 0x43be54 MOV	0x20(%RSP),%RAX

(273) 0x43be59 LEA	(%R9,%R11,1),%R13

(273) 0x43be5d VMOVQ	%XMM7,%R9

(273) 0x43be62 ADD	%R8,%R13

(273) 0x43be65 VMULPD	(%RBX,%R13,8),%YMM29,%YMM3

(273) 0x43be6c VMOVQ	%XMM4,%R13

(273) 0x43be71 VMOVQ	%XMM14,%RBX

(273) 0x43be76 LEA	(%RAX,%R11,1),%RDI

(273) 0x43be7a MOV	0x58(%RSP),%RAX

(273) 0x43be7f ADD	%R8,%RDI

(273) 0x43be82 VADDPD	%YMM9,%YMM12,%YMM10

(273) 0x43be87 VMULPD	%YMM3,%YMM10,%YMM2

(273) 0x43be8b VMOVUPD	%YMM2,(%R15,%RDI,8)

(273) 0x43be91 VMOVUPD	0x8(%R9,%RCX,1),%YMM11

(273) 0x43be98 VMOVUPD	(%R9,%RCX,1),%YMM0

(273) 0x43be9e VADDPD	0x8(%R13,%R12,8),%YMM11,%YMM12

(273) 0x43bea5 VADDPD	(%R13,%R12,8),%YMM0,%YMM9

(273) 0x43beac MOV	0x38(%RSP),%R12

(273) 0x43beb1 LEA	(%R12,%R11,1),%RCX

(273) 0x43beb5 ADD	%RAX,%R11

(273) 0x43beb8 ADD	%R8,%RCX

(273) 0x43bebb ADD	%R8,%R11

(273) 0x43bebe VMOVQ	%XMM13,%R8

(273) 0x43bec3 VMULPD	(%RBX,%RCX,8),%YMM29,%YMM3

(273) 0x43beca VADDPD	%YMM9,%YMM12,%YMM10

(273) 0x43becf VMULPD	%YMM3,%YMM10,%YMM2

(273) 0x43bed3 VMOVUPD	%YMM2,(%R8,%R11,8)

(273) 0x43bed9 MOV	%EDX,%R11D

(273) 0x43bedc AND	$-0x4,%R11D

(273) 0x43bee0 ADD	%R11D,%ESI

(273) 0x43bee3 ADD	%R11D,%R10D

(273) 0x43bee6 AND	$0x3,%EDX

(273) 0x43bee9 JE	43c1b7

(273) 0x43beef MOV	0x70(%RSP),%R9

(273) 0x43bef4 MOV	0x18(%RSP),%R11

(273) 0x43bef9 MOVSXD	%ESI,%RAX

(273) 0x43befc VMOVQ	%XMM5,%R12

(273) 0x43bf01 MOV	0x50(%RSP),%RCX

(273) 0x43bf06 MOV	0x48(%RSP),%R8

(273) 0x43bf0b MOV	0x20(%RSP),%RDI

(273) 0x43bf10 LEA	(%R9,%RAX,1),%R13

(273) 0x43bf14 LEA	(%R11,%RAX,1),%R15

(273) 0x43bf18 VMOVQ	%XMM6,%R9

(273) 0x43bf1d VMOVSD	(%R12,%R15,8),%XMM11

(273) 0x43bf23 VADDSD	(%R12,%R13,8),%XMM11,%XMM12

(273) 0x43bf29 MOV	0x40(%RSP),%R12

(273) 0x43bf2e LEA	(%RCX,%RAX,1),%RBX

(273) 0x43bf32 VMOVSD	(%R9,%RBX,8),%XMM0

(273) 0x43bf38 LEA	(%R8,%RAX,1),%R15

(273) 0x43bf3c LEA	(%RDI,%RAX,1),%RDX

(273) 0x43bf40 VMOVQ	%XMM16,%RBX

(273) 0x43bf46 VMOVQ	%XMM15,%R8

(273) 0x43bf4b VADDSD	(%R9,%R15,8),%XMM0,%XMM9

(273) 0x43bf51 VADDSD	%XMM9,%XMM12,%XMM10

(273) 0x43bf56 VMOVQ	%XMM4,%R9

(273) 0x43bf5b LEA	(%R12,%RAX,1),%RCX

(273) 0x43bf5f VMOVQ	%XMM7,%R12

(273) 0x43bf64 VMULSD	(%RBX,%RCX,8),%XMM22,%XMM3

(273) 0x43bf6b VMULSD	%XMM3,%XMM10,%XMM2

(273) 0x43bf6f VMOVSD	%XMM2,(%R8,%RDX,8)

(273) 0x43bf75 MOV	0x30(%RSP),%R8

(273) 0x43bf7a MOV	0x28(%RSP),%RBX

(273) 0x43bf7f LEA	0x1(%RSI),%EDX

(273) 0x43bf82 MOVSXD	%EDX,%RDX

(273) 0x43bf85 LEA	(%R8,%RDX,1),%R13

(273) 0x43bf89 LEA	(%R12,%R13,8),%RCX

(273) 0x43bf8d LEA	(%RDX,%RBX,1),%R15

(273) 0x43bf91 LEA	(%R8,%RAX,1),%R13

(273) 0x43bf95 MOV	0x58(%RSP),%R12

(273) 0x43bf9a VMOVQ	%R13,%XMM11

(273) 0x43bf9f LEA	(%R9,%R15,8),%R9

(273) 0x43bfa3 VMOVQ	%XMM4,%R13

(273) 0x43bfa8 LEA	(%RBX,%RAX,1),%R15

(273) 0x43bfac VMOVSD	(%R13,%R15,8),%XMM12

(273) 0x43bfb3 VMOVQ	%XMM11,%R15

(273) 0x43bfb8 VMOVQ	%XMM7,%R13

(273) 0x43bfbd VMOVSD	(%RCX),%XMM9

(273) 0x43bfc1 VADDSD	(%R13,%R15,8),%XMM12,%XMM0

(273) 0x43bfc8 MOV	0x38(%RSP),%R13

(273) 0x43bfcd VMOVQ	%XMM14,%R15

(273) 0x43bfd2 VADDSD	(%R9),%XMM9,%XMM10

(273) 0x43bfd7 VADDSD	%XMM10,%XMM0,%XMM3

(273) 0x43bfdc ADD	%RAX,%R12

(273) 0x43bfdf ADD	%R13,%RAX

(273) 0x43bfe2 MOV	0x64(%RSP),%R13D

(273) 0x43bfe7 VMULSD	(%R15,%RAX,8),%XMM22,%XMM2

(273) 0x43bfee VMOVQ	%XMM13,%RAX

(273) 0x43bff3 VMULSD	%XMM2,%XMM3,%XMM11

(273) 0x43bff7 VMOVSD	%XMM11,(%RAX,%R12,8)

(273) 0x43bffd LEA	0x1(%R10),%R12D

(273) 0x43c001 CMP	%R13D,%R12D

(273) 0x43c004 JAE	43c1b7

(273) 0x43c00a MOV	0x50(%RSP),%R15

(273) 0x43c00f MOV	0x48(%RSP),%R12

(273) 0x43c014 LEA	(%RDX,%RDI,1),%RAX

(273) 0x43c018 ADD	$0x2,%R10D

(273) 0x43c01c LEA	(%RDX,%R15,1),%R13

(273) 0x43c020 LEA	(%RDX,%R12,1),%R12

(273) 0x43c024 VMOVQ	%XMM6,%R15

(273) 0x43c029 VMOVSD	(%R15,%R13,8),%XMM12

(273) 0x43c02f VADDSD	(%R15,%R12,8),%XMM12,%XMM0

(273) 0x43c035 MOV	0x70(%RSP),%R12

(273) 0x43c03a VMOVQ	%XMM5,%R15

(273) 0x43c03f LEA	(%RDX,%R12,1),%R13

(273) 0x43c043 LEA	(%RDX,%R11,1),%R12

(273) 0x43c047 VMOVSD	(%R15,%R13,8),%XMM9

(273) 0x43c04d VADDSD	(%R15,%R12,8),%XMM9,%XMM10

(273) 0x43c053 MOV	0x40(%RSP),%R12

(273) 0x43c058 VMOVQ	%XMM16,%R13

(273) 0x43c05e VADDSD	%XMM10,%XMM0,%XMM3

(273) 0x43c063 LEA	(%RDX,%R12,1),%R15

(273) 0x43c067 VMOVQ	%XMM15,%R12

(273) 0x43c06c VMULSD	(%R13,%R15,8),%XMM22,%XMM2

(273) 0x43c074 VMULSD	%XMM2,%XMM3,%XMM11

(273) 0x43c078 VMOVSD	%XMM11,(%R12,%RAX,8)

(273) 0x43c07e LEA	0x2(%RSI),%EAX

(273) 0x43c081 CLTQ

(273) 0x43c083 VMOVQ	%XMM4,%R13

(273) 0x43c088 LEA	(%RBX,%RAX,1),%R15

(273) 0x43c08c LEA	(%R8,%RAX,1),%R12

(273) 0x43c090 LEA	(%R13,%R15,8),%R13

(273) 0x43c095 VMOVQ	%XMM7,%R15

(273) 0x43c09a LEA	(%R15,%R12,8),%R12

(273) 0x43c09e VMOVSD	(%R13),%XMM12

(273) 0x43c0a4 MOV	0x58(%RSP),%R15

(273) 0x43c0a9 VADDSD	(%R9),%XMM12,%XMM0

(273) 0x43c0ae MOV	0x38(%RSP),%R9

(273) 0x43c0b3 VMOVSD	(%R12),%XMM9

(273) 0x43c0b9 VADDSD	(%RCX),%XMM9,%XMM10

(273) 0x43c0bd VMOVQ	%XMM14,%RCX

(273) 0x43c0c2 VADDSD	%XMM10,%XMM0,%XMM2

(273) 0x43c0c7 ADD	%RDX,%R15

(273) 0x43c0ca ADD	%R9,%RDX

(273) 0x43c0cd VMULSD	(%RCX,%RDX,8),%XMM22,%XMM3

(273) 0x43c0d4 VMOVQ	%XMM13,%RDX

(273) 0x43c0d9 VMULSD	%XMM3,%XMM2,%XMM11

(273) 0x43c0dd VMOVSD	%XMM11,(%RDX,%R15,8)

(273) 0x43c0e3 MOV	0x64(%RSP),%R15D

(273) 0x43c0e8 CMP	%R15D,%R10D

(273) 0x43c0eb JAE	43c1b7

(273) 0x43c0f1 ADD	%RAX,%RDI

(273) 0x43c0f4 MOV	0x50(%RSP),%RCX

(273) 0x43c0f9 VMOVQ	%XMM6,%R10

(273) 0x43c0fe MOV	0x40(%RSP),%R15

(273) 0x43c103 MOV	%RDI,%RDX

(273) 0x43c106 MOV	0x48(%RSP),%RDI

(273) 0x43c10b ADD	%RAX,%R11

(273) 0x43c10e ADD	$0x3,%ESI

(273) 0x43c111 MOVSXD	%ESI,%RSI

(273) 0x43c114 ADD	%RAX,%R9

(273) 0x43c117 ADD	%RSI,%RBX

(273) 0x43c11a ADD	%RSI,%R8

(273) 0x43c11d ADD	%RAX,%RCX

(273) 0x43c120 ADD	%RAX,%R15

(273) 0x43c123 ADD	%RAX,%RDI

(273) 0x43c126 VMOVSD	(%R10,%RDI,8),%XMM12

(273) 0x43c12c VADDSD	(%R10,%RCX,8),%XMM12,%XMM6

(273) 0x43c132 MOV	0x70(%RSP),%RCX

(273) 0x43c137 VMOVQ	%XMM5,%RDI

(273) 0x43c13c VMOVSD	(%RDI,%R11,8),%XMM0

(273) 0x43c142 VMOVQ	%XMM16,%R11

(273) 0x43c148 VMULSD	(%R11,%R15,8),%XMM22,%XMM10

(273) 0x43c14f ADD	%RAX,%RCX

(273) 0x43c152 VADDSD	(%RDI,%RCX,8),%XMM0,%XMM5

(273) 0x43c157 VMOVQ	%XMM15,%RCX

(273) 0x43c15c VADDSD	%XMM5,%XMM6,%XMM9

(273) 0x43c160 VMULSD	%XMM10,%XMM9,%XMM2

(273) 0x43c165 VMOVSD	%XMM2,(%RCX,%RDX,8)

(273) 0x43c16a MOV	0x58(%RSP),%RDX

(273) 0x43c16f MOV	%RBX,%RDI

(273) 0x43c172 VMOVQ	%XMM4,%RBX

(273) 0x43c177 VMOVSD	(%RBX,%RDI,8),%XMM15

(273) 0x43c17c VADDSD	(%R13),%XMM15,%XMM4

(273) 0x43c182 VMOVQ	%XMM7,%R13

(273) 0x43c187 VMOVSD	(%R13,%R8,8),%XMM7

(273) 0x43c18e VADDSD	(%R12),%XMM7,%XMM3

(273) 0x43c194 VMOVQ	%XMM13,%R12

(273) 0x43c199 VADDSD	%XMM3,%XMM4,%XMM11

(273) 0x43c19d ADD	%RAX,%RDX

(273) 0x43c1a0 VMOVQ	%XMM14,%RAX

(273) 0x43c1a5 VMULSD	(%RAX,%R9,8),%XMM22,%XMM14

(273) 0x43c1ac VMULSD	%XMM14,%XMM11,%XMM12

(273) 0x43c1b1 VMOVSD	%XMM12,(%R12,%RDX,8)

(273) 0x43c1b7 MOV	0x64(%RSP),%R10D

(273) 0x43c1bc INC	%R14

(273) 0x43c1bf CMP	%R14D,0x14(%RSP)

(273) 0x43c1c4 JLE	43c1e0

(273) 0x43c1c6 MOV	0xc(%RSP),%R15D

(273) 0x43c1cb MOV	0x10(%RSP),%ECX

(273) 0x43c1cf MOV	0x60(%RSP),%R11D

(273) 0x43c1d4 SUB	%R10D,%R15D

(273) 0x43c1d7 MOV	%ECX,0x78(%RSP)

(273) 0x43c1db JMP	43ba30

0x43c1e0 VZEROUPPER

0x43c1e3 LEA	-0x28(%RBP),%RSP

0x43c1e7 POP	%RBX

0x43c1e8 POP	%R12

0x43c1ea POP	%R13

0x43c1ec POP	%R14

0x43c1ee POP	%R15

0x43c1f0 POP	%RBP

0x43c1f1 RET

0x43c1f2 NOPW	%CS:(%RAX,%RAX,1)

0x43c1fd NOPL	(%RAX)

(273) 0x43c200 MOV	0x78(%RSP),%ESI

(273) 0x43c204 XOR	%R8D,%R8D

(273) 0x43c207 JMP	43bdbe

0x43c20c INC	%R9D

0x43c20f XOR	%EDX,%EDX

0x43c211 JMP	43b993

0x43c216 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.59+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.27+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	flux_calc(global_variables&)	flux_calc.cpp:57	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36-40
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.50 cycles (4.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.79 cycles (15.21x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.88 cycles (1.10x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.63 cycles (1.13x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:39

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 108 bytes (13 double precision FP elements). The binary function is storing 20 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	87
nb uops	87
loop length	340
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	1
used zmm registers	1
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.88 cycles
front end	10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.83	5.83	5.83	5.83	5.83	5.83	6.00	6.00	6.00	6.00	0.50	1.50	1.00	0.00	0.00	0.00
cycles	5.83	5.83	5.83	5.83	5.83	5.83	6.00	6.00	6.00	6.00	0.50	1.50	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.88
Dispatch	6.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	10%
store	6%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (9.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43b910

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x50(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x54(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (6.3%)
MOV 0x48(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x4c(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
ADD $0x3,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
INC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ECX,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV %EDX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CMP %ECX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43c1e3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RDI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R12D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43c1e3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 43c20c <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8fc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R9,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CMP %R11D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 43c1e3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (6.3%)
VMOVQ 0x8(%RBX),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
DIVL 0x60(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	10-17	6	scal (6.3%)
VMOVQ 0x18(%RBX),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x28(%RBX),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x28cc7(%RIP),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x38(%RBX),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMULSD (%RBX),%XMM22,%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	3	0.50	scal (12.5%)
VMOVQ 0x10(%RBX),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ 0x20(%RBX),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
VBROADCASTSD %XMM22,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM22,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R9D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ %RBX,%XMM8	1	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ECX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV %EDI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43b993 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	flux_calc.cpp:36-40
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:36-40
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.50 cycles (4.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.63 cycles (1.13x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:38
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/flux_calc.cpp:39

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 108 bytes (13 double precision FP elements). The binary function is storing 20 bytes (2 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	87
nb uops	87
loop length	340
used x86 registers	16
used mmx registers	0
used xmm registers	9
used ymm registers	1
used zmm registers	1
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.88 cycles
front end	10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.83	5.83	5.83	5.83	5.83	5.83	6.00	6.00	6.00	6.00	0.50	1.50	1.00	0.00	0.00	0.00
cycles	5.83	5.83	5.83	5.83	5.83	5.83	6.00	6.00	6.00	6.00	0.50	1.50	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.88
Dispatch	6.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	2%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	10%
store	6%
mul	12%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (9.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 43b910

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x50(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x54(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (6.3%)
MOV 0x48(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
MOV 0x4c(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
ADD $0x3,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
INC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ECX,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV %EDX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CMP %ECX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43c1e3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RDI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R12D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43c1e3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x60(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
IMUL %R14D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 43c20c <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8fc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%R9,%R10,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R11D,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
CMP %R11D,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 43c1e3 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x8d3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x10(%RSP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	scal (6.3%)
VMOVQ 0x8(%RBX),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
DIVL 0x60(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	10-17	6	scal (6.3%)
VMOVQ 0x18(%RBX),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x28(%RBX),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x28cc7(%RIP),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x38(%RBX),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMULSD (%RBX),%XMM22,%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	3	0.50	scal (12.5%)
VMOVQ 0x10(%RBX),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ 0x20(%RBX),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x30(%RBX),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	0.50	scal (12.5%)
MOV 0x40(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	N/A
VBROADCASTSD %XMM22,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM22,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %R9D,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ %RBX,%XMM8	1	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUB %ECX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.50	scal (6.3%)
MOV %EDI,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43b993 <_Z16flux_calc_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_._omp_fn.0+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼flux_calc_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	4.33	1.59
▼Loop 273 - flux_calc.cpp:38-40 - exec–	0.00	0.01
○Loop 274 - flux_calc.cpp:39-40 - exec	4.32	1.58

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Cycles and memory resources usage

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