OV - exec - Function calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, double&, int&, double&, double&, int&, int&, int&) [clone ._omp

	Function: calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2 ...	Module: exec	Source: calc_dt.cpp:49-75 [...]	Coverage (incl. loops): 3.26% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp: 49 - 75

--------------------------------------------------------------------------------

49: #pragma omp parallel for simd collapse(2) reduction(min : dt_min_val0)

50:   for (int j = (y_min + 1); j < (y_max + 2); j++) {

51:     for (int i = (x_min + 1); i < (x_max + 2); i++) {

52:       double dsx = celldx[i];

53:       double dsy = celldy[j];

54:       double cc = soundspeed(i, j) * soundspeed(i, j);

55:       cc = cc + 2.0 * viscosity_a(i, j) / density0(i, j);

56:       cc = std::fmax(std::sqrt(cc), g_small);

57:       double dtct = dtc_safe * std::fmin(dsx, dsy) / cc;

58:       double div = 0.0;

59:       double dv1 = (xvel0(i, j) + xvel0(i + 0, j + 1)) * xarea(i, j);

60:       double dv2 = (xvel0(i + 1, j + 0) + xvel0(i + 1, j + 1)) * xarea(i + 1, j + 0);

61:       div = div + dv2 - dv1;

62:       double dtut = dtu_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

63:       dv1 = (yvel0(i, j) + yvel0(i + 1, j + 0)) * yarea(i, j);

64:       dv2 = (yvel0(i + 0, j + 1) + yvel0(i + 1, j + 1)) * yarea(i + 0, j + 1);

65:       div = div + dv2 - dv1;

66:       double dtvt = dtv_safe * 2.0 * volume(i, j) / std::fmax(std::fmax(std::fabs(dv1), std::fabs(dv2)), g_small * volume(i, j));

67:       div = div / (2.0 * volume(i, j));

68:       double dtdivt;

69:       if (div < -g_small) {

70:         dtdivt = dtdiv_safe * (-1.0 / div);

71:       } else {

72:         dtdivt = g_big;

73:       }

74:       double mins = std::fmin(dtct, std::fmin(dtut, std::fmin(dtvt, std::fmin(dtdivt, g_big))));

75:       dt_min_val0 = std::fmin(mins, dt_min_val0);

0x4384c0 PUSH	%RBP

0x4384c1 MOV	%RSP,%RBP

0x4384c4 PUSH	%R15

0x4384c6 PUSH	%R14

0x4384c8 PUSH	%R13

0x4384ca PUSH	%R12

0x4384cc PUSH	%RBX

0x4384cd MOV	%RDI,%R14

0x4384d0 AND	$-0x40,%RSP

0x4384d4 SUB	$0x6c0,%RSP

0x4384db MOV	0x80(%RDI),%EAX

0x4384e1 MOV	0x84(%RDI),%ECX

0x4384e7 MOV	0x78(%RDI),%EDX

0x4384ea MOV	0x7c(%RDI),%EBX

0x4384ed ADD	$0x2,%ECX

0x4384f0 INC	%EDX

0x4384f2 LEA	0x1(%RAX),%R15D

0x4384f6 MOV	%ECX,0x70(%RSP)

0x4384fa MOV	%EDX,0x24(%RSP)

0x4384fe CMP	%ECX,%R15D

0x438501 JGE	43954e

0x438507 MOV	0x24(%RSP),%ESI

0x43850b MOV	%ECX,%R12D

0x43850e LEA	0x2(%RBX),%R13D

0x438512 SUB	%R15D,%R12D

0x438515 CMP	%R13D,%ESI

0x438518 JGE	43954e

0x43851e MOV	%R13D,%EDI

0x438521 SUB	%ESI,%EDI

0x438523 MOV	%EDI,0x20(%RSP)

0x438527 CALL	404630 <omp_get_num_threads@plt>

0x43852c MOV	%EAX,%EBX

0x43852e CALL	404520 <omp_get_thread_num@plt>

0x438533 XOR	%EDX,%EDX

0x438535 MOV	%EAX,%R8D

0x438538 MOV	0x20(%RSP),%EAX

0x43853c IMUL	%R12D,%EAX

0x438540 DIV	%EBX

0x438542 MOV	%EAX,%ECX

0x438544 CMP	%EDX,%R8D

0x438547 JB	439545

0x43854d IMUL	%ECX,%R8D

0x438551 VMOVSD	0x2c267(%RIP),%XMM1

0x438559 LEA	(%R8,%RDX,1),%R9D

0x43855d LEA	(%RCX,%R9,1),%R10D

0x438561 MOV	%R10D,0x1c(%RSP)

0x438566 CMP	%R10D,%R9D

0x438569 JAE	4394c6

0x43856f MOV	%R9D,%EAX

0x438572 XOR	%EDX,%EDX

0x438574 MOV	0x24(%RSP),%R11D

0x438579 VMOVQ	0x48(%R14),%XMM25

0x438580 DIVL	0x20(%RSP)

0x438584 VMOVSD	0x10(%R14),%XMM3

0x43858a VMOVSD	0x8(%R14),%XMM2

0x438590 VMOVSD	(%R14),%XMM0

0x438595 VMOVSD	%XMM1,0x10(%RSP)

0x43859b VMOVSD	%XMM1,0x640(%RSP)

0x4385a4 VMOVSD	%XMM1,0x648(%RSP)

0x4385ad VMOVSD	%XMM1,0x650(%RSP)

0x4385b6 VMOVSD	%XMM1,0x658(%RSP)

0x4385bf VMOVSD	%XMM1,0x660(%RSP)

0x4385c8 VMOVSD	%XMM1,0x668(%RSP)

0x4385d1 VMOVSD	%XMM1,0x670(%RSP)

0x4385da VMOVSD	%XMM1,0x678(%RSP)

0x4385e3 VMOVSD	%XMM1,0x680(%RSP)

0x4385ec VMOVSD	%XMM1,0x688(%RSP)

0x4385f5 VMOVSD	%XMM1,0x690(%RSP)

0x4385fe VMOVSD	%XMM1,0x698(%RSP)

0x438607 VMOVSD	%XMM1,0x6a0(%RSP)

0x438610 VMOVSD	%XMM1,0x6a8(%RSP)

0x438619 VMOVSD	%XMM1,0x6b0(%RSP)

0x438622 VMOVSD	%XMM1,0x6b8(%RSP)

0x43862b VMOVQ	0x30(%R14),%XMM6

0x438631 VMOVQ	0x58(%R14),%XMM8

0x438637 VMOVSD	0x18(%R14),%XMM4

0x43863d VMOVQ	0x50(%R14),%XMM9

0x438643 VMOVQ	0x60(%R14),%XMM10

0x438649 MOV	$0x10,%R12D

0x43864f MOV	$0x1,%EDI

0x438654 VMOVAPD	%XMM0,%XMM1

0x438658 VADDSD	%XMM2,%XMM2,%XMM2

0x43865c VADDSD	%XMM3,%XMM3,%XMM3

0x438660 VPBROADCASTD	%R12D,%ZMM7

0x438666 VPBROADCASTD	%EDI,%ZMM12

0x43866c ADD	%R11D,%EDX

0x43866f MOV	%R13D,%R11D

0x438672 MOV	0x38(%R14),%R13

0x438676 ADD	%R15D,%EAX

0x438679 MOV	%EDX,0x74(%RSP)

0x43867d SUB	%EDX,%R11D

0x438680 MOVSXD	%EAX,%RDX

0x438683 LEA	0x1(%RDX),%R15

0x438687 MOV	%R13,0x60(%RSP)

0x43868c VMOVQ	0x20(%R14),%XMM26

0x438693 VMOVQ	0x28(%R14),%XMM5

0x438699 VMOVDQA32	%ZMM7,0xc0(%RSP)

0x4386a1 VMOVQ	0x40(%R14),%XMM31

0x4386a8 VMOVQ	0x68(%R14),%XMM11

0x4386ae MOV	%R15,0x68(%RSP)

0x4386b3 MOV	%R15,0x78(%RSP)

0x4386b8 VMOVQ	0x2b56e(%RIP),%XMM28

0x4386c2 MOV	%R14,0x8(%RSP)

0x4386c7 VMOVDQA32	%ZMM12,0x80(%RSP)

0x4386cf VMOVDQA64	%XMM5,%XMM16

0x4386d5 VMOVDQA64	%XMM25,%XMM5

0x4386db NOPL	(%RAX,%RAX,1)

(251) 0x4386e0 CMP	%R11D,%ECX

(251) 0x4386e3 MOV	%R11D,%EAX

(251) 0x4386e6 CMOVBE	%ECX,%EAX

(251) 0x4386e9 LEA	(%R9,%RAX,1),%R10D

(251) 0x4386ed CMP	%R10D,%R9D

(251) 0x4386f0 JAE	43950c

(251) 0x4386f6 LEA	-0x1(%RAX),%R14D

(251) 0x4386fa LEA	(,%RDX,8),%RCX

(251) 0x438702 CMP	$0xe,%R14D

(251) 0x438706 JBE	43917a

(251) 0x43870c VMOVQ	%XMM8,%R11

(251) 0x438711 MOV	0x60(%RSP),%R8

(251) 0x438716 VMOVQ	%XMM5,%RDI

(251) 0x43871b VPBROADCASTD	0x74(%RSP),%ZMM13

(251) 0x438723 MOV	(%R11),%R13

(251) 0x438726 VMOVQ	%XMM6,%RBX

(251) 0x43872b VBROADCASTSD	%XMM2,%ZMM15

(251) 0x438731 VPADDD	0x2c0c5(%RIP),%ZMM13,%ZMM0

(251) 0x43873b MOV	(%RDI),%R14

(251) 0x43873e VPBROADCASTQ	0x8(%RBX),%ZMM13

(251) 0x438745 VMOVAPD	%ZMM15,0x200(%RSP)

(251) 0x43874d VMOVQ	%XMM10,%RBX

(251) 0x438752 VPBROADCASTQ	0x10(%R11),%ZMM15

(251) 0x438759 VBROADCASTSD	%XMM3,%ZMM7

(251) 0x43875f MOV	(%RBX),%R11

(251) 0x438762 VBROADCASTSD	%XMM1,%ZMM14

(251) 0x438768 VMOVAPD	%ZMM7,0x140(%RSP)

(251) 0x438770 VMOVQ	%XMM9,%R15

(251) 0x438775 VBROADCASTSD	%XMM4,%ZMM12

(251) 0x43877b MOV	%EAX,%ESI

(251) 0x43877d VMOVAPD	%ZMM14,0x2c0(%RSP)

(251) 0x438785 VPBROADCASTQ	0x8(%R8),%ZMM14

(251) 0x43878c MOV	(%R15),%R12

(251) 0x43878f KXNORB	%K1,%K1,%K1

(251) 0x438793 IMUL	%RDX,%R13

(251) 0x438797 VMOVAPD	%ZMM12,0x100(%RSP)

(251) 0x43879f VPBROADCASTQ	0x10(%R15),%ZMM12

(251) 0x4387a6 VMOVQ	%XMM26,%R15

(251) 0x4387ac IMUL	%RDX,%R14

(251) 0x4387b0 MOV	%R11,%R8

(251) 0x4387b3 VPBROADCASTQ	%R13,%ZMM7

(251) 0x4387b9 MOV	0x78(%RSP),%R13

(251) 0x4387be IMUL	%RDX,%R8

(251) 0x4387c2 IMUL	%RDX,%R12

(251) 0x4387c6 VMOVDQA64	%ZMM13,0x4c0(%RSP)

(251) 0x4387ce VMOVDQA64	%ZMM15,0x440(%RSP)

(251) 0x4387d6 VPBROADCASTQ	%R14,%ZMM15

(251) 0x4387dc VMOVQ	%XMM31,%R14

(251) 0x4387e2 VPBROADCASTQ	%R8,%ZMM30

(251) 0x4387e8 VMOVDQA64	%ZMM14,0x480(%RSP)

(251) 0x4387f0 VPBROADCASTQ	0x10(%RDI),%ZMM14

(251) 0x4387f7 MOV	(%R15),%RDI

(251) 0x4387fa VPBROADCASTQ	%R12,%ZMM13

(251) 0x438800 IMUL	%R13,%R11

(251) 0x438804 VMOVDQA64	%ZMM12,0x3c0(%RSP)

(251) 0x43880c VPBROADCASTQ	0x10(%R14),%ZMM12

(251) 0x438813 VMOVDQA64	%ZMM13,0x380(%RSP)

(251) 0x43881b VMOVQ	%XMM11,%R8

(251) 0x438820 VMOVDQA64	%ZMM7,0x400(%RSP)

(251) 0x438828 VPBROADCASTQ	0x10(%R15),%ZMM7

(251) 0x43882f VPBROADCASTQ	%R11,%ZMM29

(251) 0x438835 MOV	(%R14),%R11

(251) 0x438838 IMUL	%RDX,%RDI

(251) 0x43883c VMOVDQA64	%ZMM15,0x300(%RSP)

(251) 0x438844 VPBROADCASTQ	0x10(%RBX),%ZMM15

(251) 0x43884b SHR	$0x4,%ESI

(251) 0x43884e VMOVDQA64	%ZMM14,0x340(%RSP)

(251) 0x438856 VPBROADCASTQ	%RDI,%ZMM14

(251) 0x43885c IMUL	%RDX,%R11

(251) 0x438860 VMOVQ	%XMM16,%RDI

(251) 0x438866 VMOVDQA64	%ZMM12,0x280(%RSP)

(251) 0x43886e VPBROADCASTQ	%R11,%ZMM13

(251) 0x438874 VMOVQ	%XMM8,%R11

(251) 0x438879 VMOVDQA64	%ZMM30,%ZMM8

(251) 0x43887f VMOVDQA64	%ZMM13,0x240(%RSP)

(251) 0x438887 VPBROADCASTQ	0x10(%R8),%ZMM13

(251) 0x43888e MOV	(%RDI),%R14

(251) 0x438891 MOV	(%R8),%R15

(251) 0x438894 VBROADCASTSD	0x2acea(%RIP),%ZMM24

(251) 0x43889e VBROADCASTSD	0x2b3e0(%RIP),%ZMM23

(251) 0x4388a8 VMOVQ	%XMM5,%R8

(251) 0x4388ad VPBROADCASTQ	0x10(%RDI),%ZMM25

(251) 0x4388b4 XOR	%EDI,%EDI

(251) 0x4388b6 VMOVSD	%XMM3,0x58(%RSP)

(251) 0x4388bc VMOVSD	%XMM4,0x50(%RSP)

(251) 0x4388c2 VMOVSD	%XMM1,0x48(%RSP)

(251) 0x4388c8 VMOVQ	%XMM31,0x40(%RSP)

(251) 0x4388d0 VMOVQ	%XMM11,0x38(%RSP)

(251) 0x4388d6 VMOVSD	%XMM2,0x28(%RSP)

(251) 0x4388dc VMOVQ	%XMM16,0x30(%RSP)

(251) 0x4388e4 MOV	%R14,%RBX

(251) 0x4388e7 IMUL	%R13,%R14

(251) 0x4388eb MOV	%R15,%R12

(251) 0x4388ee IMUL	%RDX,%RBX

(251) 0x4388f2 IMUL	%R13,%R15

(251) 0x4388f6 VMOVQ	%XMM10,%R13

(251) 0x4388fb IMUL	%RDX,%R12

(251) 0x4388ff VPBROADCASTQ	%RBX,%ZMM12

(251) 0x438905 VPBROADCASTQ	%R15,%ZMM21

(251) 0x43890b VMOVQ	%XMM9,%R15

(251) 0x438910 VMOVDQA64	%ZMM12,0x1c0(%RSP)

(251) 0x438918 VPBROADCASTQ	%R14,%ZMM12

(251) 0x43891e VPBROADCASTQ	%R12,%ZMM22

(251) 0x438924 VMOVDQA64	%ZMM21,%ZMM5

(251) 0x43892a VMOVDQA64	%ZMM12,0x180(%RSP)

(251) 0x438932 VBROADCASTSD	0x2b2f4(%RIP),%ZMM12

(251) 0x43893c VMOVDQA64	%ZMM14,%ZMM21

(251) 0x438942 VMOVQ	%XMM6,%R14

(251) 0x438947 VMOVQ	%XMM26,%R12

(251) 0x43894d VMOVDQA32	%ZMM0,%ZMM6

(251) 0x438953 VMOVDQA64	%ZMM29,%ZMM26

(251) 0x438959 VMOVDQA64	%ZMM7,%ZMM14

(251) 0x43895f NOP

  (253) 0x438960 VMOVDQA64	0x4c0(%RSP),%ZMM9

  (253) 0x438968 VMOVDQA32	%ZMM6,%ZMM2

  (253) 0x43896e KMOVB	%K1,%K3

  (253) 0x438972 VPADDD	0xc0(%RSP),%ZMM6,%ZMM6

  (253) 0x43897a INC	%EDI

  (253) 0x43897c VEXTRACTI32X8	$0x1,%ZMM2,%YMM4

  (253) 0x438983 VPMOVSXDQ	%YMM2,%ZMM1

  (253) 0x438989 KMOVB	%K1,%K4

  (253) 0x43898d VPADDD	0x80(%RSP),%ZMM2,%ZMM2

  (253) 0x438995 KMOVB	%K1,%K5

  (253) 0x438999 VPMOVSXDQ	%YMM4,%ZMM0

  (253) 0x43899f VMOVDQA64	0x480(%RSP),%ZMM4

  (253) 0x4389a7 VPSLLQ	$0x3,%ZMM1,%ZMM3

  (253) 0x4389ae KMOVB	%K1,%K6

  (253) 0x4389b2 VPSLLQ	$0x3,%ZMM0,%ZMM11

  (253) 0x4389b9 KMOVB	%K1,%K7

  (253) 0x4389bd KMOVB	%K1,%K2

  (253) 0x4389c1 VPADDQ	%ZMM9,%ZMM3,%ZMM10

  (253) 0x4389c7 VPADDQ	%ZMM9,%ZMM11,%ZMM7

  (253) 0x4389cd VMOVDQA64	0x400(%RSP),%ZMM9

  (253) 0x4389d5 VMOVDQA64	0x440(%RSP),%ZMM11

  (253) 0x4389dd VGATHERQPD	(,%ZMM10,1),%ZMM18{%K3}

  (253) 0x4389e8 VGATHERQPD	(,%ZMM7,1),%ZMM17{%K4}

  (253) 0x4389f3 KMOVB	%K1,%K3

  (253) 0x4389f7 KMOVB	%K1,%K4

  (253) 0x4389fb VGATHERQPD	(%RCX,%ZMM4,1),%ZMM20{%K5}

  (253) 0x438a02 KMOVB	%K1,%K5

  (253) 0x438a06 VMINPD	%ZMM20,%ZMM18,%ZMM18

  (253) 0x438a0c VMINPD	%ZMM20,%ZMM17,%ZMM17

  (253) 0x438a12 VPADDQ	%ZMM9,%ZMM1,%ZMM3

  (253) 0x438a18 VPADDQ	%ZMM9,%ZMM0,%ZMM4

  (253) 0x438a1e VPSLLQ	$0x3,%ZMM3,%ZMM10

  (253) 0x438a25 VPADDQ	%ZMM11,%ZMM10,%ZMM7

  (253) 0x438a2b VMOVDQA64	0x380(%RSP),%ZMM10

  (253) 0x438a33 VPSLLQ	$0x3,%ZMM4,%ZMM9

  (253) 0x438a3a VPADDQ	%ZMM11,%ZMM9,%ZMM3

  (253) 0x438a40 VMOVDQA64	0x3c0(%RSP),%ZMM9

  (253) 0x438a48 VGATHERQPD	(,%ZMM7,1),%ZMM27{%K6}

  (253) 0x438a53 KMOVB	%K1,%K6

  (253) 0x438a57 VGATHERQPD	(,%ZMM3,1),%ZMM4{%K7}

  (253) 0x438a62 KMOVB	%K1,%K7

  (253) 0x438a66 VPADDQ	%ZMM10,%ZMM1,%ZMM11

  (253) 0x438a6c VPADDQ	%ZMM10,%ZMM0,%ZMM19

  (253) 0x438a72 VMOVDQA64	0x300(%RSP),%ZMM10

  (253) 0x438a7a VPSLLQ	$0x3,%ZMM19,%ZMM16

  (253) 0x438a81 VPSLLQ	$0x3,%ZMM11,%ZMM7

  (253) 0x438a88 VPADDQ	%ZMM9,%ZMM16,%ZMM31

  (253) 0x438a8e VPADDQ	%ZMM9,%ZMM7,%ZMM11

  (253) 0x438a94 VMOVDQA64	0x340(%RSP),%ZMM9

  (253) 0x438a9c VGATHERQPD	(,%ZMM11,1),%ZMM3{%K2}

  (253) 0x438aa7 KMOVB	%K1,%K2

  (253) 0x438aab VGATHERQPD	(,%ZMM31,1),%ZMM7{%K3}

  (253) 0x438ab6 VADDPD	%ZMM3,%ZMM3,%ZMM3

  (253) 0x438abc VADDPD	%ZMM7,%ZMM7,%ZMM11

  (253) 0x438ac2 KMOVB	%K1,%K3

  (253) 0x438ac6 VPADDQ	%ZMM10,%ZMM1,%ZMM30

  (253) 0x438acc VPADDQ	%ZMM10,%ZMM0,%ZMM31

  (253) 0x438ad2 VPSLLQ	$0x3,%ZMM30,%ZMM29

  (253) 0x438ad9 VPSLLQ	$0x3,%ZMM31,%ZMM30

  (253) 0x438ae0 VPADDQ	%ZMM9,%ZMM29,%ZMM19

  (253) 0x438ae6 VPADDQ	%ZMM9,%ZMM30,%ZMM29

  (253) 0x438aec VGATHERQPD	(,%ZMM19,1),%ZMM16{%K4}

  (253) 0x438af7 KMOVB	%K1,%K4

  (253) 0x438afb VGATHERQPD	(,%ZMM29,1),%ZMM19{%K5}

  (253) 0x438b06 VDIVPD	%ZMM16,%ZMM3,%ZMM10

  (253) 0x438b0c KMOVB	%K1,%K5

  (253) 0x438b10 VDIVPD	%ZMM19,%ZMM11,%ZMM7

  (253) 0x438b16 VMOVAPD	0x2c0(%RSP),%ZMM11

  (253) 0x438b1e VFMADD231PD	%ZMM27,%ZMM27,%ZMM10

  (253) 0x438b24 VMULPD	%ZMM11,%ZMM18,%ZMM27

  (253) 0x438b2a VMULPD	%ZMM11,%ZMM17,%ZMM20

  (253) 0x438b30 VPMOVSXDQ	%YMM2,%ZMM17

  (253) 0x438b36 VSQRTPD	%ZMM10,%ZMM9

  (253) 0x438b3c VFMADD132PD	%ZMM4,%ZMM7,%ZMM4

  (253) 0x438b42 VMAXPD	%ZMM24,%ZMM9,%ZMM7

  (253) 0x438b48 VDIVPD	%ZMM7,%ZMM27,%ZMM3

  (253) 0x438b4e VSQRTPD	%ZMM4,%ZMM4

  (253) 0x438b54 VMAXPD	%ZMM24,%ZMM4,%ZMM10

  (253) 0x438b5a VPADDQ	%ZMM8,%ZMM1,%ZMM4

  (253) 0x438b60 VPSLLQ	$0x3,%ZMM4,%ZMM11

  (253) 0x438b67 VPADDQ	%ZMM26,%ZMM1,%ZMM4

  (253) 0x438b6d VPADDQ	%ZMM15,%ZMM11,%ZMM7

  (253) 0x438b73 VPSLLQ	$0x3,%ZMM4,%ZMM11

  (253) 0x438b7a VPADDQ	%ZMM21,%ZMM1,%ZMM4

  (253) 0x438b80 VDIVPD	%ZMM10,%ZMM20,%ZMM9

  (253) 0x438b86 VMOVAPD	%ZMM3,0x600(%RSP)

  (253) 0x438b8e VPADDQ	%ZMM8,%ZMM0,%ZMM3

  (253) 0x438b94 VPSLLQ	$0x3,%ZMM3,%ZMM10

  (253) 0x438b9b VPADDQ	%ZMM26,%ZMM0,%ZMM3

  (253) 0x438ba1 VMOVAPD	%ZMM9,0x5c0(%RSP)

  (253) 0x438ba9 VPADDQ	%ZMM15,%ZMM10,%ZMM9

  (253) 0x438baf VPSLLQ	$0x3,%ZMM3,%ZMM10

  (253) 0x438bb6 VGATHERQPD	(,%ZMM9,1),%ZMM31{%K7}

  (253) 0x438bc1 KMOVB	%K1,%K7

  (253) 0x438bc5 VPADDQ	%ZMM15,%ZMM10,%ZMM9

  (253) 0x438bcb VGATHERQPD	(,%ZMM7,1),%ZMM16{%K6}

  (253) 0x438bd6 VPADDQ	%ZMM15,%ZMM11,%ZMM7

  (253) 0x438bdc KMOVB	%K1,%K6

  (253) 0x438be0 VGATHERQPD	(,%ZMM9,1),%ZMM11{%K3}

  (253) 0x438beb VPADDQ	%ZMM21,%ZMM0,%ZMM10

  (253) 0x438bf1 VGATHERQPD	(,%ZMM7,1),%ZMM30{%K2}

  (253) 0x438bfc VADDPD	%ZMM11,%ZMM31,%ZMM18

  (253) 0x438c02 VPSLLQ	$0x3,%ZMM4,%ZMM7

  (253) 0x438c09 VEXTRACTI32X8	$0x1,%ZMM2,%YMM11

  (253) 0x438c10 VPADDQ	%ZMM14,%ZMM7,%ZMM3

  (253) 0x438c16 VPSLLQ	$0x3,%ZMM10,%ZMM9

  (253) 0x438c1d VPMOVSXDQ	%YMM11,%ZMM2

  (253) 0x438c23 VPADDQ	%ZMM14,%ZMM9,%ZMM7

  (253) 0x438c29 VGATHERQPD	(,%ZMM3,1),%ZMM29{%K4}

  (253) 0x438c34 VPADDQ	%ZMM17,%ZMM8,%ZMM3

  (253) 0x438c3a VGATHERQPD	(,%ZMM7,1),%ZMM4{%K5}

  (253) 0x438c45 VADDPD	%ZMM30,%ZMM16,%ZMM19

  (253) 0x438c4b VPSLLQ	$0x3,%ZMM3,%ZMM10

  (253) 0x438c52 VMULPD	%ZMM4,%ZMM18,%ZMM18

  (253) 0x438c58 KMOVB	%K1,%K2

  (253) 0x438c5c VPADDQ	%ZMM15,%ZMM10,%ZMM9

  (253) 0x438c62 KMOVB	%K1,%K3

  (253) 0x438c66 KMOVB	%K1,%K4

  (253) 0x438c6a VGATHERQPD	(,%ZMM9,1),%ZMM4{%K6}

  (253) 0x438c75 VPADDQ	%ZMM2,%ZMM8,%ZMM7

  (253) 0x438c7b VPSLLQ	$0x3,%ZMM7,%ZMM11

  (253) 0x438c82 KMOVB	%K1,%K5

  (253) 0x438c86 VMULPD	%ZMM29,%ZMM19,%ZMM19

  (253) 0x438c8c VPADDQ	%ZMM17,%ZMM26,%ZMM9

  (253) 0x438c92 VPADDQ	%ZMM15,%ZMM11,%ZMM10

  (253) 0x438c98 VPSLLQ	$0x3,%ZMM9,%ZMM7

  (253) 0x438c9f KMOVB	%K1,%K6

  (253) 0x438ca3 VPADDQ	%ZMM15,%ZMM7,%ZMM11

  (253) 0x438ca9 VGATHERQPD	(,%ZMM11,1),%ZMM16{%K2}

  (253) 0x438cb4 KMOVB	%K1,%K2

  (253) 0x438cb8 VGATHERQPD	(,%ZMM10,1),%ZMM3{%K7}

  (253) 0x438cc3 VPADDQ	%ZMM17,%ZMM21,%ZMM11

  (253) 0x438cc9 VPADDQ	%ZMM2,%ZMM26,%ZMM10

  (253) 0x438ccf VADDPD	%ZMM16,%ZMM4,%ZMM4

  (253) 0x438cd5 KMOVB	%K1,%K7

  (253) 0x438cd9 VPSLLQ	$0x3,%ZMM10,%ZMM9

  (253) 0x438ce0 VPSLLQ	$0x3,%ZMM11,%ZMM10

  (253) 0x438ce7 VPADDQ	%ZMM15,%ZMM9,%ZMM7

  (253) 0x438ced VPADDQ	%ZMM14,%ZMM10,%ZMM9

  (253) 0x438cf3 VGATHERQPD	(,%ZMM7,1),%ZMM27{%K3}

  (253) 0x438cfe KMOVB	%K1,%K3

  (253) 0x438d02 VGATHERQPD	(,%ZMM9,1),%ZMM31{%K4}

  (253) 0x438d0d VPADDQ	%ZMM2,%ZMM21,%ZMM7

  (253) 0x438d13 VMOVDQA64	0x240(%RSP),%ZMM9

  (253) 0x438d1b VPSLLQ	$0x3,%ZMM7,%ZMM11

  (253) 0x438d22 VPADDQ	%ZMM14,%ZMM11,%ZMM10

  (253) 0x438d28 VMOVDQA64	0x280(%RSP),%ZMM11

  (253) 0x438d30 VADDPD	%ZMM27,%ZMM3,%ZMM3

  (253) 0x438d36 VGATHERQPD	(,%ZMM10,1),%ZMM20{%K5}

  (253) 0x438d41 VMULPD	%ZMM31,%ZMM4,%ZMM4

  (253) 0x438d47 KMOVB	%K1,%K4

  (253) 0x438d4b VMULPD	%ZMM20,%ZMM3,%ZMM3

  (253) 0x438d51 KMOVB	%K1,%K5

  (253) 0x438d55 VPADDQ	%ZMM9,%ZMM1,%ZMM30

  (253) 0x438d5b VPADDQ	%ZMM9,%ZMM0,%ZMM27

  (253) 0x438d61 VPSLLQ	$0x3,%ZMM30,%ZMM29

  (253) 0x438d68 VPSLLQ	$0x3,%ZMM27,%ZMM31

  (253) 0x438d6f VPADDQ	%ZMM11,%ZMM29,%ZMM16

  (253) 0x438d75 VPADDQ	%ZMM11,%ZMM31,%ZMM20

  (253) 0x438d7b VMOVAPD	0x200(%RSP),%ZMM11

  (253) 0x438d83 VGATHERQPD	(,%ZMM16,1),%ZMM7{%K6}

  (253) 0x438d8e VANDPD	%ZMM12,%ZMM4,%ZMM27

  (253) 0x438d94 VANDPD	%ZMM12,%ZMM19,%ZMM29

  (253) 0x438d9a VMULPD	%ZMM24,%ZMM7,%ZMM10

  (253) 0x438da0 VMAXPD	%ZMM29,%ZMM27,%ZMM31

  (253) 0x438da6 VGATHERQPD	(,%ZMM20,1),%ZMM30{%K7}

  (253) 0x438db1 VMULPD	%ZMM24,%ZMM30,%ZMM9

  (253) 0x438db7 KMOVB	%K1,%K6

  (253) 0x438dbb VANDPD	%ZMM12,%ZMM18,%ZMM29

  (253) 0x438dc1 KMOVB	%K1,%K7

  (253) 0x438dc5 VMAXPD	%ZMM10,%ZMM31,%ZMM20

  (253) 0x438dcb VANDPD	%ZMM12,%ZMM3,%ZMM31

  (253) 0x438dd1 VMULPD	%ZMM11,%ZMM7,%ZMM16

  (253) 0x438dd7 VMULPD	%ZMM11,%ZMM30,%ZMM27

  (253) 0x438ddd VDIVPD	%ZMM20,%ZMM16,%ZMM16

  (253) 0x438de3 VMAXPD	%ZMM29,%ZMM31,%ZMM20

  (253) 0x438de9 VMOVAPD	%ZMM16,0x580(%RSP)

  (253) 0x438df1 VMAXPD	%ZMM9,%ZMM20,%ZMM16

  (253) 0x438df7 VPADDQ	%ZMM22,%ZMM0,%ZMM20

  (253) 0x438dfd VDIVPD	%ZMM16,%ZMM27,%ZMM11

  (253) 0x438e03 VPADDQ	%ZMM22,%ZMM1,%ZMM27

  (253) 0x438e09 VPSLLQ	$0x3,%ZMM20,%ZMM16

  (253) 0x438e10 VPSLLQ	$0x3,%ZMM27,%ZMM31

  (253) 0x438e17 VPADDQ	%ZMM13,%ZMM31,%ZMM29

  (253) 0x438e1d VPADDQ	%ZMM13,%ZMM16,%ZMM31

  (253) 0x438e23 VMOVAPD	%ZMM11,0x540(%RSP)

  (253) 0x438e2b VGATHERQPD	(,%ZMM29,1),%ZMM27{%K2}

  (253) 0x438e36 KMOVB	%K1,%K2

  (253) 0x438e3a VPADDQ	%ZMM22,%ZMM17,%ZMM29

  (253) 0x438e40 VGATHERQPD	(,%ZMM31,1),%ZMM20{%K3}

  (253) 0x438e4b VPSLLQ	$0x3,%ZMM29,%ZMM16

  (253) 0x438e52 VPADDQ	%ZMM13,%ZMM16,%ZMM29

  (253) 0x438e58 KMOVB	%K1,%K3

  (253) 0x438e5c VPADDQ	%ZMM22,%ZMM2,%ZMM16

  (253) 0x438e62 VGATHERQPD	(,%ZMM29,1),%ZMM31{%K4}

  (253) 0x438e6d VPSLLQ	$0x3,%ZMM16,%ZMM29

  (253) 0x438e74 VPADDQ	%ZMM13,%ZMM29,%ZMM16

  (253) 0x438e7a VPADDQ	%ZMM5,%ZMM17,%ZMM17

  (253) 0x438e80 VGATHERQPD	(,%ZMM16,1),%ZMM11{%K5}

  (253) 0x438e8b VADDPD	%ZMM31,%ZMM27,%ZMM27

  (253) 0x438e91 VPADDQ	%ZMM5,%ZMM1,%ZMM31

  (253) 0x438e97 VPADDQ	%ZMM5,%ZMM2,%ZMM2

  (253) 0x438e9d VMOVAPD	%ZMM11,0x500(%RSP)

  (253) 0x438ea5 VMOVDQA64	0x1c0(%RSP),%ZMM11

  (253) 0x438ead VADDPD	0x500(%RSP),%ZMM20,%ZMM20

  (253) 0x438eb5 KMOVB	%K1,%K4

  (253) 0x438eb9 KMOVB	%K1,%K5

  (253) 0x438ebd VPSLLQ	$0x3,%ZMM2,%ZMM2

  (253) 0x438ec4 VPADDQ	%ZMM11,%ZMM1,%ZMM29

  (253) 0x438eca VPSLLQ	$0x3,%ZMM29,%ZMM16

  (253) 0x438ed1 VPADDQ	%ZMM25,%ZMM16,%ZMM29

  (253) 0x438ed7 VGATHERQPD	(,%ZMM29,1),%ZMM16{%K6}

  (253) 0x438ee2 KMOVB	%K1,%K6

  (253) 0x438ee6 VPADDQ	%ZMM11,%ZMM0,%ZMM29

  (253) 0x438eec VMULPD	%ZMM16,%ZMM27,%ZMM27

  (253) 0x438ef2 VPSLLQ	$0x3,%ZMM29,%ZMM29

  (253) 0x438ef9 VPSLLQ	$0x3,%ZMM31,%ZMM16

  (253) 0x438f00 VPADDQ	%ZMM25,%ZMM29,%ZMM29

  (253) 0x438f06 VPADDQ	%ZMM5,%ZMM0,%ZMM31

  (253) 0x438f0c VGATHERQPD	(,%ZMM29,1),%ZMM11{%K7}

  (253) 0x438f17 VPADDQ	%ZMM13,%ZMM16,%ZMM29

  (253) 0x438f1d VPSLLQ	$0x3,%ZMM31,%ZMM16

  (253) 0x438f24 VMULPD	%ZMM11,%ZMM20,%ZMM20

  (253) 0x438f2a KMOVB	%K1,%K7

  (253) 0x438f2e VPADDQ	%ZMM13,%ZMM16,%ZMM31

  (253) 0x438f34 VGATHERQPD	(,%ZMM29,1),%ZMM11{%K2}

  (253) 0x438f3f VPSLLQ	$0x3,%ZMM17,%ZMM16

  (253) 0x438f46 VGATHERQPD	(,%ZMM31,1),%ZMM29{%K3}

  (253) 0x438f51 VPADDQ	%ZMM13,%ZMM16,%ZMM31

  (253) 0x438f57 VGATHERQPD	(,%ZMM31,1),%ZMM17{%K4}

  (253) 0x438f62 VMOVDQA64	0x180(%RSP),%ZMM31

  (253) 0x438f6a VPADDQ	%ZMM13,%ZMM2,%ZMM16

  (253) 0x438f70 VADDPD	%ZMM27,%ZMM19,%ZMM19

  (253) 0x438f76 VGATHERQPD	(,%ZMM16,1),%ZMM2{%K5}

  (253) 0x438f81 VADDPD	%ZMM17,%ZMM11,%ZMM11

  (253) 0x438f87 VANDPD	%ZMM12,%ZMM27,%ZMM17

  (253) 0x438f8d VADDPD	%ZMM2,%ZMM29,%ZMM29

  (253) 0x438f93 VADDPD	%ZMM20,%ZMM18,%ZMM18

  (253) 0x438f99 VPADDQ	%ZMM31,%ZMM1,%ZMM1

  (253) 0x438f9f VPADDQ	%ZMM31,%ZMM0,%ZMM0

  (253) 0x438fa5 VPSLLQ	$0x3,%ZMM1,%ZMM1

  (253) 0x438fac VPADDQ	%ZMM25,%ZMM1,%ZMM16

  (253) 0x438fb2 VPSLLQ	$0x3,%ZMM0,%ZMM0

  (253) 0x438fb9 VPADDQ	%ZMM25,%ZMM0,%ZMM0

  (253) 0x438fbf VGATHERQPD	(,%ZMM16,1),%ZMM1{%K6}

  (253) 0x438fca VGATHERQPD	(,%ZMM0,1),%ZMM31{%K7}

  (253) 0x438fd5 VMULPD	%ZMM1,%ZMM11,%ZMM1

  (253) 0x438fdb VMOVAPD	0x140(%RSP),%ZMM11

  (253) 0x438fe3 VMULPD	%ZMM31,%ZMM29,%ZMM16

  (253) 0x438fe9 VANDPD	%ZMM12,%ZMM1,%ZMM0

  (253) 0x438fef VADDPD	%ZMM1,%ZMM4,%ZMM4

  (253) 0x438ff5 VADDPD	%ZMM16,%ZMM3,%ZMM3

  (253) 0x438ffb VMAXPD	%ZMM17,%ZMM0,%ZMM0

  (253) 0x439001 VSUBPD	%ZMM19,%ZMM4,%ZMM1

  (253) 0x439007 VBROADCASTSD	0x2a56f(%RIP),%ZMM4

  (253) 0x439011 VMULPD	%ZMM11,%ZMM7,%ZMM2

  (253) 0x439017 VMAXPD	%ZMM10,%ZMM0,%ZMM10

  (253) 0x43901d VMULPD	%ZMM11,%ZMM30,%ZMM31

  (253) 0x439023 VANDPD	%ZMM12,%ZMM16,%ZMM11

  (253) 0x439029 VDIVPD	%ZMM10,%ZMM2,%ZMM0

  (253) 0x43902f VANDPD	%ZMM12,%ZMM20,%ZMM2

  (253) 0x439035 VMAXPD	%ZMM2,%ZMM11,%ZMM10

  (253) 0x43903b VMULPD	0x2b7fb(%RIP),%ZMM1,%ZMM11

  (253) 0x439045 VSUBPD	%ZMM18,%ZMM3,%ZMM2

  (253) 0x43904b VMOVAPD	%ZMM23,%ZMM1

  (253) 0x439051 VMAXPD	%ZMM9,%ZMM10,%ZMM9

  (253) 0x439057 VMULPD	0x2b7df(%RIP),%ZMM2,%ZMM10

  (253) 0x439061 VDIVPD	%ZMM9,%ZMM31,%ZMM29

  (253) 0x439067 VDIVPD	%ZMM7,%ZMM11,%ZMM7

  (253) 0x43906d VDIVPD	%ZMM30,%ZMM10,%ZMM9

  (253) 0x439073 VCMPPD	$0x1,0x2b802(%RIP),%ZMM7,%K2

  (253) 0x43907e VDIVPD	%ZMM7,%ZMM4,%ZMM11

  (253) 0x439084 VMOVAPD	0x100(%RSP),%ZMM7

  (253) 0x43908c VMULPD	%ZMM7,%ZMM11,%ZMM1{%K2}

  (253) 0x439092 VMINPD	0x600(%RSP),%ZMM1,%ZMM3

  (253) 0x43909a VCMPPD	$0x1,0x2b7db(%RIP),%ZMM9,%K3

  (253) 0x4390a5 VBROADCASTSD	0x2a4d1(%RIP),%ZMM2

  (253) 0x4390af VMINPD	0x680(%RSP),%ZMM23,%ZMM4

  (253) 0x4390b7 VMINPD	0x540(%RSP),%ZMM4,%ZMM11

  (253) 0x4390bf VDIVPD	%ZMM9,%ZMM2,%ZMM10

  (253) 0x4390c5 VMOVAPD	%ZMM23,%ZMM9

  (253) 0x4390cb VMINPD	0x640(%RSP),%ZMM23,%ZMM2

  (253) 0x4390d3 VMINPD	%ZMM0,%ZMM3,%ZMM0

  (253) 0x4390d9 VMULPD	%ZMM7,%ZMM10,%ZMM9{%K3}

  (253) 0x4390df VMINPD	0x5c0(%RSP),%ZMM9,%ZMM1

  (253) 0x4390e7 VMINPD	0x580(%RSP),%ZMM2,%ZMM10

  (253) 0x4390ef VMINPD	%ZMM29,%ZMM1,%ZMM7

  (253) 0x4390f5 VMINPD	%ZMM0,%ZMM10,%ZMM0

  (253) 0x4390fb VMINPD	%ZMM7,%ZMM11,%ZMM3

  (253) 0x439101 VMOVAPD	%ZMM0,0x640(%RSP)

  (253) 0x439109 VMOVAPD	%ZMM3,0x680(%RSP)

  (253) 0x439111 CMP	%ESI,%EDI

  (253) 0x439113 JNE	438960

(251) 0x439119 MOV	%EAX,%ESI

(251) 0x43911b VMOVQ	0x40(%RSP),%XMM31

(251) 0x439123 VMOVQ	0x38(%RSP),%XMM11

(251) 0x439129 VMOVQ	%R14,%XMM6

(251) 0x43912e AND	$-0x10,%ESI

(251) 0x439131 VMOVQ	0x30(%RSP),%XMM16

(251) 0x439139 VMOVSD	0x58(%RSP),%XMM3

(251) 0x43913f VMOVSD	0x50(%RSP),%XMM4

(251) 0x439145 VMOVQ	%R11,%XMM8

(251) 0x43914a ADD	%ESI,%R9D

(251) 0x43914d VMOVSD	0x48(%RSP),%XMM1

(251) 0x439153 VMOVSD	0x28(%RSP),%XMM2

(251) 0x439159 VMOVQ	%R15,%XMM9

(251) 0x43915e VMOVQ	%R8,%XMM5

(251) 0x439163 ADD	%ESI,0x74(%RSP)

(251) 0x439167 VMOVQ	%R13,%XMM10

(251) 0x43916c VMOVQ	%R12,%XMM26

(251) 0x439172 TEST	$0xf,%AL

(251) 0x439174 JE	439509

(251) 0x43917a MOV	0x60(%RSP),%RDI

(251) 0x43917f VMOVQ	%XMM6,%RBX

(251) 0x439184 VMOVQ	%XMM9,%R8

(251) 0x439189 VMOVSD	0x640(%RSP),%XMM15

(251) 0x439192 VMOVQ	0x8(%RBX),%XMM24

(251) 0x439199 VMOVQ	%XMM5,%RBX

(251) 0x43919e MOV	(%R8),%R13

(251) 0x4391a1 MOV	0x10(%R8),%R12

(251) 0x4391a5 VMOVQ	%XMM10,%RAX

(251) 0x4391aa VMOVSD	0x2b68c(%RIP),%XMM30

(251) 0x4391b4 VMOVSD	0x2b6c2(%RIP),%XMM29

(251) 0x4391be MOV	0x10(%RAX),%RSI

(251) 0x4391c2 MOVSXD	0x74(%RSP),%RAX

(251) 0x4391c7 MOV	0x8(%RDI),%R14

(251) 0x4391cb MOV	(%RBX),%RDI

(251) 0x4391ce IMUL	%RDX,%R13

(251) 0x4391d2 VMOVSD	(%R14,%RCX,1),%XMM25

(251) 0x4391d9 VMOVQ	%XMM8,%RCX

(251) 0x4391de MOV	0x10(%RBX),%R14

(251) 0x4391e2 IMUL	%RDX,%RDI

(251) 0x4391e6 MOV	(%RCX),%R11

(251) 0x4391e9 MOV	0x10(%RCX),%R15

(251) 0x4391ed VMOVQ	%XMM10,%RCX

(251) 0x4391f2 LEA	(%R12,%R13,8),%R13

(251) 0x4391f6 MOV	0x78(%RSP),%RBX

(251) 0x4391fb LEA	(%R14,%RDI,8),%R12

(251) 0x4391ff VMOVQ	%XMM26,%R14

(251) 0x439205 IMUL	%RDX,%R11

(251) 0x439209 MOV	(%R14),%RDI

(251) 0x43920c LEA	(%R15,%R11,8),%R11

(251) 0x439210 MOV	(%RCX),%R15

(251) 0x439213 MOV	0x10(%R14),%RCX

(251) 0x439217 IMUL	%RDX,%RDI

(251) 0x43921b SAL	$0x3,%R15

(251) 0x43921f MOV	%R15,%R8

(251) 0x439222 IMUL	%RBX,%R15

(251) 0x439226 VMOVQ	%XMM31,%RBX

(251) 0x43922c IMUL	%RDX,%R8

(251) 0x439230 MOV	(%RBX),%R14

(251) 0x439233 ADD	%RSI,%R8

(251) 0x439236 ADD	%R15,%RSI

(251) 0x439239 LEA	(%RCX,%RDI,8),%R15

(251) 0x43923d VMOVQ	%XMM11,%RCX

(251) 0x439242 MOV	(%RCX),%RCX

(251) 0x439245 MOV	0x10(%RBX),%RDI

(251) 0x439249 VMOVQ	%R15,%XMM13

(251) 0x43924e VMOVQ	%XMM16,%RBX

(251) 0x439254 VMOVQ	%XMM11,%R15

(251) 0x439259 IMUL	%RDX,%R14

(251) 0x43925d SAL	$0x3,%RCX

(251) 0x439261 LEA	(%RDI,%R14,8),%R14

(251) 0x439265 MOV	%RDX,%RDI

(251) 0x439268 IMUL	%RCX,%RDI

(251) 0x43926c ADD	0x10(%R15),%RDI

(251) 0x439270 MOV	(%RBX),%R15

(251) 0x439273 SAL	$0x3,%R15

(251) 0x439277 IMUL	%R15,%RDX

(251) 0x43927b ADD	0x10(%RBX),%RDX

(251) 0x43927f MOV	0x78(%RSP),%RBX

(251) 0x439284 IMUL	%RBX,%RCX

(251) 0x439288 VMOVQ	%XMM11,%RBX

(251) 0x43928d ADD	0x10(%RBX),%RCX

(251) 0x439291 MOV	0x78(%RSP),%RBX

(251) 0x439296 IMUL	%RBX,%R15

(251) 0x43929a VMOVQ	%XMM16,%RBX

(251) 0x4392a0 ADD	0x10(%RBX),%R15

(251) 0x4392a4 MOV	0x74(%RSP),%EBX

(251) 0x4392a8 SUB	%EBX,%R9D

(251) 0x4392ab VMOVQ	%XMM13,%RBX

(251) 0x4392b0 MOV	%R9D,0x600(%RSP)

(251) 0x4392b8 JMP	4392e3

0x4392ba NOPW	(%RAX,%RAX,1)

  (252) 0x4392c0 VMINSD	%XMM18,%XMM12,%XMM21

  (252) 0x4392c6 VMINSD	%XMM21,%XMM15,%XMM15

  (252) 0x4392cc MOV	0x600(%RSP),%R9D

  (252) 0x4392d4 INC	%RAX

  (252) 0x4392d7 ADD	%EAX,%R9D

  (252) 0x4392da CMP	%R10D,%R9D

  (252) 0x4392dd JAE	439500

  (252) 0x4392e3 VMOVSD	(%R13,%RAX,8),%XMM12

  (252) 0x4392ea VMOVSD	(%R11,%RAX,8),%XMM14

  (252) 0x4392f0 VADDSD	%XMM12,%XMM12,%XMM7

  (252) 0x4392f5 VDIVSD	(%R12,%RAX,8),%XMM7,%XMM0

  (252) 0x4392fb VFMADD132SD	%XMM14,%XMM0,%XMM14

  (252) 0x439300 VMOVQ	%XMM24,%R9

  (252) 0x439306 VMOVSD	(%R8,%RAX,8),%XMM0

  (252) 0x43930c VMOVSD	(%R14,%RAX,8),%XMM21

  (252) 0x439313 VMINSD	(%R9,%RAX,8),%XMM25,%XMM13

  (252) 0x43931a VMULSD	%XMM1,%XMM13,%XMM12

  (252) 0x43931e VADDSD	(%RSI,%RAX,8),%XMM0,%XMM13

  (252) 0x439323 VMULSD	0x2a25b(%RIP),%XMM21,%XMM22

  (252) 0x43932d VMULSD	%XMM21,%XMM2,%XMM23

  (252) 0x439333 VSQRTSD	%XMM14,%XMM14,%XMM14

  (252) 0x439338 VMAXSD	0x2a248(%RIP),%XMM14,%XMM14

  (252) 0x439340 VDIVSD	%XMM14,%XMM12,%XMM7

  (252) 0x439345 VMOVSD	0x8(%R8,%RAX,8),%XMM14

  (252) 0x43934c VMINSD	0x2a934(%RIP),%XMM7,%XMM12

  (252) 0x439354 VADDSD	0x8(%RSI,%RAX,8),%XMM14,%XMM0

  (252) 0x43935a VMULSD	(%RBX,%RAX,8),%XMM13,%XMM7

  (252) 0x43935f VMULSD	0x8(%RBX,%RAX,8),%XMM0,%XMM0

  (252) 0x439365 VANDPD	%XMM28,%XMM7,%XMM20

  (252) 0x43936b VANDPD	%XMM28,%XMM0,%XMM27

  (252) 0x439371 VMOVSD	(%RDI,%RAX,8),%XMM13

  (252) 0x439376 VADDSD	0x8(%RDI,%RAX,8),%XMM13,%XMM14

  (252) 0x43937c VMAXSD	%XMM20,%XMM27,%XMM17

  (252) 0x439382 VMULSD	(%RDX,%RAX,8),%XMM14,%XMM13

  (252) 0x439387 VMAXSD	%XMM22,%XMM17,%XMM19

  (252) 0x43938d VMOVSD	(%RCX,%RAX,8),%XMM14

  (252) 0x439392 VDIVSD	%XMM19,%XMM23,%XMM18

  (252) 0x439398 VADDSD	0x8(%RCX,%RAX,8),%XMM14,%XMM14

  (252) 0x43939e VANDPD	%XMM28,%XMM13,%XMM23

  (252) 0x4393a4 VMULSD	(%R15,%RAX,8),%XMM14,%XMM14

  (252) 0x4393aa VANDPD	%XMM28,%XMM14,%XMM20

  (252) 0x4393b0 VADDSD	%XMM14,%XMM0,%XMM0

  (252) 0x4393b5 VMULSD	%XMM21,%XMM3,%XMM27

  (252) 0x4393bb VADDSD	%XMM13,%XMM7,%XMM7

  (252) 0x4393c0 VMAXSD	%XMM23,%XMM20,%XMM17

  (252) 0x4393c6 VSUBSD	%XMM7,%XMM0,%XMM13

  (252) 0x4393ca VMAXSD	%XMM22,%XMM17,%XMM22

  (252) 0x4393d0 VMULSD	%XMM30,%XMM13,%XMM14

  (252) 0x4393d6 VDIVSD	%XMM22,%XMM27,%XMM19

  (252) 0x4393dc VDIVSD	%XMM21,%XMM14,%XMM0

  (252) 0x4393e2 VMINSD	%XMM19,%XMM18,%XMM18

  (252) 0x4393e8 VCOMISD	%XMM0,%XMM29

  (252) 0x4393ee JBE	4392c0

  (252) 0x4393f4 VMOVSD	0x2a184(%RIP),%XMM7

  (252) 0x4393fc VDIVSD	%XMM0,%XMM7,%XMM13

  (252) 0x439400 VMULSD	%XMM4,%XMM13,%XMM14

  (252) 0x439404 VMINSD	%XMM12,%XMM14,%XMM12

  (252) 0x439409 VMINSD	%XMM18,%XMM12,%XMM0

  (252) 0x43940f VMINSD	%XMM0,%XMM15,%XMM15

  (252) 0x439413 JMP	4392cc

0x439418 NOPL	(%RAX,%RAX,1)

0x439420 VMOVSD	0x10(%RSP),%XMM3

0x439426 VMOVSD	0x660(%RSP),%XMM5

0x43942f VMINSD	0x640(%RSP),%XMM3,%XMM4

0x439438 VMINSD	0x658(%RSP),%XMM5,%XMM10

0x439441 VMINSD	0x668(%RSP),%XMM4,%XMM1

0x43944a VMINSD	0x678(%RSP),%XMM10,%XMM11

0x439453 VMINSD	0x680(%RSP),%XMM1,%XMM6

0x43945c VMINSD	0x690(%RSP),%XMM11,%XMM2

0x439465 VMINSD	0x698(%RSP),%XMM6,%XMM8

0x43946e VMINSD	0x6a8(%RSP),%XMM2,%XMM7

0x439477 VMINSD	0x6b0(%RSP),%XMM8,%XMM9

0x439480 VMOVSD	0x648(%RSP),%XMM14

0x439489 VMINSD	%XMM7,%XMM9,%XMM13

0x43948d VMINSD	0x650(%RSP),%XMM14,%XMM12

0x439496 MOV	0x8(%RSP),%R14

0x43949b VMINSD	0x670(%RSP),%XMM12,%XMM0

0x4394a4 VMINSD	0x688(%RSP),%XMM0,%XMM15

0x4394ad VMINSD	0x6a0(%RSP),%XMM15,%XMM3

0x4394b6 VMINSD	0x6b8(%RSP),%XMM3,%XMM4

0x4394bf VMINSD	%XMM4,%XMM13,%XMM1

0x4394c3 VZEROUPPER

0x4394c6 MOV	0x70(%R14),%RAX

0x4394ca LEA	0x70(%R14),%R12

(250) 0x4394ce VMOVQ	%RAX,%XMM6

(250) 0x4394d3 VMINSD	%XMM6,%XMM1,%XMM8

(250) 0x4394d7 VMOVQ	%XMM8,%R13

(250) 0x4394dc LOCK CMPXCHG	%R13,(%R12)

(250) 0x4394e2 JNE	4394ce

0x4394e4 LEA	-0x28(%RBP),%RSP

0x4394e8 POP	%RBX

0x4394e9 POP	%R12

0x4394eb POP	%R13

0x4394ed POP	%R14

0x4394ef POP	%R15

0x4394f1 POP	%RBP

0x4394f2 RET

0x4394f3 NOPW	%CS:(%RAX,%RAX,1)

0x4394fe XCHG	%AX,%AX

(251) 0x439500 VMOVSD	%XMM15,0x640(%RSP)

(251) 0x439509 MOV	%R10D,%R9D

(251) 0x43950c MOV	0x68(%RSP),%R10

(251) 0x439511 INCQ	0x78(%RSP)

(251) 0x439516 MOV	%R10,%RDX

(251) 0x439519 CMP	%R10D,0x70(%RSP)

(251) 0x43951e JLE	439420

(251) 0x439524 MOV	0x1c(%RSP),%ECX

(251) 0x439528 MOV	0x24(%RSP),%EAX

(251) 0x43952c INC	%R10

(251) 0x43952f MOV	0x20(%RSP),%R11D

(251) 0x439534 MOV	%R10,0x68(%RSP)

(251) 0x439539 SUB	%R9D,%ECX

(251) 0x43953c MOV	%EAX,0x74(%RSP)

(251) 0x439540 JMP	4386e0

0x439545 INC	%ECX

0x439547 XOR	%EDX,%EDX

0x439549 JMP	43854d

0x43954e VMOVSD	0x2b26a(%RIP),%XMM1

0x439556 JMP	4394c6

0x43955b NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.45+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►2.32+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	calc_dt_kernel(int, int, int, [...]	calc_dt.cpp:49	exec
○	calc_dt(global_variables&, int[...]	calc_dt.cpp:131	exec
○	timestep(global_variables&, pa[...]	timestep.cpp:78	exec
○	hydro(global_variables&, paral[...]	hydro.cpp:60	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 18.75 to 13.25 cycles (1.42x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 18.75 to 10.10 cycles (1.86x speedup).

Details

7% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
7% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
13% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
VMOVDQA32: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60

Type of elements and instruction set

18 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 320 bytes (40 double precision FP elements). The binary function is storing 316 bytes (39 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	148
nb uops	150
loop length	787
used x86 registers	16
used mmx registers	0
used xmm registers	21
used ymm registers	0
used zmm registers	2
nb stack references	29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.75 cycles
front end	18.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	18.50	18.50	18.50	18.50	0.00	1.50	9.50	9.00	10.50	10.50
cycles	6.50	6.50	6.50	6.50	6.50	6.50	18.50	18.50	18.50	18.50	0.00	1.50	9.50	9.00	10.50	10.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	18.75
Dispatch	18.50
DIV/SQRT	12.00
Overall L1	18.75

Vectorization ratios

INT

all	12%
load	0%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

INT+FP

all	7%
load	0%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	13%

Vector efficiency ratios

INT

all	14%
load	11%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

INT+FP

all	13%
load	11%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.75 cycles. At this rate:

6% of peak load performance is reached (17.07 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (16.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4384c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x6c0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x80(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x84(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x7c(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ECX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EDX,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %ECX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43954e <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x108e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x24(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %ECX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RBX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43954e <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x108e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
IMUL %R12D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 439545 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1085>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVSD 0x2c267(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%R8,%RDX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%R9,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R10D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 4394c6 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1006>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x24(%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
VMOVQ 0x48(%R14),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x20(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	10-17	6	scal (6.3%)
VMOVSD 0x10(%R14),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R14),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x640(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x648(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x650(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x658(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x660(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x668(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x670(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x678(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x680(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x688(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x690(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x698(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x6a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x6a8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x6b0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x6b8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ 0x30(%R14),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x58(%R14),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%R14),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x50(%R14),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x60(%R14),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x10,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDSD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VPBROADCASTD %R12D,%ZMM7	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPBROADCASTD %EDI,%ZMM12	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
ADD %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x38(%R14),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (12.5%)
ADD %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDX,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RDX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ 0x20(%R14),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x28(%R14),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA32 %ZMM7,0xc0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
VMOVQ 0x40(%R14),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x68(%R14),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R15,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ 0x2b56e(%RIP),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R14,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA32 %ZMM12,0x80(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
VMOVDQA64 %XMM5,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA64 %XMM25,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVSD 0x10(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x660(%RSP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMINSD 0x640(%RSP),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x658(%RSP),%XMM5,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x668(%RSP),%XMM4,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x678(%RSP),%XMM10,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x680(%RSP),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x690(%RSP),%XMM11,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x698(%RSP),%XMM6,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x6a8(%RSP),%XMM2,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x6b0(%RSP),%XMM8,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD 0x648(%RSP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMINSD %XMM7,%XMM9,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x650(%RSP),%XMM14,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x8(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
VMINSD 0x670(%RSP),%XMM12,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x688(%RSP),%XMM0,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x6a0(%RSP),%XMM15,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x6b8(%RSP),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD %XMM4,%XMM13,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV 0x70(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
LEA 0x70(%R14),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43854d <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x8d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSD 0x2b26a(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 4394c6 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1006>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	calc_dt.cpp:49-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:49-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

7% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
7% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
13% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:51
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:55
VMOVDQA32: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:63
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/calc_dt.cpp:60

Type of elements and instruction set

18 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 320 bytes (40 double precision FP elements). The binary function is storing 316 bytes (39 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	148
nb uops	150
loop length	787
used x86 registers	16
used mmx registers	0
used xmm registers	21
used ymm registers	0
used zmm registers	2
nb stack references	29

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.75 cycles
front end	18.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	18.50	18.50	18.50	18.50	0.00	1.50	9.50	9.00	10.50	10.50
cycles	6.50	6.50	6.50	6.50	6.50	6.50	18.50	18.50	18.50	18.50	0.00	1.50	9.50	9.00	10.50	10.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	18.75
Dispatch	18.50
DIV/SQRT	12.00
Overall L1	18.75

Vectorization ratios

INT

all	12%
load	0%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	21%

all	2%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

INT+FP

all	7%
load	0%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	13%

Vector efficiency ratios

INT

all	14%
load	11%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

INT+FP

all	13%
load	11%
store	17%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 18.75 cycles. At this rate:

6% of peak load performance is reached (17.07 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (16.85 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4384c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x6c0,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x80(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x84(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x78(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
MOV 0x7c(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ECX,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %EDX,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %ECX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43954e <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x108e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x24(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
MOV %ECX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x2(%RBX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 43954e <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x108e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x20(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
IMUL %R12D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 439545 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1085>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVSD 0x2c267(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
LEA (%R8,%RDX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%R9,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R10D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
CMP %R10D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 4394c6 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1006>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R9D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x24(%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (6.3%)
VMOVQ 0x48(%R14),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
DIVL 0x20(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	10-17	6	scal (6.3%)
VMOVSD 0x10(%R14),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x8(%R14),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R14),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x640(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x648(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x650(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x658(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x660(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x668(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x670(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x678(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x680(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x688(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x690(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x698(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x6a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x6a8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x6b0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD %XMM1,0x6b8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ 0x30(%R14),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x58(%R14),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x18(%R14),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x50(%R14),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x60(%R14),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
MOV $0x10,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV $0x1,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVAPD %XMM0,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VADDSD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VADDSD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VPBROADCASTD %R12D,%ZMM7	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VPBROADCASTD %EDI,%ZMM12	2	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
ADD %R11D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R13D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV 0x38(%R14),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (12.5%)
ADD %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EDX,0x74(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (6.3%)
SUB %EDX,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RDX),%R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %R13,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ 0x20(%R14),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x28(%R14),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA32 %ZMM7,0xc0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
VMOVQ 0x40(%R14),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ 0x68(%R14),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R15,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ 0x2b56e(%RIP),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %R14,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA32 %ZMM12,0x80(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	1	1	4	1	vect (100.0%)
VMOVDQA64 %XMM5,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA64 %XMM25,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VMOVSD 0x10(%RSP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD 0x660(%RSP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMINSD 0x640(%RSP),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x658(%RSP),%XMM5,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x668(%RSP),%XMM4,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x678(%RSP),%XMM10,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x680(%RSP),%XMM1,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x690(%RSP),%XMM11,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x698(%RSP),%XMM6,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x6a8(%RSP),%XMM2,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x6b0(%RSP),%XMM8,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMOVSD 0x648(%RSP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
VMINSD %XMM7,%XMM9,%XMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x650(%RSP),%XMM14,%XMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
MOV 0x8(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
VMINSD 0x670(%RSP),%XMM12,%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x688(%RSP),%XMM0,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x6a0(%RSP),%XMM15,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD 0x6b8(%RSP),%XMM3,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VMINSD %XMM4,%XMM13,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	scal (12.5%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
MOV 0x70(%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	N/A
LEA 0x70(%R14),%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43854d <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x8d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
VMOVSD 0x2b26a(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	1	0.50	scal (12.5%)
JMP 4394c6 <_Z14calc_dt_kerneliiiidddddRN6clover8Buffer2DIdEES2_RNS_8Buffer1DIdEES5_S5_S5_S2_S2_S2_S2_S2_S2_S2_S2_RdRiS6_S6_S7_S7_S7_._omp_fn.0+0x1006>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼calc_dt_kernel(int, int, int, int, double, double, double, double, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D–	3.26	1.20
▼Loop 251 - calc_dt.cpp:49-75 - exec–	0.00	0.01
○Loop 253 - calc_dt.cpp:52-75 - exec	3.26	1.20
○Loop 252 - calc_dt.cpp:54-75 - exec	0.00	0.00
○Loop 250 - calc_dt.cpp:49-49 - exec	0.00	0.00

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Matching between your function (in the source code) and the binary function

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Vector efficiency ratios

Cycles and memory resources usage

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