OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage (incl. loops): 3.61% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

0x4354f0 PUSH	%RBP

0x4354f1 MOV	%RSP,%RBP

0x4354f4 PUSH	%R15

0x4354f6 PUSH	%R14

0x4354f8 PUSH	%R13

0x4354fa PUSH	%R12

0x4354fc PUSH	%RBX

0x4354fd MOV	%RDI,%R13

0x435500 SUB	$0x38,%RSP

0x435504 MOV	0x34(%RDI),%EAX

0x435507 MOV	0x28(%RDI),%ESI

0x43550a MOV	0x30(%RDI),%R14D

0x43550e MOV	0x2c(%RDI),%EDI

0x435511 ADD	$0x3,%EAX

0x435514 INC	%ESI

0x435516 MOV	%EAX,-0x4c(%RBP)

0x435519 MOV	%ESI,-0x50(%RBP)

0x43551c CMP	%EAX,%R14D

0x43551f JGE	4357e0

0x435525 MOV	%EAX,%EBX

0x435527 LEA	0x3(%RDI),%R15D

0x43552b SUB	%R14D,%EBX

0x43552e CMP	%R15D,%ESI

0x435531 JGE	4357e0

0x435537 MOV	%R15D,%EDX

0x43553a SUB	%ESI,%EDX

0x43553c MOV	%EDX,-0x48(%RBP)

0x43553f CALL	404630 <omp_get_num_threads@plt>

0x435544 MOV	%EAX,%R12D

0x435547 CALL	404520 <omp_get_thread_num@plt>

0x43554c XOR	%EDX,%EDX

0x43554e MOV	%EAX,%ECX

0x435550 MOV	-0x48(%RBP),%EAX

0x435553 IMUL	%EBX,%EAX

0x435556 DIV	%R12D

0x435559 MOV	%EAX,%R9D

0x43555c CMP	%EDX,%ECX

0x43555e JB	435845

0x435564 IMUL	%R9D,%ECX

0x435568 LEA	(%RCX,%RDX,1),%ECX

0x43556b LEA	(%R9,%RCX,1),%EDI

0x43556f CMP	%EDI,%ECX

0x435571 JAE	4357e0

0x435577 MOV	%ECX,%EAX

0x435579 XOR	%EDX,%EDX

0x43557b MOV	-0x50(%RBP),%R8D

0x43557f MOV	(%R13),%RSI

0x435583 DIVL	-0x48(%RBP)

0x435586 VMOVQ	0x8(%R13),%XMM7

0x43558c VMOVQ	0x10(%R13),%XMM3

0x435592 VMOVQ	0x2e696(%RIP),%XMM6

0x43559a VMOVQ	0x20(%R13),%XMM20

0x4355a1 MOV	0x18(%R13),%R13

0x4355a5 VMOVSD	0x2ef8b(%RIP),%XMM15

0x4355ad VMOVSD	0x2f0f3(%RIP),%XMM14

0x4355b5 VMOVSD	0x2dfc1(%RIP),%XMM19

0x4355bf VMOVSD	0x2e3c9(%RIP),%XMM13

0x4355c7 MOV	%EDI,-0x54(%RBP)

0x4355ca VMOVQ	%RSI,%XMM4

0x4355cf VMOVQ	%R13,%XMM8

0x4355d4 LEA	(%RAX,%R14,1),%R11D

0x4355d8 ADD	%R8D,%EDX

0x4355db LEA	-0x1(%R14,%RAX,1),%R10D

0x4355e0 MOVSXD	%R11D,%R11

0x4355e3 SUB	%EDX,%R15D

0x4355e6 INC	%R11

0x4355e9 NOPL	(%RAX)

(235) 0x4355f0 CMP	%R15D,%R9D

(235) 0x4355f3 CMOVA	%R15D,%R9D

(235) 0x4355f7 LEA	0x2(%R10),%R15D

(235) 0x4355fb LEA	(%RCX,%R9,1),%R14D

(235) 0x4355ff MOV	%R15D,-0x3c(%RBP)

(235) 0x435603 MOV	%R14D,-0x44(%RBP)

(235) 0x435607 CMP	%R14D,%ECX

(235) 0x43560a JAE	435840

(235) 0x435610 VMOVQ	%XMM20,%RCX

(235) 0x435616 MOVSXD	%EDX,%RDX

(235) 0x435619 LEA	-0x1(%R9),%R9D

(235) 0x43561d VMOVQ	%XMM7,%R13

(235) 0x435622 VMOVQ	0x8(%RCX),%XMM9

(235) 0x435627 LEA	0x1(%RDX,%R9,1),%R8

(235) 0x43562c MOV	(%R13),%R14

(235) 0x435630 VMOVQ	%XMM4,%RAX

(235) 0x435635 MOV	%R8,-0x38(%RBP)

(235) 0x435639 VMOVQ	%XMM8,%R8

(235) 0x43563e LEA	-0x1(%R11),%RBX

(235) 0x435642 MOV	(%RAX),%RSI

(235) 0x435645 MOV	(%R8),%R9

(235) 0x435648 VMOVQ	%XMM3,%R12

(235) 0x43564d LEA	0x1(%RDX),%RCX

(235) 0x435651 VXORPD	%XMM5,%XMM5,%XMM5

(235) 0x435655 VMOVQ	0x10(%R12),%XMM12

(235) 0x43565c VMOVQ	(%R12),%XMM11

(235) 0x435662 MOV	0x10(%RAX),%R12

(235) 0x435666 IMUL	%RBX,%R14

(235) 0x43566a VMOVQ	%XMM9,%RDI

(235) 0x43566f LEA	-0x8(%RDI,%R11,8),%R15

(235) 0x435674 MOV	0x10(%R13),%RDI

(235) 0x435678 MOV	0x10(%R8),%R13

(235) 0x43567c IMUL	%RBX,%R9

(235) 0x435680 LEA	(%RDI,%R14,8),%RAX

(235) 0x435684 LEA	(%R13,%R9,8),%RDI

(235) 0x435689 LEA	0x3(%R10),%R14D

(235) 0x43568d MOV	%RSI,%R13

(235) 0x435690 MOV	%R14D,-0x40(%RBP)

(235) 0x435694 VMOVQ	%RAX,%XMM10

(235) 0x435699 MOV	%R11,%R14

(235) 0x43569c MOV	%RBX,%RSI

(235) 0x43569f MOV	%R15,%R11

(235) 0x4356a2 MOV	%RDI,%R15

(235) 0x4356a5 JMP	4357af

0x4356aa NOPW	(%RAX,%RAX,1)

  (236) 0x4356b0 MOVSXD	%R10D,%RAX

  (236) 0x4356b3 MOV	%R14,%R9

  (236) 0x4356b6 MOV	%RSI,%R8

  (236) 0x4356b9 MOVSXD	%R10D,%RDI

  (236) 0x4356bc MOV	%R13,%RBX

  (236) 0x4356bf IMUL	%R13,%RAX

  (236) 0x4356c3 IMUL	%R8,%RBX

  (236) 0x4356c7 IMUL	%R13,%R9

  (236) 0x4356cb ADD	%RDX,%RAX

  (236) 0x4356ce ADD	%RDX,%RBX

  (236) 0x4356d1 ADD	%RDX,%R9

  (236) 0x4356d4 VMOVSD	(%R12,%RBX,8),%XMM1

  (236) 0x4356da VSUBSD	(%R12,%RAX,8),%XMM1,%XMM2

  (236) 0x4356e0 VMOVSD	(%R12,%R9,8),%XMM0

  (236) 0x4356e6 VSUBSD	%XMM1,%XMM0,%XMM0

  (236) 0x4356ea VMULSD	%XMM2,%XMM0,%XMM17

  (236) 0x4356f0 VCOMISD	%XMM5,%XMM17

  (236) 0x4356f6 JBE	435797

  (236) 0x4356fc VANDPD	%XMM6,%XMM2,%XMM2

  (236) 0x435700 VANDPD	%XMM6,%XMM0,%XMM23

  (236) 0x435706 VCOMISD	%XMM0,%XMM5

  (236) 0x43570a JAE	4357f0

  (236) 0x435710 VMOVAPD	%XMM13,%XMM25

  (236) 0x435716 VMOVAPD	%XMM13,%XMM24

  (236) 0x43571c VMOVQ	%XMM11,%RAX

  (236) 0x435721 VMOVQ	%XMM12,%R9

  (236) 0x435726 VANDPD	%XMM6,%XMM21,%XMM22

  (236) 0x43572c VMOVSD	(%R11),%XMM27

  (236) 0x435732 IMUL	%RAX,%R8

  (236) 0x435736 VMULSD	%XMM14,%XMM27,%XMM29

  (236) 0x43573c VMINSD	%XMM2,%XMM23,%XMM30

  (236) 0x435742 ADD	%RDX,%R8

  (236) 0x435745 VDIVSD	(%R9,%R8,8),%XMM22,%XMM16

  (236) 0x43574c VMOVQ	%XMM9,%R8

  (236) 0x435751 VADDSD	%XMM25,%XMM16,%XMM0

  (236) 0x435757 VSUBSD	%XMM16,%XMM15,%XMM26

  (236) 0x43575d VMULSD	%XMM2,%XMM0,%XMM0

  (236) 0x435761 VMULSD	%XMM23,%XMM26,%XMM18

  (236) 0x435767 VDIVSD	(%R8,%RDI,8),%XMM0,%XMM0

  (236) 0x43576d VDIVSD	%XMM27,%XMM18,%XMM28

  (236) 0x435773 VSUBSD	%XMM16,%XMM25,%XMM31

  (236) 0x435779 VADDSD	%XMM28,%XMM0,%XMM0

  (236) 0x43577f VMULSD	%XMM29,%XMM0,%XMM0

  (236) 0x435785 VMINSD	%XMM30,%XMM0,%XMM2

  (236) 0x43578b VMULSD	%XMM31,%XMM2,%XMM0

  (236) 0x435791 VFMADD231SD	%XMM24,%XMM0,%XMM1

  (236) 0x435797 VMULSD	%XMM21,%XMM1,%XMM1

  (236) 0x43579d VMOVSD	%XMM1,(%R15,%RDX,8)

  (236) 0x4357a3 MOV	%RCX,%RDX

  (236) 0x4357a6 CMP	%RCX,-0x38(%RBP)

  (236) 0x4357aa JE	435810

  (236) 0x4357ac INC	%RCX

  (236) 0x4357af VMOVQ	%XMM10,%RBX

  (236) 0x4357b4 VMOVSD	(%RBX,%RDX,8),%XMM21

  (236) 0x4357bb VCOMISD	%XMM21,%XMM5

  (236) 0x4357c1 JBE	4356b0

  (236) 0x4357c7 MOVSXD	-0x40(%RBP),%RAX

  (236) 0x4357cb MOVSXD	-0x3c(%RBP),%RDI

  (236) 0x4357cf MOV	%RSI,%R9

  (236) 0x4357d2 MOV	%R14,%R8

  (236) 0x4357d5 JMP	4356bc

0x4357da NOPW	(%RAX,%RAX,1)

0x4357e0 ADD	$0x38,%RSP

0x4357e4 POP	%RBX

0x4357e5 POP	%R12

0x4357e7 POP	%R13

0x4357e9 POP	%R14

0x4357eb POP	%R15

0x4357ed POP	%RBP

0x4357ee RET

0x4357ef NOP

  (236) 0x4357f0 VMOVAPD	%XMM19,%XMM24

  (236) 0x4357f6 VMOVSD	0x2e190(%RIP),%XMM25

  (236) 0x435800 JMP	43571c

0x435805 NOPW	%CS:(%RAX,%RAX,1)

(235) 0x435810 MOV	%R14,%R11

(235) 0x435813 MOV	-0x3c(%RBP),%R12D

(235) 0x435817 INC	%R10D

(235) 0x43581a INC	%R11

(235) 0x43581d CMP	%R12D,-0x4c(%RBP)

(235) 0x435821 JLE	4357e0

(235) 0x435823 MOV	-0x54(%RBP),%R9D

(235) 0x435827 MOV	-0x44(%RBP),%ECX

(235) 0x43582a MOV	-0x48(%RBP),%R15D

(235) 0x43582e MOV	-0x50(%RBP),%EDX

(235) 0x435831 SUB	%ECX,%R9D

(235) 0x435834 JMP	4355f0

0x435839 NOPL	(%RAX)

(235) 0x435840 MOV	%ECX,-0x44(%RBP)

(235) 0x435843 JMP	435813

0x435845 INC	%R9D

0x435848 XOR	%EDX,%EDX

0x43584a JMP	435564

0x43584f NOP

Coverage (%)	Name	Source Location	Module
►96.86+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.13 cycles (5.65x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.25 cycles (1.17x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.00 cycles (1.20x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:182
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:182

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:182
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:205

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 108 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	84
nb uops	82
loop length	313
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.25 cycles
front end	10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.25
Dispatch	6.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (9.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4354f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x30(%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ESI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4357e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x2f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RDI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4357e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x2f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 435845 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x355>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RDX,1),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R9,%RCX,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP %EDI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4357e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x2f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x50(%RBP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%R13),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
DIVL -0x48(%RBP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%R13),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x2e696(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R13),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x18(%R13),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVSD 0x2ef8b(%RIP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0x2f0f3(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0x2dfc1(%RIP),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0x2e3c9(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %EDI,-0x54(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
VMOVQ %RSI,%XMM4	1	0	0	1	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R13,%XMM8	1	0	0	1	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RAX,%R14,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %R8D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%R14,%RAX,1),%R10D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOVSXD %R11D,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 435564 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x74>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.13 cycles (5.65x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.00 cycles (1.20x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:182
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:182

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:182
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:199
LEA: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:205

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 108 bytes. The binary function is storing 16 bytes.

General properties

nb instructions	84
nb uops	82
loop length	313
used x86 registers	16
used mmx registers	0
used xmm registers	10
used ymm registers	0
used zmm registers	0
nb stack references	4

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.25 cycles
front end	10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	6.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.25
Dispatch	6.00
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	0%

Vector efficiency ratios

INT

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	8%
load	10%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

3% of peak load performance is reached (9.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4354f0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x30(%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ESI,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EAX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4357e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x2f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RDI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 4357e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x2f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV -0x48(%RBP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 435845 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x355>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RCX,%RDX,1),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA (%R9,%RCX,1),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
CMP %EDI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 4357e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x2f0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV -0x50(%RBP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV (%R13),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
DIVL -0x48(%RBP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x8(%R13),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x2e696(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x20(%R13),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV 0x18(%R13),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
VMOVSD 0x2ef8b(%RIP),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0x2f0f3(%RIP),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0x2dfc1(%RIP),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVSD 0x2e3c9(%RIP),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV %EDI,-0x54(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
VMOVQ %RSI,%XMM4	1	0	0	1	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %R13,%XMM8	1	0	0	1	0	0	0	0	0	0	0	2	1	scal (12.5%)
LEA (%RAX,%R14,1),%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
ADD %R8D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%R14,%RAX,1),%R10D	2	0	0	0.50	0.50	0	0	0.25	0.25	0.25	0.25	2	0.50	N/A
MOVSXD %R11D,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
ADD $0x38,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 435564 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.10+0x74>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.61	1.33
▼Loop 235 - advec_mom.cpp:182-211 - exec–	0.01	0.01
○Loop 236 - advec_mom.cpp:186-211 - exec	3.61	1.32

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Expensive FP math instructions/calls

CALL instructions

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code