OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:108-139 [...]	Coverage (incl. loops): 3.66% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 108 - 139

--------------------------------------------------------------------------------

108: #pragma omp parallel for simd collapse(2)

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

115:             upwind = i + 2;

116:             donor = i + 1;

117:             downwind = i;

118:             dif = donor;

119:           } else {

120:             upwind = i - 1;

121:             donor = i;

122:             downwind = i + 1;

123:             dif = upwind;

124:           }

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

0x4349c0 PUSH	%RBP

0x4349c1 MOV	%RSP,%RBP

0x4349c4 PUSH	%R15

0x4349c6 PUSH	%R14

0x4349c8 PUSH	%R13

0x4349ca PUSH	%R12

0x4349cc PUSH	%RBX

0x4349cd AND	$-0x40,%RSP

0x4349d1 SUB	$0x180,%RSP

0x4349d8 MOV	0x30(%RDI),%EAX

0x4349db MOV	0x34(%RDI),%EDX

0x4349de MOV	0x28(%RDI),%ESI

0x4349e1 MOV	0x2c(%RDI),%EBX

0x4349e4 VMOVAPD	%YMM3,0xa0(%RSP)

0x4349ed VMOVAPD	%YMM4,0x140(%RSP)

0x4349f6 VMOVAPD	%ZMM27,0xc0(%RSP)

0x4349fe VMOVAPD	%ZMM28,0x100(%RSP)

0x434a06 ADD	$0x3,%EDX

0x434a09 LEA	0x1(%RAX),%R12D

0x434a0d MOV	%ESI,0x160(%RSP)

0x434a14 MOV	%EDX,0x164(%RSP)

0x434a1b CMP	%EDX,%R12D

0x434a1e JGE	435450

0x434a24 MOV	%RDI,%R14

0x434a27 LEA	0x3(%RBX),%EDI

0x434a2a MOV	%EDX,%EBX

0x434a2c SUB	%R12D,%EBX

0x434a2f CMP	%EDI,%ESI

0x434a31 JGE	435450

0x434a37 MOV	%EDI,%R15D

0x434a3a MOV	%EDI,0x178(%RSP)

0x434a41 SUB	%ESI,%R15D

0x434a44 MOV	%R15D,0x5c(%RSP)

0x434a49 VZEROUPPER

0x434a4c CALL	404630 <omp_get_num_threads@plt>

0x434a51 MOV	%EAX,%R13D

0x434a54 CALL	404520 <omp_get_thread_num@plt>

0x434a59 XOR	%EDX,%EDX

0x434a5b VMOVAPD	0x100(%RSP),%ZMM28

0x434a63 MOV	%EAX,%R8D

0x434a66 MOV	%R15D,%EAX

0x434a69 VMOVAPD	0xc0(%RSP),%ZMM27

0x434a71 VMOVAPD	0x140(%RSP),%YMM4

0x434a7a IMUL	%EBX,%EAX

0x434a7d VMOVAPD	0xa0(%RSP),%YMM3

0x434a86 MOV	0x178(%RSP),%R9D

0x434a8e DIV	%R13D

0x434a91 CMP	%EDX,%R8D

0x434a94 MOV	%EAX,%ECX

0x434a96 JB	4354de

0x434a9c IMUL	%ECX,%R8D

0x434aa0 LEA	(%R8,%RDX,1),%R15D

0x434aa4 LEA	(%RCX,%R15,1),%R10D

0x434aa8 MOV	%R10D,0x58(%RSP)

0x434aad CMP	%R10D,%R15D

0x434ab0 JAE	435450

0x434ab6 MOV	%R15D,%EAX

0x434ab9 XOR	%EDX,%EDX

0x434abb MOV	0x160(%RSP),%R11D

0x434ac3 VMOVQ	0x8(%R14),%XMM23

0x434aca DIVL	0x5c(%RSP)

0x434ace VMOVQ	0x10(%R14),%XMM24

0x434ad5 VMOVQ	(%R14),%XMM25

0x434adb MOV	0x20(%R14),%RSI

0x434adf VMOVQ	0x18(%R14),%XMM26

0x434ae6 VMOVDQA32	0x2fb50(%RIP),%YMM31

0x434af0 VMOVAPD	%YMM4,%YMM20

0x434af6 VMOVAPD	%YMM3,%YMM14

0x434afa VMOVQ	0x2f12c(%RIP),%XMM29

0x434b04 VMOVSD	0x2ee82(%RIP),%XMM30

0x434b0e VMOVQ	%XMM23,0x48(%RSP)

0x434b16 MOV	%RSI,0x50(%RSP)

0x434b1b VMOVQ	%XMM24,0x40(%RSP)

0x434b23 VMOVQ	%XMM25,0x38(%RSP)

0x434b2b VMOVQ	%XMM26,0x30(%RSP)

0x434b33 ADD	%EDX,%R11D

0x434b36 ADD	%R12D,%EAX

0x434b39 SUB	%R11D,%R9D

0x434b3c MOVSXD	%EAX,%R12

0x434b3f MOV	%R11D,0xc0(%RSP)

0x434b47 MOV	%R9D,%R13D

0x434b4a NOPW	(%RAX,%RAX,1)

(232) 0x434b50 CMP	%R13D,%ECX

(232) 0x434b53 MOV	%R13D,%R10D

(232) 0x434b56 CMOVBE	%ECX,%R10D

(232) 0x434b5a LEA	(%R15,%R10,1),%EBX

(232) 0x434b5e CMP	%EBX,%R15D

(232) 0x434b61 JAE	43549b

(232) 0x434b67 MOV	0x48(%RSP),%RCX

(232) 0x434b6c MOV	0x40(%RSP),%RDI

(232) 0x434b71 MOV	0x38(%RSP),%R8

(232) 0x434b76 MOV	0x30(%RSP),%RAX

(232) 0x434b7b MOV	0x50(%RSP),%R13

(232) 0x434b80 MOV	(%RCX),%RDX

(232) 0x434b83 MOV	0x10(%RDI),%R9

(232) 0x434b87 MOV	(%RDI),%R11

(232) 0x434b8a VMOVQ	0x10(%R8),%XMM2

(232) 0x434b90 MOV	(%R8),%RDI

(232) 0x434b93 MOV	(%RAX),%R8

(232) 0x434b96 MOV	0x10(%RCX),%R14

(232) 0x434b9a MOV	0x10(%RAX),%RSI

(232) 0x434b9e MOV	0x8(%R13),%RCX

(232) 0x434ba2 IMUL	%R12,%RDX

(232) 0x434ba6 MOV	%R9,0x178(%RSP)

(232) 0x434bae IMUL	%R12,%R11

(232) 0x434bb2 MOV	%R14,0x140(%RSP)

(232) 0x434bba LEA	-0x1(%R10),%R14D

(232) 0x434bbe MOV	%RSI,0x170(%RSP)

(232) 0x434bc6 IMUL	%R12,%R8

(232) 0x434bca IMUL	%R12,%RDI

(232) 0x434bce MOV	%RDX,0xa0(%RSP)

(232) 0x434bd6 MOV	%R11,0x100(%RSP)

(232) 0x434bde MOV	%R8,0x168(%RSP)

(232) 0x434be6 CMP	$0xe,%R14D

(232) 0x434bea JBE	4354d0

(232) 0x434bf0 MOVSXD	0xc0(%RSP),%R13

(232) 0x434bf8 VMOVQ	%XMM2,%RAX

(232) 0x434bfd VPBROADCASTD	0xc0(%RSP),%ZMM15

(232) 0x434c05 LEA	(%R9,%R11,8),%R9

(232) 0x434c09 VPADDD	0x2faad(%RIP),%ZMM15,%ZMM15

(232) 0x434c13 MOV	%R10D,%R11D

(232) 0x434c16 VBROADCASTSD	0x2f010(%RIP),%ZMM11

(232) 0x434c20 VBROADCASTSD	0x2ed66(%RIP),%ZMM10

(232) 0x434c2a VBROADCASTSD	0x2e94c(%RIP),%ZMM19

(232) 0x434c34 VBROADCASTSD	0x2f8fa(%RIP),%ZMM18

(232) 0x434c3e VBROADCASTSD	0x2fa60(%RIP),%ZMM17

(232) 0x434c48 KXNORB	%K1,%K1,%K1

(232) 0x434c4c SHR	$0x4,%R11D

(232) 0x434c50 VPXORD	%XMM16,%XMM16,%XMM16

(232) 0x434c56 VMOVAPD	%YMM20,0x80(%RSP)

(232) 0x434c5e VMOVAPD	%YMM14,0x60(%RSP)

(232) 0x434c64 LEA	(%RDX,%R13,1),%R14

(232) 0x434c68 LEA	(%RAX,%RDI,8),%RDX

(232) 0x434c6c LEA	(%RCX,%R13,8),%RAX

(232) 0x434c70 ADD	%R8,%R13

(232) 0x434c73 MOV	$0x10,%R8D

(232) 0x434c79 LEA	(%RSI,%R13,8),%R13

(232) 0x434c7d VXORPD	%XMM0,%XMM0,%XMM0

(232) 0x434c81 VPTERNLOGD	$-0x1,%ZMM16,%ZMM16,%ZMM16

(232) 0x434c88 VPBROADCASTD	%R8D,%ZMM26

(232) 0x434c8e MOV	0x140(%RSP),%R8

(232) 0x434c96 SUB	%RAX,%R13

(232) 0x434c99 SAL	$0x7,%R11

(232) 0x434c9d ADD	%RAX,%R11

(232) 0x434ca0 LEA	(%R8,%R14,8),%R8

(232) 0x434ca4 MOV	$0x1,%R14D

(232) 0x434caa VPBROADCASTD	%R14D,%ZMM25

(232) 0x434cb0 MOV	$0x2,%R14D

(232) 0x434cb6 SUB	%RAX,%R8

(232) 0x434cb9 VPBROADCASTD	%R14D,%ZMM24

(232) 0x434cbf VMOVQ	%XMM2,%R14

(232) 0x434cc4 NOPW	%CS:(%RAX,%RAX,1)

(232) 0x434ccf NOP

  (234) 0x434cd0 VMOVUPD	(%R8,%RAX,1),%ZMM23

  (234) 0x434cd7 VMOVUPD	0x40(%R8,%RAX,1),%ZMM22

  (234) 0x434cdf VMOVDQA32	%ZMM15,%ZMM1

  (234) 0x434ce5 KMOVB	%K1,%K6

  (234) 0x434ce9 VPADDD	%ZMM26,%ZMM15,%ZMM15

  (234) 0x434cef VPMOVSXDQ	%YMM1,%ZMM8

  (234) 0x434cf5 VEXTRACTI32X8	$0x1,%ZMM1,%YMM7

  (234) 0x434cfc VPADDD	%ZMM25,%ZMM1,%ZMM13

  (234) 0x434d02 VPADDD	%ZMM16,%ZMM1,%ZMM6

  (234) 0x434d08 VPMOVSXDQ	%YMM7,%ZMM5

  (234) 0x434d0e VEXTRACTI32X8	$0x1,%ZMM13,%YMM9

  (234) 0x434d15 KMOVB	%K1,%K7

  (234) 0x434d19 VPMOVSXDQ	%YMM13,%ZMM21

  (234) 0x434d1f VMOVDQA64	%ZMM8,%ZMM20

  (234) 0x434d25 VMOVDQA	%YMM13,%YMM12

  (234) 0x434d2a VPMOVSXDQ	%YMM9,%ZMM14

  (234) 0x434d30 VCMPPD	$0x1,%ZMM0,%ZMM23,%K4

  (234) 0x434d37 VCMPPD	$0x1,%ZMM0,%ZMM22,%K3

  (234) 0x434d3e VMOVDQA64	%ZMM5,%ZMM3

  (234) 0x434d44 KUNPCKBW	%K4,%K3,%K2

  (234) 0x434d48 VPMOVSXDQ	%YMM12,%ZMM20{%K4}

  (234) 0x434d4e VMOVDQA64	%ZMM8,%ZMM21{%K4}

  (234) 0x434d54 VPADDD	%ZMM24,%ZMM1,%ZMM6{%K2}

  (234) 0x434d5a KNOTW	%K2,%K5

  (234) 0x434d5e KMOVB	%K1,%K4

  (234) 0x434d62 VPMOVSXDQ	%YMM9,%ZMM3{%K3}

  (234) 0x434d68 KMOVB	%K1,%K2

  (234) 0x434d6c VMOVDQA64	%ZMM5,%ZMM14{%K3}

  (234) 0x434d72 VPADDD	%ZMM16,%ZMM1,%ZMM13{%K5}

  (234) 0x434d78 VGATHERQPD	(%RDX,%ZMM20,8),%ZMM8{%K6}

  (234) 0x434d7f KMOVB	%K1,%K3

  (234) 0x434d83 KMOVB	%K1,%K5

  (234) 0x434d87 VGATHERDPD	(%RDX,%YMM6,8),%ZMM2{%K4}

  (234) 0x434d8e VSHUFI32X4	$-0x12,%ZMM6,%ZMM6,%ZMM1

  (234) 0x434d95 VGATHERQPD	(%RDX,%ZMM21,8),%ZMM6{%K2}

  (234) 0x434d9c VGATHERQPD	(%RDX,%ZMM3,8),%ZMM7{%K7}

  (234) 0x434da3 VSUBPD	%ZMM2,%ZMM8,%ZMM9

  (234) 0x434da9 VSUBPD	%ZMM8,%ZMM6,%ZMM4

  (234) 0x434daf VGATHERDPD	(%RDX,%YMM1,8),%ZMM5{%K3}

  (234) 0x434db6 VGATHERQPD	(%RDX,%ZMM14,8),%ZMM21{%K5}

  (234) 0x434dbd VMOVAPD	%ZMM0,%ZMM6

  (234) 0x434dc3 VSUBPD	%ZMM7,%ZMM21,%ZMM2

  (234) 0x434dc9 VSUBPD	%ZMM5,%ZMM7,%ZMM12

  (234) 0x434dcf VMULPD	%ZMM4,%ZMM9,%ZMM14

  (234) 0x434dd5 VANDPD	%ZMM11,%ZMM4,%ZMM21

  (234) 0x434ddb VANDPD	%ZMM11,%ZMM9,%ZMM9

  (234) 0x434de1 VMULPD	%ZMM2,%ZMM12,%ZMM1

  (234) 0x434de7 VANDPD	%ZMM11,%ZMM12,%ZMM12

  (234) 0x434ded VCMPPD	$0xe,%ZMM0,%ZMM14,%K3

  (234) 0x434df4 VANDPD	%ZMM11,%ZMM2,%ZMM14

  (234) 0x434dfa VMOVUPD	(%RAX),%ZMM28{%K3}

  (234) 0x434e00 VCMPPD	$0xe,%ZMM0,%ZMM1,%K2

  (234) 0x434e07 VMOVUPD	0x40(%RAX),%ZMM27{%K2}

  (234) 0x434e0e KMOVB	%K3,%K4

  (234) 0x434e12 VCMPPD	$0xe,%ZMM0,%ZMM4,%K7{%K3}

  (234) 0x434e19 KMOVB	%K2,%K5

  (234) 0x434e1d VCMPPD	$0xe,%ZMM0,%ZMM2,%K6{%K2}

  (234) 0x434e24 VANDPD	%ZMM11,%ZMM22,%ZMM2

  (234) 0x434e2a VGATHERQPD	(%R9,%ZMM20,8),%ZMM6{%K4}

  (234) 0x434e31 VMOVAPD	%ZMM0,%ZMM20

  (234) 0x434e37 VGATHERQPD	(%R9,%ZMM3,8),%ZMM20{%K5}

  (234) 0x434e3e VANDPD	%ZMM11,%ZMM23,%ZMM3

  (234) 0x434e44 VDIVPD	%ZMM6,%ZMM3,%ZMM4

  (234) 0x434e4a VMOVAPD	%ZMM0,%ZMM6

  (234) 0x434e50 VBLENDMPD	%ZMM10,%ZMM19,%ZMM1{%K7}

  (234) 0x434e56 KMOVB	%K2,%K7

  (234) 0x434e5a VBLENDMPD	%ZMM10,%ZMM19,%ZMM5{%K6}

  (234) 0x434e60 KMOVB	%K3,%K6

  (234) 0x434e64 VDIVPD	%ZMM20,%ZMM2,%ZMM3

  (234) 0x434e6a VMOVAPD	%ZMM0,%ZMM2

  (234) 0x434e70 VGATHERDPD	(%RCX,%YMM13,8),%ZMM2{%K6}

  (234) 0x434e77 VSHUFI32X4	$-0x12,%ZMM13,%ZMM13,%ZMM13

  (234) 0x434e7e VGATHERDPD	(%RCX,%YMM13,8),%ZMM6{%K7}

  (234) 0x434e85 VSUBPD	%ZMM3,%ZMM18,%ZMM20

  (234) 0x434e8b VADDPD	%ZMM10,%ZMM3,%ZMM13

  (234) 0x434e91 VSUBPD	%ZMM3,%ZMM10,%ZMM3

  (234) 0x434e97 VMULPD	%ZMM12,%ZMM13,%ZMM13

  (234) 0x434e9d VMULPD	%ZMM14,%ZMM20,%ZMM20

  (234) 0x434ea3 VMINPD	%ZMM14,%ZMM12,%ZMM12

  (234) 0x434ea9 VMULPD	%ZMM5,%ZMM3,%ZMM5

  (234) 0x434eaf VADDPD	%ZMM10,%ZMM4,%ZMM3

  (234) 0x434eb5 VDIVPD	%ZMM27,%ZMM20,%ZMM20

  (234) 0x434ebb VDIVPD	%ZMM6,%ZMM13,%ZMM6

  (234) 0x434ec1 VADDPD	%ZMM6,%ZMM20,%ZMM13

  (234) 0x434ec7 VMULPD	%ZMM17,%ZMM27,%ZMM20

  (234) 0x434ecd VSUBPD	%ZMM4,%ZMM18,%ZMM6

  (234) 0x434ed3 VSUBPD	%ZMM4,%ZMM10,%ZMM4

  (234) 0x434ed9 VMULPD	%ZMM20,%ZMM13,%ZMM20

  (234) 0x434edf VMULPD	%ZMM21,%ZMM6,%ZMM13

  (234) 0x434ee5 VMINPD	%ZMM21,%ZMM9,%ZMM21

  (234) 0x434eeb VMULPD	%ZMM9,%ZMM3,%ZMM6

  (234) 0x434ef1 VMULPD	%ZMM1,%ZMM4,%ZMM1

  (234) 0x434ef7 VMINPD	%ZMM12,%ZMM20,%ZMM14

  (234) 0x434efd VDIVPD	%ZMM28,%ZMM13,%ZMM12

  (234) 0x434f03 VFMADD231PD	%ZMM5,%ZMM14,%ZMM7{%K2}

  (234) 0x434f09 VMULPD	%ZMM22,%ZMM7,%ZMM7

  (234) 0x434f0f VDIVPD	%ZMM2,%ZMM6,%ZMM2

  (234) 0x434f15 VMOVUPD	%ZMM7,0x40(%R13,%RAX,1)

  (234) 0x434f1d VADDPD	%ZMM2,%ZMM12,%ZMM13

  (234) 0x434f23 VMULPD	%ZMM17,%ZMM28,%ZMM12

  (234) 0x434f29 VMULPD	%ZMM12,%ZMM13,%ZMM3

  (234) 0x434f2f VMINPD	%ZMM21,%ZMM3,%ZMM9

  (234) 0x434f35 VFMADD231PD	%ZMM1,%ZMM9,%ZMM8{%K3}

  (234) 0x434f3b VMULPD	%ZMM23,%ZMM8,%ZMM8

  (234) 0x434f41 VMOVUPD	%ZMM8,(%R13,%RAX,1)

  (234) 0x434f49 SUB	$-0x80,%RAX

  (234) 0x434f4d CMP	%RAX,%R11

  (234) 0x434f50 JNE	434cd0

(232) 0x434f56 MOV	0xc0(%RSP),%EAX

(232) 0x434f5d MOV	%R10D,%EDX

(232) 0x434f60 VMOVAPD	0x80(%RSP),%YMM20

(232) 0x434f68 VMOVAPD	0x60(%RSP),%YMM14

(232) 0x434f6e AND	$-0x10,%EDX

(232) 0x434f71 VMOVQ	%R14,%XMM2

(232) 0x434f76 ADD	%EDX,%R15D

(232) 0x434f79 ADD	%EDX,%EAX

(232) 0x434f7b TEST	$0xf,%R10B

(232) 0x434f7f JE	435498

(232) 0x434f85 SUB	%EDX,%R10D

(232) 0x434f88 LEA	-0x1(%R10),%R9D

(232) 0x434f8c CMP	$0x6,%R9D

(232) 0x434f90 JBE	4352c3

(232) 0x434f96 MOVSXD	0xc0(%RSP),%R8

(232) 0x434f9e MOV	0xa0(%RSP),%R11

(232) 0x434fa6 MOV	0x140(%RSP),%R13

(232) 0x434fae VXORPD	%XMM4,%XMM4,%XMM4

(232) 0x434fb2 VPBROADCASTD	%EAX,%YMM19

(232) 0x434fb8 VPADDD	0x2f6fe(%RIP),%YMM19,%YMM11

(232) 0x434fc2 VPADDD	0x2f6b4(%RIP),%YMM19,%YMM1

(232) 0x434fcc KMOVB	0x2f728(%RIP),%K0

(232) 0x434fd4 VPADDD	%YMM31,%YMM19,%YMM0

(232) 0x434fda VMOVAPD	%YMM4,%YMM22

(232) 0x434fe0 VBROADCASTSD	0x2e596(%RIP),%YMM18

(232) 0x434fea VMOVQ	%XMM2,%R9

(232) 0x434fef VMOVAPD	%YMM4,%YMM23

(232) 0x434ff5 VMOVAPD	%YMM4,%YMM21

(232) 0x434ffb LEA	(%R11,%R8,1),%RSI

(232) 0x434fff MOV	0x178(%RSP),%R11

(232) 0x435007 ADD	%RDX,%RSI

(232) 0x43500a LEA	(%R13,%RSI,8),%R14

(232) 0x43500f VPMOVSXDQ	%XMM11,%YMM5

(232) 0x435014 VMOVDQA	%XMM1,%XMM12

(232) 0x435018 VEXTRACTI32X4	$0x1,%YMM11,%XMM10

(232) 0x43501f VMOVUPD	(%R14),%YMM15

(232) 0x435024 VMOVUPD	0x20(%R14),%YMM13

(232) 0x43502a VPMOVSXDQ	%XMM10,%YMM6

(232) 0x43502f VPMOVSXDQ	%XMM1,%YMM8

(232) 0x435034 VMOVDQA64	%YMM5,%YMM26

(232) 0x43503a VEXTRACTI32X4	$0x1,%YMM1,%XMM9

(232) 0x435041 LEA	(%R9,%RDI,8),%R13

(232) 0x435045 MOV	0x100(%RSP),%RSI

(232) 0x43504d VPMOVSXDQ	%XMM9,%YMM3

(232) 0x435052 VMOVDQA64	%YMM6,%YMM25

(232) 0x435058 LEA	(%R8,%RDX,1),%R9

(232) 0x43505c LEA	(%RCX,%R9,8),%R9

(232) 0x435060 VCMPPD	$0x1,%YMM4,%YMM15,%K3

(232) 0x435067 VCMPPD	$0x1,%YMM4,%YMM13,%K2

(232) 0x43506e LEA	(%R11,%RSI,8),%R11

(232) 0x435072 MOV	0x168(%RSP),%RSI

(232) 0x43507a KANDB	%K0,%K3,%K1

(232) 0x43507e KSHIFTLB	$0x4,%K2,%K4

(232) 0x435084 VPMOVSXDQ	%XMM12,%YMM26{%K3}

(232) 0x43508a VMOVDQA64	%YMM5,%YMM8{%K3}

(232) 0x435090 KORB	%K4,%K1,%K5

(232) 0x435094 VPADDD	0x2f662(%RIP),%YMM19,%YMM0{%K5}

(232) 0x43509e KXNORB	%K3,%K3,%K3

(232) 0x4350a2 VPMOVSXDQ	%XMM9,%YMM25{%K2}

(232) 0x4350a8 KMOVB	%K3,%K7

(232) 0x4350ac VMOVDQA64	%YMM6,%YMM3{%K2}

(232) 0x4350b2 KNOTB	%K5,%K6

(232) 0x4350b6 ADD	%RSI,%R8

(232) 0x4350b9 KMOVB	%K3,%K2

(232) 0x4350bd KMOVB	%K3,%K1

(232) 0x4350c1 VPADDD	%YMM31,%YMM19,%YMM1{%K6}

(232) 0x4350c7 ADD	%RDX,%R8

(232) 0x4350ca KMOVB	%K3,%K4

(232) 0x4350ce KMOVB	%K3,%K5

(232) 0x4350d2 VGATHERQPD	(%R13,%YMM26,8),%YMM5{%K7}

(232) 0x4350da MOV	0x170(%RSP),%RDX

(232) 0x4350e2 VGATHERQPD	(%R13,%YMM25,8),%YMM11{%K2}

(232) 0x4350ea VPERM2I128	$0x11,%YMM0,%YMM0,%YMM6

(232) 0x4350f0 VGATHERDPD	(%R13,%XMM0,8),%YMM10{%K1}

(232) 0x4350f8 VGATHERQPD	(%R13,%YMM8,8),%YMM0{%K5}

(232) 0x435100 VGATHERQPD	(%R13,%YMM3,8),%YMM8{%K3}

(232) 0x435108 VGATHERDPD	(%R13,%XMM6,8),%YMM12{%K4}

(232) 0x435110 VSUBPD	%YMM10,%YMM5,%YMM9

(232) 0x435115 VSUBPD	%YMM11,%YMM8,%YMM10

(232) 0x43511a VBROADCASTSD	0x2eb0d(%RIP),%YMM8

(232) 0x435123 VSUBPD	%YMM12,%YMM11,%YMM7

(232) 0x435128 VSUBPD	%YMM5,%YMM0,%YMM6

(232) 0x43512c LEA	(%RDX,%R8,8),%R8

(232) 0x435130 VMULPD	%YMM10,%YMM7,%YMM12

(232) 0x435135 VMULPD	%YMM6,%YMM9,%YMM3

(232) 0x435139 VANDPD	%YMM8,%YMM10,%YMM17

(232) 0x43513f VANDPD	%YMM8,%YMM6,%YMM16

(232) 0x435145 VANDPD	%YMM8,%YMM15,%YMM0

(232) 0x43514a VANDPD	%YMM8,%YMM9,%YMM9

(232) 0x43514f VCMPPD	$0xe,%YMM4,%YMM12,%K2

(232) 0x435156 VCMPPD	$0xe,%YMM4,%YMM3,%K6

(232) 0x43515d VANDPD	%YMM8,%YMM13,%YMM3

(232) 0x435162 VANDPD	%YMM8,%YMM7,%YMM7

(232) 0x435167 VBROADCASTSD	0x2f3c8(%RIP),%YMM8

(232) 0x435170 KMOVB	%K2,%K4

(232) 0x435174 VCMPPD	$0xe,%YMM4,%YMM6,%K7{%K6}

(232) 0x43517b VBROADCASTSD	0x2e80c(%RIP),%YMM6

(232) 0x435184 VCMPPD	$0xe,%YMM4,%YMM10,%K3{%K2}

(232) 0x43518b KMOVB	%K6,%K1

(232) 0x43518f KMOVB	%K2,%R13D

(232) 0x435193 KMOVB	%K6,%R14D

(232) 0x435197 VGATHERQPD	(%R11,%YMM25,8),%YMM22{%K4}

(232) 0x43519e VGATHERDPD	(%RCX,%XMM1,8),%YMM21{%K6}

(232) 0x4351a5 VDIVPD	%YMM22,%YMM3,%YMM12

(232) 0x4351ab VGATHERQPD	(%R11,%YMM26,8),%YMM23{%K1}

(232) 0x4351b2 VPERM2I128	$0x11,%YMM1,%YMM1,%YMM1

(232) 0x4351b8 MOV	%R10D,%R11D

(232) 0x4351bb AND	$0xf,%R13D

(232) 0x4351bf VGATHERDPD	(%RCX,%XMM1,8),%YMM4{%K2}

(232) 0x4351c6 AND	$0xf,%R14D

(232) 0x4351ca AND	$-0x8,%R11D

(232) 0x4351ce KMOVB	%R14D,%K5

(232) 0x4351d3 VMOVUPD	(%R9),%YMM20{%K5}

(232) 0x4351d9 ADD	%R11D,%EAX

(232) 0x4351dc ADD	%R11D,%R15D

(232) 0x4351df VBLENDMPD	%YMM6,%YMM18,%YMM24{%K7}

(232) 0x4351e5 VMOVAPD	%YMM6,%YMM18{%K3}

(232) 0x4351eb AND	$0x7,%R10D

(232) 0x4351ef KMOVB	%R13D,%K3

(232) 0x4351f4 VMOVUPD	0x20(%R9),%YMM14{%K3}

(232) 0x4351fb VDIVPD	%YMM23,%YMM0,%YMM10

(232) 0x435201 VSUBPD	%YMM12,%YMM8,%YMM26

(232) 0x435207 VADDPD	%YMM6,%YMM12,%YMM23

(232) 0x43520d VSUBPD	%YMM12,%YMM6,%YMM12

(232) 0x435212 VMULPD	%YMM17,%YMM26,%YMM25

(232) 0x435218 VMULPD	%YMM7,%YMM23,%YMM19

(232) 0x43521e VBROADCASTSD	0x2f480(%RIP),%YMM26

(232) 0x435228 VMINPD	%YMM17,%YMM7,%YMM7

(232) 0x43522e VSUBPD	%YMM10,%YMM8,%YMM8

(232) 0x435233 VDIVPD	%YMM14,%YMM25,%YMM22

(232) 0x435239 VMULPD	%YMM26,%YMM14,%YMM25

(232) 0x43523f VMULPD	%YMM26,%YMM20,%YMM17

(232) 0x435245 VDIVPD	%YMM4,%YMM19,%YMM4

(232) 0x43524b VADDPD	%YMM4,%YMM22,%YMM0

(232) 0x435251 VSUBPD	%YMM10,%YMM6,%YMM4

(232) 0x435256 VADDPD	%YMM6,%YMM10,%YMM6

(232) 0x43525a VMULPD	%YMM25,%YMM0,%YMM3

(232) 0x435260 VMULPD	%YMM16,%YMM8,%YMM0

(232) 0x435266 VMULPD	%YMM9,%YMM6,%YMM10

(232) 0x43526b VMINPD	%YMM16,%YMM9,%YMM9

(232) 0x435271 VMINPD	%YMM7,%YMM3,%YMM1

(232) 0x435275 VMULPD	%YMM18,%YMM12,%YMM3

(232) 0x43527b VMULPD	%YMM24,%YMM4,%YMM7

(232) 0x435281 VDIVPD	%YMM20,%YMM0,%YMM12

(232) 0x435287 VFMADD231PD	%YMM1,%YMM3,%YMM11{%K3}

(232) 0x43528d VDIVPD	%YMM21,%YMM10,%YMM4

(232) 0x435293 VMULPD	%YMM13,%YMM11,%YMM13

(232) 0x435298 VMOVUPD	%YMM13,0x20(%R8)

(232) 0x43529e VADDPD	%YMM4,%YMM12,%YMM8

(232) 0x4352a2 VMULPD	%YMM17,%YMM8,%YMM0

(232) 0x4352a8 VMINPD	%YMM9,%YMM0,%YMM12

(232) 0x4352ad VFMADD231PD	%YMM12,%YMM7,%YMM5{%K5}

(232) 0x4352b3 VMULPD	%YMM15,%YMM5,%YMM15

(232) 0x4352b8 VMOVUPD	%YMM15,(%R8)

(232) 0x4352bd JE	435498

(232) 0x4352c3 MOV	0xa0(%RSP),%RSI

(232) 0x4352cb MOV	0x140(%RSP),%R9

(232) 0x4352d3 MOV	0x170(%RSP),%R14

(232) 0x4352db MOV	0x168(%RSP),%R13

(232) 0x4352e3 LEA	0x1(%RAX),%R10D

(232) 0x4352e7 MOV	%R12,0xc0(%RSP)

(232) 0x4352ef DEC	%R15D

(232) 0x4352f2 VXORPD	%XMM7,%XMM7,%XMM7

(232) 0x4352f6 MOVSXD	%R10D,%RDX

(232) 0x4352f9 VMOVSD	0x2f237(%RIP),%XMM9

(232) 0x435301 VMOVSD	0x2f39f(%RIP),%XMM8

(232) 0x435309 LEA	(%R9,%RSI,8),%R8

(232) 0x43530d LEA	(%R14,%R13,8),%R10

(232) 0x435311 VMOVQ	%XMM2,%RSI

(232) 0x435316 MOV	%RCX,%R14

(232) 0x435319 MOV	%R8,%R12

(232) 0x43531c JMP	435420

0x435321 NOPW	%CS:(%RAX,%RAX,1)

0x43532c NOPL	(%RAX)

  (233) 0x435330 LEA	-0x2(%RDX),%R8D

  (233) 0x435334 MOV	%RDX,%R13

  (233) 0x435337 MOVSXD	%R8D,%RCX

  (233) 0x43533a MOVSXD	%R8D,%R8

  (233) 0x43533d LEA	(%RDI,%R9,1),%R11

  (233) 0x435341 LEA	(%RDI,%R13,1),%R13

  (233) 0x435345 ADD	%RDI,%R8

  (233) 0x435348 VMOVSD	(%RSI,%R11,8),%XMM10

  (233) 0x43534e VMOVSD	(%RSI,%R13,8),%XMM11

  (233) 0x435354 VSUBSD	%XMM10,%XMM11,%XMM1

  (233) 0x435359 VSUBSD	(%RSI,%R8,8),%XMM10,%XMM5

  (233) 0x43535f VMULSD	%XMM1,%XMM5,%XMM3

  (233) 0x435363 VCOMISD	%XMM7,%XMM3

  (233) 0x435367 JBE	435403

  (233) 0x43536d VANDPD	%XMM29,%XMM5,%XMM6

  (233) 0x435373 VANDPD	%XMM29,%XMM1,%XMM24

  (233) 0x435379 VCOMISD	%XMM1,%XMM7

  (233) 0x43537d JAE	435470

  (233) 0x435383 VMOVAPD	%XMM30,%XMM16

  (233) 0x435389 VMOVAPD	%XMM30,%XMM12

  (233) 0x43538f MOV	0x100(%RSP),%R11

  (233) 0x435397 MOV	0x178(%RSP),%R8

  (233) 0x43539f VANDPD	%XMM29,%XMM2,%XMM4

  (233) 0x4353a5 VMOVSD	-0x8(%R14,%RDX,8),%XMM21

  (233) 0x4353ad VMINSD	%XMM24,%XMM6,%XMM3

  (233) 0x4353b3 VMULSD	%XMM8,%XMM21,%XMM19

  (233) 0x4353b9 ADD	%R11,%R9

  (233) 0x4353bc VDIVSD	(%R8,%R9,8),%XMM4,%XMM15

  (233) 0x4353c2 VADDSD	%XMM16,%XMM15,%XMM0

  (233) 0x4353c8 VSUBSD	%XMM15,%XMM9,%XMM18

  (233) 0x4353ce VMULSD	%XMM6,%XMM0,%XMM13

  (233) 0x4353d2 VMULSD	%XMM24,%XMM18,%XMM22

  (233) 0x4353d8 VDIVSD	(%R14,%RCX,8),%XMM13,%XMM5

  (233) 0x4353de VDIVSD	%XMM21,%XMM22,%XMM23

  (233) 0x4353e4 VSUBSD	%XMM15,%XMM16,%XMM4

  (233) 0x4353ea VADDSD	%XMM23,%XMM5,%XMM11

  (233) 0x4353f0 VMULSD	%XMM19,%XMM11,%XMM1

  (233) 0x4353f6 VMINSD	%XMM3,%XMM1,%XMM6

  (233) 0x4353fa VMULSD	%XMM4,%XMM6,%XMM15

  (233) 0x4353fe VFMADD231SD	%XMM12,%XMM15,%XMM10

  (233) 0x435403 VMULSD	%XMM10,%XMM2,%XMM2

  (233) 0x435408 VMOVSD	%XMM2,-0x8(%R10,%RDX,8)

  (233) 0x43540f INC	%RDX

  (233) 0x435412 MOV	%EDX,%R9D

  (233) 0x435415 SUB	%EAX,%R9D

  (233) 0x435418 ADD	%R15D,%R9D

  (233) 0x43541b CMP	%EBX,%R9D

  (233) 0x43541e JAE	435490

  (233) 0x435420 VMOVSD	-0x8(%R12,%RDX,8),%XMM2

  (233) 0x435427 LEA	-0x1(%RDX),%R9

  (233) 0x43542b VCOMISD	%XMM2,%XMM7

  (233) 0x43542f JBE	435330

  (233) 0x435435 MOV	%R9,%R13

  (233) 0x435438 MOVSXD	%EDX,%RCX

  (233) 0x43543b LEA	0x1(%RDX),%R8D

  (233) 0x43543f MOV	%RDX,%R9

  (233) 0x435442 JMP	43533a

0x435447 NOPW	(%RAX,%RAX,1)

0x435450 VZEROUPPER

0x435453 LEA	-0x28(%RBP),%RSP

0x435457 POP	%RBX

0x435458 POP	%R12

0x43545a POP	%R13

0x43545c POP	%R14

0x43545e POP	%R15

0x435460 POP	%RBP

0x435461 RET

0x435462 NOPW	%CS:(%RAX,%RAX,1)

0x43546d NOPL	(%RAX)

  (233) 0x435470 VMOVSD	0x2e108(%RIP),%XMM12

  (233) 0x435478 VMOVSD	0x2e50e(%RIP),%XMM16

  (233) 0x435482 JMP	43538f

0x435487 NOPW	(%RAX,%RAX,1)

(232) 0x435490 MOV	0xc0(%RSP),%R12

(232) 0x435498 MOV	%EBX,%R15D

(232) 0x43549b INC	%R12

(232) 0x43549e CMP	%R12D,0x164(%RSP)

(232) 0x4354a6 JLE	435450

(232) 0x4354a8 MOV	0x58(%RSP),%ECX

(232) 0x4354ac MOV	0x160(%RSP),%EAX

(232) 0x4354b3 MOV	0x5c(%RSP),%R13D

(232) 0x4354b8 SUB	%R15D,%ECX

(232) 0x4354bb MOV	%EAX,0xc0(%RSP)

(232) 0x4354c2 JMP	434b50

0x4354c7 NOPW	(%RAX,%RAX,1)

(232) 0x4354d0 MOV	0xc0(%RSP),%EAX

(232) 0x4354d7 XOR	%EDX,%EDX

(232) 0x4354d9 JMP	434f85

0x4354de INC	%ECX

0x4354e0 XOR	%EDX,%EDX

0x4354e2 JMP	434a9c

0x4354e7 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.64+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.38 to 5.00 cycles (2.47x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 23% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 12.38 to 8.68 cycles (1.43x speedup).

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

31% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
36% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:114
VMOVAPD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 308 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	102
nb uops	99
loop length	492
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	5
used zmm registers	2
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.38 cycles
front end	12.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	5.00	5.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	5.00	5.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.38
Dispatch	9.00
DIV/SQRT	12.00
Overall L1	12.38

Vectorization ratios

INT

all	8%
load	9%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	90%
load	80%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	28%
load	31%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	36%

Vector efficiency ratios

INT

all	10%
load	13%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	64%
load	62%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	23%
load	28%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.38 cycles. At this rate:

9% of peak load performance is reached (24.89 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (20.69 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4349c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x180,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV 0x2c(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVAPD %YMM3,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPD %YMM4,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPD %ZMM27,0xc0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	1	4	1	vect (100.0%)
VMOVAPD %ZMM28,0x100(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	1	4	1	vect (100.0%)
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %EDX,0x164(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 435450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x3(%RBX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R12D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 435450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDI,0x178(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
SUB %ESI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,0x5c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVAPD 0x100(%RSP),%ZMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD 0xc0(%RSP),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x140(%RSP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVAPD 0xa0(%RSP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
MOV 0x178(%RSP),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 4354de <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0xb1e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%R15,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R10D,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R10D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 435450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x160(%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
VMOVQ 0x8(%R14),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
DIVL 0x5c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ 0x10(%R14),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ (%R14),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
VMOVQ 0x18(%R14),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDQA32 0x2fb50(%RIP),%YMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM4,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVQ 0x2f12c(%RIP),%XMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x2ee82(%RIP),%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM23,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOV %RSI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM24,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM25,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM26,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB %R11D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R11D,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 434a9c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0xdc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:108-139
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:108-139

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.38 to 5.00 cycles (2.47x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

28% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

31% of SSE/AVX loads are used in vector version.
26% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
36% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:114
VMOVAPD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 308 bytes. The binary function is storing 256 bytes.

General properties

nb instructions	102
nb uops	99
loop length	492
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	5
used zmm registers	2
nb stack references	15

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	12.38 cycles
front end	12.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	5.00	5.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	9.00	9.00	9.00	9.00	0.00	0.00	0.00	0.00	5.00	5.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	12.38
Dispatch	9.00
DIV/SQRT	12.00
Overall L1	12.38

Vectorization ratios

INT

all	8%
load	9%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	90%
load	80%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	28%
load	31%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	36%

Vector efficiency ratios

INT

all	10%
load	13%
store	9%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	64%
load	62%
store	75%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	50%

INT+FP

all	23%
load	28%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.38 cycles. At this rate:

9% of peak load performance is reached (24.89 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (20.69 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the function is: 4349c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x180,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x34(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x28(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV 0x2c(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
VMOVAPD %YMM3,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPD %YMM4,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	4	0.50	vect (50.0%)
VMOVAPD %ZMM27,0xc0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	1	4	1	vect (100.0%)
VMOVAPD %ZMM28,0x100(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	1	4	1	vect (100.0%)
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %EDX,0x164(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 435450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x3(%RBX),%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R12D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 435450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %EDI,0x178(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
SUB %ESI,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV %R15D,0x5c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
VMOVAPD 0x100(%RSP),%ZMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVAPD 0xc0(%RSP),%ZMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (100.0%)
VMOVAPD 0x140(%RSP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
VMOVAPD 0xa0(%RSP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
MOV 0x178(%RSP),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 4354de <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0xb1e>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %ECX,%R8D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%R8,%RDX,1),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA (%RCX,%R15,1),%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R10D,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R10D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 435450 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0xa90>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x160(%RSP),%R11D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
VMOVQ 0x8(%R14),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
DIVL 0x5c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ 0x10(%R14),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ (%R14),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV 0x20(%R14),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (12.5%)
VMOVQ 0x18(%R14),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDQA32 0x2fb50(%RIP),%YMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.50	vect (50.0%)
VMOVAPD %YMM4,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVQ 0x2f12c(%RIP),%XMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x2ee82(%RIP),%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM23,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
MOV %RSI,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM24,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM25,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM26,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	1	0.50	scal (12.5%)
ADD %EDX,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R12D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB %R11D,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R11D,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R9D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 434a9c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.6+0xdc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.66	1.34
▼Loop 232 - advec_mom.cpp:110-139 - exec–	0.01	0.01
○Loop 234 - advec_mom.cpp:114-139 - exec	3.65	1.34
○Loop 233 - advec_mom.cpp:114-139 - exec	0.00	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code