OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:218-221 [...]	Coverage (incl. loops): 4.36% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 218 - 221

--------------------------------------------------------------------------------

218: #pragma omp parallel for simd collapse(2)

219:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

220:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

221:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i + 0, j - 1) - mom_flux(i, j)) / node_mass_post(i, j);

0x434470 PUSH	%RBP

0x434471 MOV	%RSP,%RBP

0x434474 PUSH	%R15

0x434476 PUSH	%R14

0x434478 PUSH	%R13

0x43447a PUSH	%R12

0x43447c PUSH	%RBX

0x43447d AND	$-0x40,%RSP

0x434481 SUB	$0x40,%RSP

0x434485 MOV	0x28(%RDI),%EAX

0x434488 MOV	0x2c(%RDI),%EDX

0x43448b MOV	0x20(%RDI),%EBX

0x43448e MOV	0x24(%RDI),%ECX

0x434491 ADD	$0x3,%EDX

0x434494 INC	%EBX

0x434496 LEA	0x1(%RAX),%R15D

0x43449a MOV	%EDX,0x18(%RSP)

0x43449e MOV	%EBX,0x14(%RSP)

0x4344a2 CMP	%EDX,%R15D

0x4344a5 JGE	434983

0x4344ab MOV	%EDX,%R12D

0x4344ae LEA	0x3(%RCX),%R13D

0x4344b2 SUB	%R15D,%R12D

0x4344b5 CMP	%R13D,%EBX

0x4344b8 JGE	434983

0x4344be MOV	%R13D,%ESI

0x4344c1 MOV	%RDI,%R14

0x4344c4 SUB	%EBX,%ESI

0x4344c6 MOV	%ESI,0x1c(%RSP)

0x4344ca CALL	404630 <omp_get_num_threads@plt>

0x4344cf MOV	%EAX,%EBX

0x4344d1 CALL	404520 <omp_get_thread_num@plt>

0x4344d6 MOV	0x1c(%RSP),%EDI

0x4344da XOR	%EDX,%EDX

0x4344dc MOV	%EAX,%ECX

0x4344de IMUL	%EDI,%R12D

0x4344e2 MOV	%R12D,%EAX

0x4344e5 DIV	%EBX

0x4344e7 MOV	%EAX,%R8D

0x4344ea CMP	%EDX,%ECX

0x4344ec JB	4349ac

0x4344f2 IMUL	%R8D,%ECX

0x4344f6 ADD	%EDX,%ECX

0x4344f8 LEA	(%R8,%RCX,1),%R9D

0x4344fc MOV	%R9D,0x10(%RSP)

0x434501 CMP	%R9D,%ECX

0x434504 JAE	434983

0x43450a MOV	%ECX,%EAX

0x43450c XOR	%EDX,%EDX

0x43450e MOV	0x14(%RSP),%R10D

0x434513 VMOVQ	(%R14),%XMM11

0x434518 DIVL	0x1c(%RSP)

0x43451c VMOVQ	0x10(%R14),%XMM10

0x434522 VMOVQ	0x18(%R14),%XMM9

0x434528 VMOVQ	0x8(%R14),%XMM8

0x43452e ADD	%EDX,%R10D

0x434531 ADD	%R15D,%EAX

0x434534 MOVSXD	%EAX,%RBX

0x434537 SUB	%R10D,%R13D

0x43453a MOV	%R8D,%EAX

0x43453d MOV	%R10D,0x3c(%RSP)

0x434542 NOPW	%CS:(%RAX,%RAX,1)

0x43454d NOPL	(%RAX)

(230) 0x434550 CMP	%R13D,%EAX

(230) 0x434553 CMOVA	%R13D,%EAX

(230) 0x434557 LEA	(%RCX,%RAX,1),%R11D

(230) 0x43455b MOV	%R11D,0x38(%RSP)

(230) 0x434560 CMP	%R11D,%ECX

(230) 0x434563 JAE	434951

(230) 0x434569 VMOVQ	%XMM11,%R13

(230) 0x43456e VMOVQ	%XMM10,%R15

(230) 0x434573 LEA	-0x1(%RBX),%EDI

(230) 0x434576 LEA	-0x1(%RAX),%EDX

(230) 0x434579 VMOVQ	%XMM8,%R9

(230) 0x43457e MOV	(%R13),%R14

(230) 0x434582 VMOVQ	0x10(%R13),%XMM1

(230) 0x434588 MOV	(%R15),%R10

(230) 0x43458b MOV	(%R9),%R13

(230) 0x43458e VMOVQ	%XMM9,%RSI

(230) 0x434593 MOVSXD	%EDI,%RDI

(230) 0x434596 VMOVQ	0x10(%R15),%XMM6

(230) 0x43459c MOV	(%RSI),%R8

(230) 0x43459f VMOVQ	0x10(%R9),%XMM5

(230) 0x4345a5 MOV	0x10(%RSI),%R12

(230) 0x4345a9 IMUL	%RBX,%R14

(230) 0x4345ad IMUL	%RBX,%R10

(230) 0x4345b1 IMUL	%RBX,%R13

(230) 0x4345b5 IMUL	%R8,%RDI

(230) 0x4345b9 MOV	%R14,0x20(%RSP)

(230) 0x4345be IMUL	%RBX,%R8

(230) 0x4345c2 MOV	%R10,0x28(%RSP)

(230) 0x4345c7 MOV	%R13,0x30(%RSP)

(230) 0x4345cc CMP	$0x6,%EDX

(230) 0x4345cf JBE	4349a0

(230) 0x4345d5 MOVSXD	0x3c(%RSP),%R15

(230) 0x4345da VMOVQ	%XMM6,%RDX

(230) 0x4345df LEA	(%R14,%R15,1),%R11

(230) 0x4345e3 LEA	(%RDI,%R15,1),%R9

(230) 0x4345e7 LEA	(%R8,%R15,1),%RSI

(230) 0x4345eb LEA	(%R10,%R15,1),%R10

(230) 0x4345ef ADD	%R13,%R15

(230) 0x4345f2 VMOVQ	%XMM5,%R13

(230) 0x4345f7 LEA	(%RDX,%R10,8),%R10

(230) 0x4345fb LEA	(%R12,%R9,8),%RDX

(230) 0x4345ff LEA	(%R13,%R15,8),%R15

(230) 0x434604 MOV	%EAX,%R13D

(230) 0x434607 VMOVQ	%XMM1,%R14

(230) 0x43460c SHR	$0x3,%R13D

(230) 0x434610 SAL	$0x6,%R13

(230) 0x434614 LEA	-0x40(%R13),%R9

(230) 0x434618 LEA	(%R14,%R11,8),%R14

(230) 0x43461c LEA	(%R12,%RSI,8),%R11

(230) 0x434620 XOR	%ESI,%ESI

(230) 0x434622 SHR	$0x6,%R9

(230) 0x434626 INC	%R9

(230) 0x434629 AND	$0x3,%R9D

(230) 0x43462d JE	4346cd

(230) 0x434633 CMP	$0x1,%R9

(230) 0x434637 JE	434696

(230) 0x434639 CMP	$0x2,%R9

(230) 0x43463d JE	434668

(230) 0x43463f VMOVUPD	(%R10),%ZMM0

(230) 0x434645 VMOVUPD	(%R11),%ZMM3

(230) 0x43464b VFMSUB132PD	(%R14),%ZMM3,%ZMM0

(230) 0x434651 VADDPD	(%RDX),%ZMM0,%ZMM2

(230) 0x434657 VDIVPD	(%R15),%ZMM2,%ZMM4

(230) 0x43465d MOV	$0x40,%ESI

(230) 0x434662 VMOVUPD	%ZMM4,(%R14)

(230) 0x434668 VMOVUPD	(%R10,%RSI,1),%ZMM12

(230) 0x43466f VMOVUPD	(%R11,%RSI,1),%ZMM7

(230) 0x434676 VFMSUB132PD	(%R14,%RSI,1),%ZMM7,%ZMM12

(230) 0x43467d VADDPD	(%RDX,%RSI,1),%ZMM12,%ZMM13

(230) 0x434684 VDIVPD	(%R15,%RSI,1),%ZMM13,%ZMM14

(230) 0x43468b VMOVUPD	%ZMM14,(%R14,%RSI,1)

(230) 0x434692 ADD	$0x40,%RSI

(230) 0x434696 VMOVUPD	(%R10,%RSI,1),%ZMM15

(230) 0x43469d VMOVUPD	(%R11,%RSI,1),%ZMM0

(230) 0x4346a4 VFMSUB132PD	(%R14,%RSI,1),%ZMM0,%ZMM15

(230) 0x4346ab VADDPD	(%RDX,%RSI,1),%ZMM15,%ZMM3

(230) 0x4346b2 VDIVPD	(%R15,%RSI,1),%ZMM3,%ZMM2

(230) 0x4346b9 VMOVUPD	%ZMM2,(%R14,%RSI,1)

(230) 0x4346c0 ADD	$0x40,%RSI

(230) 0x4346c4 CMP	%R13,%RSI

(230) 0x4346c7 JE	434797

  (231) 0x4346cd VMOVUPD	(%R11,%RSI,1),%ZMM12

  (231) 0x4346d4 VMOVUPD	(%R10,%RSI,1),%ZMM4

  (231) 0x4346db VFMSUB132PD	(%R14,%RSI,1),%ZMM12,%ZMM4

  (231) 0x4346e2 VADDPD	(%RDX,%RSI,1),%ZMM4,%ZMM7

  (231) 0x4346e9 VDIVPD	(%R15,%RSI,1),%ZMM7,%ZMM13

  (231) 0x4346f0 VMOVUPD	%ZMM13,(%R14,%RSI,1)

  (231) 0x4346f7 VMOVUPD	0x40(%R11,%RSI,1),%ZMM15

  (231) 0x4346ff VMOVUPD	0x40(%R10,%RSI,1),%ZMM14

  (231) 0x434707 VFMSUB132PD	0x40(%R14,%RSI,1),%ZMM15,%ZMM14

  (231) 0x43470f VADDPD	0x40(%RDX,%RSI,1),%ZMM14,%ZMM0

  (231) 0x434717 VDIVPD	0x40(%R15,%RSI,1),%ZMM0,%ZMM3

  (231) 0x43471f VMOVUPD	%ZMM3,0x40(%R14,%RSI,1)

  (231) 0x434727 VMOVUPD	0x80(%R10,%RSI,1),%ZMM2

  (231) 0x43472f VMOVUPD	0x80(%R11,%RSI,1),%ZMM4

  (231) 0x434737 VFMSUB132PD	0x80(%R14,%RSI,1),%ZMM4,%ZMM2

  (231) 0x43473f VADDPD	0x80(%RDX,%RSI,1),%ZMM2,%ZMM12

  (231) 0x434747 VDIVPD	0x80(%R15,%RSI,1),%ZMM12,%ZMM7

  (231) 0x43474f VMOVUPD	%ZMM7,0x80(%R14,%RSI,1)

  (231) 0x434757 VMOVUPD	0xc0(%R10,%RSI,1),%ZMM13

  (231) 0x43475f VMOVUPD	0xc0(%R11,%RSI,1),%ZMM14

  (231) 0x434767 VFMSUB132PD	0xc0(%R14,%RSI,1),%ZMM14,%ZMM13

  (231) 0x43476f VADDPD	0xc0(%RDX,%RSI,1),%ZMM13,%ZMM15

  (231) 0x434777 VDIVPD	0xc0(%R15,%RSI,1),%ZMM15,%ZMM0

  (231) 0x43477f VMOVUPD	%ZMM0,0xc0(%R14,%RSI,1)

  (231) 0x434787 ADD	$0x100,%RSI

  (231) 0x43478e CMP	%R13,%RSI

  (231) 0x434791 JNE	4346cd

(230) 0x434797 MOV	0x3c(%RSP),%R14D

(230) 0x43479c MOV	%EAX,%ESI

(230) 0x43479e AND	$-0x8,%ESI

(230) 0x4347a1 ADD	%ESI,%ECX

(230) 0x4347a3 LEA	(%RSI,%R14,1),%R9D

(230) 0x4347a7 TEST	$0x7,%AL

(230) 0x4347a9 JE	43494d

(230) 0x4347af SUB	%ESI,%EAX

(230) 0x4347b1 LEA	-0x1(%RAX),%R10D

(230) 0x4347b5 CMP	$0x2,%R10D

(230) 0x4347b9 JBE	434840

(230) 0x4347bf MOVSXD	0x3c(%RSP),%RDX

(230) 0x4347c4 MOV	0x20(%RSP),%R11

(230) 0x4347c9 MOV	0x30(%RSP),%R14

(230) 0x4347ce VMOVQ	%XMM1,%R13

(230) 0x4347d3 LEA	(%R11,%RDX,1),%R15

(230) 0x4347d7 MOV	0x28(%RSP),%R11

(230) 0x4347dc ADD	%RSI,%R15

(230) 0x4347df LEA	(%R13,%R15,8),%R10

(230) 0x4347e4 LEA	(%R14,%RDX,1),%R13

(230) 0x4347e8 LEA	(%RDI,%RDX,1),%R14

(230) 0x4347ec ADD	%RSI,%R13

(230) 0x4347ef ADD	%RSI,%R14

(230) 0x4347f2 VMOVUPD	(%R10),%YMM3

(230) 0x4347f7 LEA	(%R11,%RDX,1),%R15

(230) 0x4347fb ADD	%R8,%RDX

(230) 0x4347fe ADD	%RSI,%RDX

(230) 0x434801 ADD	%RSI,%R15

(230) 0x434804 VMOVQ	%XMM6,%RSI

(230) 0x434809 VMOVUPD	(%R12,%RDX,8),%YMM2

(230) 0x43480f VMOVQ	%XMM5,%RDX

(230) 0x434814 VFMSUB132PD	(%RSI,%R15,8),%YMM2,%YMM3

(230) 0x43481a VADDPD	(%R12,%R14,8),%YMM3,%YMM4

(230) 0x434820 VDIVPD	(%RDX,%R13,8),%YMM4,%YMM12

(230) 0x434826 VMOVUPD	%YMM12,(%R10)

(230) 0x43482b MOV	%EAX,%R10D

(230) 0x43482e AND	$-0x4,%R10D

(230) 0x434832 ADD	%R10D,%R9D

(230) 0x434835 ADD	%R10D,%ECX

(230) 0x434838 TEST	$0x3,%AL

(230) 0x43483a JE	43494d

(230) 0x434840 MOV	0x20(%RSP),%R10

(230) 0x434845 MOV	0x28(%RSP),%R15

(230) 0x43484a MOVSXD	%R9D,%RAX

(230) 0x43484d VMOVQ	%XMM1,%R14

(230) 0x434852 VMOVQ	%XMM6,%R11

(230) 0x434857 LEA	(%RDI,%RAX,1),%RSI

(230) 0x43485b LEA	(%R10,%RAX,1),%R13

(230) 0x43485f LEA	(%R14,%R13,8),%RDX

(230) 0x434863 LEA	(%R15,%RAX,1),%R14

(230) 0x434867 LEA	(%R8,%RAX,1),%R13

(230) 0x43486b VMOVSD	(%R11,%R14,8),%XMM7

(230) 0x434871 MOV	0x30(%RSP),%R11

(230) 0x434876 VMOVSD	(%R12,%R13,8),%XMM13

(230) 0x43487c VFMSUB132SD	(%RDX),%XMM13,%XMM7

(230) 0x434881 VADDSD	(%R12,%RSI,8),%XMM7,%XMM14

(230) 0x434887 VMOVQ	%XMM5,%RSI

(230) 0x43488c ADD	%R11,%RAX

(230) 0x43488f VDIVSD	(%RSI,%RAX,8),%XMM14,%XMM15

(230) 0x434894 VMOVSD	%XMM15,(%RDX)

(230) 0x434898 MOV	0x38(%RSP),%EDX

(230) 0x43489c LEA	0x1(%RCX),%EAX

(230) 0x43489f CMP	%EDX,%EAX

(230) 0x4348a1 JAE	43494d

(230) 0x4348a7 LEA	0x1(%R9),%EAX

(230) 0x4348ab VMOVQ	%XMM1,%R13

(230) 0x4348b0 ADD	$0x2,%ECX

(230) 0x4348b3 CLTQ

(230) 0x4348b5 LEA	(%R10,%RAX,1),%R14

(230) 0x4348b9 LEA	(%RDI,%RAX,1),%RSI

(230) 0x4348bd LEA	(%R13,%R14,8),%RDX

(230) 0x4348c2 VMOVQ	%RSI,%XMM3

(230) 0x4348c7 LEA	(%R15,%RAX,1),%R14

(230) 0x4348cb LEA	(%R8,%RAX,1),%R13

(230) 0x4348cf VMOVQ	%XMM6,%RSI

(230) 0x4348d4 ADD	%R11,%RAX

(230) 0x4348d7 VMOVSD	(%R12,%R13,8),%XMM2

(230) 0x4348dd MOV	%R11,%R13

(230) 0x4348e0 VMOVSD	(%RSI,%R14,8),%XMM0

(230) 0x4348e6 VMOVQ	%XMM5,%R11

(230) 0x4348eb VMOVQ	%XMM3,%R14

(230) 0x4348f0 VFMSUB132SD	(%RDX),%XMM2,%XMM0

(230) 0x4348f5 VADDSD	(%R12,%R14,8),%XMM0,%XMM4

(230) 0x4348fb VDIVSD	(%R11,%RAX,8),%XMM4,%XMM12

(230) 0x434901 MOV	0x38(%RSP),%EAX

(230) 0x434905 VMOVSD	%XMM12,(%RDX)

(230) 0x434909 CMP	%EAX,%ECX

(230) 0x43490b JAE	43494d

(230) 0x43490d ADD	$0x2,%R9D

(230) 0x434911 VMOVQ	%XMM1,%RCX

(230) 0x434916 MOVSXD	%R9D,%R9

(230) 0x434919 ADD	%R9,%R10

(230) 0x43491c ADD	%R9,%RDI

(230) 0x43491f ADD	%R9,%R15

(230) 0x434922 ADD	%R9,%R8

(230) 0x434925 LEA	(%RCX,%R10,8),%RDX

(230) 0x434929 ADD	%R9,%R13

(230) 0x43492c VMOVSD	(%RSI,%R15,8),%XMM1

(230) 0x434932 VMOVSD	(%R12,%R8,8),%XMM6

(230) 0x434938 VFMSUB132SD	(%RDX),%XMM6,%XMM1

(230) 0x43493d VADDSD	(%R12,%RDI,8),%XMM1,%XMM7

(230) 0x434943 VDIVSD	(%R11,%R13,8),%XMM7,%XMM5

(230) 0x434949 VMOVSD	%XMM5,(%RDX)

(230) 0x43494d MOV	0x38(%RSP),%ECX

(230) 0x434951 INC	%RBX

(230) 0x434954 CMP	%EBX,0x18(%RSP)

(230) 0x434958 JLE	434980

(230) 0x43495a MOV	0x10(%RSP),%EAX

(230) 0x43495e MOV	0x14(%RSP),%R8D

(230) 0x434963 MOV	0x1c(%RSP),%R13D

(230) 0x434968 SUB	%ECX,%EAX

(230) 0x43496a MOV	%R8D,0x3c(%RSP)

(230) 0x43496f JMP	434550

0x434974 NOPW	%CS:(%RAX,%RAX,1)

0x43497f NOP

0x434980 VZEROUPPER

0x434983 LEA	-0x28(%RBP),%RSP

0x434987 POP	%RBX

0x434988 POP	%R12

0x43498a POP	%R13

0x43498c POP	%R14

0x43498e POP	%R15

0x434990 POP	%RBP

0x434991 RET

0x434992 NOPW	%CS:(%RAX,%RAX,1)

0x43499d NOPL	(%RAX)

(230) 0x4349a0 MOV	0x3c(%RSP),%R9D

(230) 0x4349a5 XOR	%ESI,%ESI

(230) 0x4349a7 JMP	4347af

0x4349ac INC	%R8D

0x4349af XOR	%EDX,%EDX

0x4349b1 JMP	4344f2

0x4349b6 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.77+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:218-221
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:218-221

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.63 cycles (1.25x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.38 cycles (1.28x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:221

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	80
nb uops	77
loop length	288
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.63
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

all	7%
load	9%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (5.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 434470

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x24(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EBX,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 434983 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x513>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 434983 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x513>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %EBX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x1c(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EDI,%R12D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 4349ac <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x53c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R8D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R8,%RCX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R9D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 434983 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x513>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x14(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%R14),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x1c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x10(%R14),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R14),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x8(%R14),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %R10D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10D,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4344f2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x82>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:218-221
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:218-221

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.38 cycles (1.28x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:220
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:221

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	80
nb uops	77
loop length	288
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.63 cycles
front end	9.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.63
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

all	7%
load	9%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	7%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (5.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 434470

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x24(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
LEA 0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %EBX,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 434983 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x513>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 434983 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x513>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R13D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %EBX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x1c(%RSP),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %EDI,%R12D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %EBX	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 4349ac <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x53c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R8D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R8,%RCX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R9D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 434983 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x513>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x14(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%R14),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x1c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x10(%R14),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R14),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x8(%R14),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %R15D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
SUB %R10D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10D,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4344f2 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.11+0x82>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.36	1.60
▼Loop 230 - advec_mom.cpp:220-221 - exec–	0.00	0.01
○Loop 231 - advec_mom.cpp:221-221 - exec	4.36	1.60

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code