OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:157-160 [...]	Coverage (incl. loops): 1.32% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 157 - 160

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

159:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

160:           node_flux(i, j) = 0.25 * (mass_flux_y(i - 1, j + 0) + mass_flux_y(i, j) + mass_flux_y(i - 1, j + 1) + mass_flux_y(i + 0, j + 1));

0x433f90 PUSH	%RBP

0x433f91 MOV	%RSP,%RBP

0x433f94 PUSH	%R15

0x433f96 PUSH	%R14

0x433f98 PUSH	%R13

0x433f9a PUSH	%R12

0x433f9c PUSH	%RBX

0x433f9d MOV	%RDI,%R15

0x433fa0 AND	$-0x40,%RSP

0x433fa4 SUB	$0x40,%RSP

0x433fa8 MOV	0x18(%RDI),%EAX

0x433fab MOV	0x1c(%RDI),%EDX

0x433fae MOV	0x10(%RDI),%EDI

0x433fb1 MOV	0x14(%R15),%ECX

0x433fb5 ADD	$0x4,%EDX

0x433fb8 INC	%EDI

0x433fba LEA	-0x1(%RAX),%EBX

0x433fbd MOV	%EDX,0x28(%RSP)

0x433fc1 MOV	%EDI,0x24(%RSP)

0x433fc5 CMP	%EDX,%EBX

0x433fc7 JGE	434433

0x433fcd MOV	%EDX,%R12D

0x433fd0 LEA	0x3(%RCX),%R14D

0x433fd4 SUB	%EBX,%R12D

0x433fd7 CMP	%R14D,%EDI

0x433fda JGE	434433

0x433fe0 MOV	%R14D,%ESI

0x433fe3 SUB	%EDI,%ESI

0x433fe5 MOV	%ESI,0x2c(%RSP)

0x433fe9 CALL	404630 <omp_get_num_threads@plt>

0x433fee MOV	%EAX,%R13D

0x433ff1 CALL	404520 <omp_get_thread_num@plt>

0x433ff6 XOR	%EDX,%EDX

0x433ff8 MOV	%EAX,%EDI

0x433ffa MOV	0x2c(%RSP),%EAX

0x433ffe IMUL	%R12D,%EAX

0x434002 DIV	%R13D

0x434005 MOV	%EAX,%R13D

0x434008 CMP	%EDX,%EDI

0x43400a JB	43445c

0x434010 IMUL	%R13D,%EDI

0x434014 ADD	%EDX,%EDI

0x434016 LEA	(%R13,%RDI,1),%R8D

0x43401b MOV	%R8D,0x20(%RSP)

0x434020 CMP	%R8D,%EDI

0x434023 JAE	434433

0x434029 MOV	%EDI,%EAX

0x43402b XOR	%EDX,%EDX

0x43402d MOV	0x24(%RSP),%R9D

0x434032 VMOVQ	(%R15),%XMM4

0x434037 DIVL	0x2c(%RSP)

0x43403b VMOVQ	0x8(%R15),%XMM3

0x434041 VMOVSD	0x30657(%RIP),%XMM9

0x434049 VBROADCASTSD	%XMM9,%YMM10

0x43404e VBROADCASTSD	%XMM9,%ZMM5

0x434054 ADD	%EDX,%R9D

0x434057 ADD	%EBX,%EAX

0x434059 SUB	%R9D,%R14D

0x43405c MOVSXD	%EAX,%R12

0x43405f MOV	%R9D,0x3c(%RSP)

0x434064 NOPW	%CS:(%RAX,%RAX,1)

0x43406f NOP

(228) 0x434070 CMP	%R14D,%R13D

(228) 0x434073 MOV	%R14D,%EDX

(228) 0x434076 CMOVBE	%R13D,%EDX

(228) 0x43407a LEA	(%RDI,%RDX,1),%R10D

(228) 0x43407e MOV	%R10D,0x38(%RSP)

(228) 0x434083 CMP	%R10D,%EDI

(228) 0x434086 JAE	434402

(228) 0x43408c VMOVQ	%XMM4,%R11

(228) 0x434091 VMOVQ	%XMM3,%R14

(228) 0x434096 LEA	-0x1(%RDX),%ECX

(228) 0x434099 MOV	(%R11),%R9

(228) 0x43409c MOV	(%R14),%R8

(228) 0x43409f VMOVQ	0x10(%R14),%XMM6

(228) 0x4340a5 MOV	0x10(%R11),%R15

(228) 0x4340a9 MOV	%R9,%RBX

(228) 0x4340ac IMUL	%R12,%R8

(228) 0x4340b0 IMUL	%R12,%RBX

(228) 0x4340b4 MOV	%R8,0x30(%RSP)

(228) 0x4340b9 ADD	%RBX,%R9

(228) 0x4340bc CMP	$0x6,%ECX

(228) 0x4340bf JBE	434450

(228) 0x4340c5 MOVSXD	0x3c(%RSP),%R10

(228) 0x4340ca VMOVQ	%XMM6,%R11

(228) 0x4340cf XOR	%EAX,%EAX

(228) 0x4340d1 LEA	(%RBX,%R10,1),%RSI

(228) 0x4340d5 LEA	(%R9,%R10,1),%RCX

(228) 0x4340d9 ADD	%R8,%R10

(228) 0x4340dc LEA	(%R11,%R10,8),%R11

(228) 0x4340e0 MOV	%EDX,%R10D

(228) 0x4340e3 SHR	$0x3,%R10D

(228) 0x4340e7 SAL	$0x6,%R10

(228) 0x4340eb LEA	-0x40(%R10),%R8

(228) 0x4340ef SHR	$0x6,%R8

(228) 0x4340f3 SAL	$0x3,%RSI

(228) 0x4340f7 SAL	$0x3,%RCX

(228) 0x4340fb INC	%R8

(228) 0x4340fe LEA	-0x8(%R15,%RSI,1),%R14

(228) 0x434103 LEA	-0x8(%R15,%RCX,1),%R13

(228) 0x434108 ADD	%R15,%RSI

(228) 0x43410b ADD	%R15,%RCX

(228) 0x43410e AND	$0x3,%R8D

(228) 0x434112 JE	4341c5

(228) 0x434118 CMP	$0x1,%R8

(228) 0x43411c JE	434188

(228) 0x43411e CMP	$0x2,%R8

(228) 0x434122 JE	434154

(228) 0x434124 VMOVUPD	(%R14),%ZMM0

(228) 0x43412a VMOVUPD	(%R13),%ZMM11

(228) 0x434131 VADDPD	(%RSI),%ZMM0,%ZMM1

(228) 0x434137 MOV	$0x40,%EAX

(228) 0x43413c VADDPD	(%RCX),%ZMM11,%ZMM2

(228) 0x434142 VADDPD	%ZMM2,%ZMM1,%ZMM7

(228) 0x434148 VMULPD	%ZMM5,%ZMM7,%ZMM8

(228) 0x43414e VMOVUPD	%ZMM8,(%R11)

(228) 0x434154 VMOVUPD	(%R14,%RAX,1),%ZMM12

(228) 0x43415b VMOVUPD	(%R13,%RAX,1),%ZMM14

(228) 0x434163 VADDPD	(%RSI,%RAX,1),%ZMM12,%ZMM13

(228) 0x43416a VADDPD	(%RCX,%RAX,1),%ZMM14,%ZMM15

(228) 0x434171 VADDPD	%ZMM15,%ZMM13,%ZMM0

(228) 0x434177 VMULPD	%ZMM5,%ZMM0,%ZMM1

(228) 0x43417d VMOVUPD	%ZMM1,(%R11,%RAX,1)

(228) 0x434184 ADD	$0x40,%RAX

(228) 0x434188 VMOVUPD	(%R14,%RAX,1),%ZMM11

(228) 0x43418f VMOVUPD	(%R13,%RAX,1),%ZMM7

(228) 0x434197 VADDPD	(%RSI,%RAX,1),%ZMM11,%ZMM2

(228) 0x43419e VADDPD	(%RCX,%RAX,1),%ZMM7,%ZMM8

(228) 0x4341a5 VADDPD	%ZMM8,%ZMM2,%ZMM12

(228) 0x4341ab VMULPD	%ZMM5,%ZMM12,%ZMM13

(228) 0x4341b1 VMOVUPD	%ZMM13,(%R11,%RAX,1)

(228) 0x4341b8 ADD	$0x40,%RAX

(228) 0x4341bc CMP	%R10,%RAX

(228) 0x4341bf JE	4342a0

  (229) 0x4341c5 VMOVUPD	(%R14,%RAX,1),%ZMM14

  (229) 0x4341cc VMOVUPD	(%R13,%RAX,1),%ZMM0

  (229) 0x4341d4 VADDPD	(%RSI,%RAX,1),%ZMM14,%ZMM15

  (229) 0x4341db VADDPD	(%RCX,%RAX,1),%ZMM0,%ZMM1

  (229) 0x4341e2 VADDPD	%ZMM1,%ZMM15,%ZMM11

  (229) 0x4341e8 VMULPD	%ZMM5,%ZMM11,%ZMM2

  (229) 0x4341ee VMOVUPD	%ZMM2,(%R11,%RAX,1)

  (229) 0x4341f5 VMOVUPD	0x40(%R14,%RAX,1),%ZMM7

  (229) 0x4341fd VMOVUPD	0x40(%R13,%RAX,1),%ZMM12

  (229) 0x434205 VADDPD	0x40(%RSI,%RAX,1),%ZMM7,%ZMM8

  (229) 0x43420d VADDPD	0x40(%RCX,%RAX,1),%ZMM12,%ZMM13

  (229) 0x434215 VADDPD	%ZMM13,%ZMM8,%ZMM14

  (229) 0x43421b VMULPD	%ZMM5,%ZMM14,%ZMM15

  (229) 0x434221 VMOVUPD	%ZMM15,0x40(%R11,%RAX,1)

  (229) 0x434229 VMOVUPD	0x80(%R14,%RAX,1),%ZMM0

  (229) 0x434231 VMOVUPD	0x80(%R13,%RAX,1),%ZMM11

  (229) 0x434239 VADDPD	0x80(%RSI,%RAX,1),%ZMM0,%ZMM1

  (229) 0x434241 VADDPD	0x80(%RCX,%RAX,1),%ZMM11,%ZMM2

  (229) 0x434249 VADDPD	%ZMM2,%ZMM1,%ZMM7

  (229) 0x43424f VMULPD	%ZMM5,%ZMM7,%ZMM8

  (229) 0x434255 VMOVUPD	%ZMM8,0x80(%R11,%RAX,1)

  (229) 0x43425d VMOVUPD	0xc0(%R14,%RAX,1),%ZMM12

  (229) 0x434265 VMOVUPD	0xc0(%R13,%RAX,1),%ZMM14

  (229) 0x43426d VADDPD	0xc0(%RSI,%RAX,1),%ZMM12,%ZMM13

  (229) 0x434275 VADDPD	0xc0(%RCX,%RAX,1),%ZMM14,%ZMM15

  (229) 0x43427d VADDPD	%ZMM15,%ZMM13,%ZMM0

  (229) 0x434283 VMULPD	%ZMM5,%ZMM0,%ZMM1

  (229) 0x434289 VMOVUPD	%ZMM1,0xc0(%R11,%RAX,1)

  (229) 0x434291 ADD	$0x100,%RAX

  (229) 0x434297 CMP	%R10,%RAX

  (229) 0x43429a JNE	4341c5

(228) 0x4342a0 MOV	0x3c(%RSP),%R13D

(228) 0x4342a5 MOV	%EDX,%EAX

(228) 0x4342a7 AND	$-0x8,%EAX

(228) 0x4342aa ADD	%EAX,%EDI

(228) 0x4342ac ADD	%EAX,%R13D

(228) 0x4342af TEST	$0x7,%DL

(228) 0x4342b2 JE	4343fe

(228) 0x4342b8 SUB	%EAX,%EDX

(228) 0x4342ba LEA	-0x1(%RDX),%ESI

(228) 0x4342bd CMP	$0x2,%ESI

(228) 0x4342c0 JBE	434326

(228) 0x4342c2 MOVSXD	0x3c(%RSP),%R14

(228) 0x4342c7 MOV	0x30(%RSP),%R10

(228) 0x4342cc VMOVQ	%XMM6,%R8

(228) 0x4342d1 LEA	(%R9,%R14,1),%R11

(228) 0x4342d5 LEA	(%RBX,%R14,1),%RCX

(228) 0x4342d9 ADD	%RAX,%R11

(228) 0x4342dc ADD	%RAX,%RCX

(228) 0x4342df ADD	%R10,%RAX

(228) 0x4342e2 SAL	$0x3,%R11

(228) 0x4342e6 VMOVUPD	-0x8(%R15,%R11,1),%YMM11

(228) 0x4342ed VMOVUPD	(%R15,%R11,1),%YMM2

(228) 0x4342f3 VADDPD	-0x8(%R15,%RCX,8),%YMM11,%YMM7

(228) 0x4342fa VADDPD	(%R15,%RCX,8),%YMM2,%YMM8

(228) 0x434300 ADD	%R14,%RAX

(228) 0x434303 VADDPD	%YMM8,%YMM7,%YMM12

(228) 0x434308 VMULPD	%YMM10,%YMM12,%YMM13

(228) 0x43430d VMOVUPD	%YMM13,(%R8,%RAX,8)

(228) 0x434313 MOV	%EDX,%EAX

(228) 0x434315 AND	$-0x4,%EAX

(228) 0x434318 ADD	%EAX,%R13D

(228) 0x43431b ADD	%EAX,%EDI

(228) 0x43431d AND	$0x3,%EDX

(228) 0x434320 JE	4343fe

(228) 0x434326 MOVSXD	%R13D,%RDX

(228) 0x434329 MOV	0x30(%RSP),%R11

(228) 0x43432e LEA	-0x1(%R13),%EAX

(228) 0x434332 LEA	(%R9,%RDX,1),%R14

(228) 0x434336 CLTQ

(228) 0x434338 LEA	(%RDX,%RBX,1),%RSI

(228) 0x43433c LEA	(%R15,%R14,8),%R8

(228) 0x434340 MOV	0x38(%RSP),%R14D

(228) 0x434345 LEA	(%RBX,%RAX,1),%R10

(228) 0x434349 ADD	%R9,%RAX

(228) 0x43434c VMOVSD	(%R15,%R10,8),%XMM14

(228) 0x434352 LEA	(%R15,%RSI,8),%RCX

(228) 0x434356 VADDSD	(%R15,%RAX,8),%XMM14,%XMM15

(228) 0x43435c VMOVQ	%XMM6,%RAX

(228) 0x434361 VMOVSD	(%R8),%XMM0

(228) 0x434366 VADDSD	(%RCX),%XMM0,%XMM1

(228) 0x43436a VADDSD	%XMM1,%XMM15,%XMM11

(228) 0x43436e VMULSD	%XMM9,%XMM11,%XMM7

(228) 0x434373 ADD	%R11,%RDX

(228) 0x434376 VMOVSD	%XMM7,(%RAX,%RDX,8)

(228) 0x43437b LEA	0x1(%RDI),%EDX

(228) 0x43437e CMP	%R14D,%EDX

(228) 0x434381 JAE	4343fe

(228) 0x434383 LEA	0x1(%R13),%EAX

(228) 0x434387 VMOVSD	(%R8),%XMM2

(228) 0x43438c ADD	$0x2,%EDI

(228) 0x43438f VADDSD	(%RCX),%XMM2,%XMM8

(228) 0x434393 CLTQ

(228) 0x434395 VMOVQ	%XMM6,%RCX

(228) 0x43439a LEA	(%RBX,%RAX,1),%RSI

(228) 0x43439e LEA	(%R9,%RAX,1),%RDX

(228) 0x4343a2 ADD	%R11,%RAX

(228) 0x4343a5 LEA	(%R15,%RSI,8),%R10

(228) 0x4343a9 LEA	(%R15,%RDX,8),%RDX

(228) 0x4343ad VMOVSD	(%RDX),%XMM12

(228) 0x4343b1 VADDSD	(%R10),%XMM12,%XMM13

(228) 0x4343b6 VADDSD	%XMM13,%XMM8,%XMM14

(228) 0x4343bb VMULSD	%XMM9,%XMM14,%XMM15

(228) 0x4343c0 VMOVSD	%XMM15,(%RCX,%RAX,8)

(228) 0x4343c5 CMP	%R14D,%EDI

(228) 0x4343c8 JAE	4343fe

(228) 0x4343ca ADD	$0x2,%R13D

(228) 0x4343ce MOVSXD	%R13D,%RDI

(228) 0x4343d1 ADD	%RDI,%R11

(228) 0x4343d4 ADD	%RDI,%RBX

(228) 0x4343d7 ADD	%R9,%RDI

(228) 0x4343da VMOVSD	(%R15,%RBX,8),%XMM0

(228) 0x4343e0 VMOVSD	(%R15,%RDI,8),%XMM1

(228) 0x4343e6 VADDSD	(%R10),%XMM0,%XMM11

(228) 0x4343eb VADDSD	(%RDX),%XMM1,%XMM7

(228) 0x4343ef VADDSD	%XMM7,%XMM11,%XMM2

(228) 0x4343f3 VMULSD	%XMM9,%XMM2,%XMM8

(228) 0x4343f8 VMOVSD	%XMM8,(%RCX,%R11,8)

(228) 0x4343fe MOV	0x38(%RSP),%EDI

(228) 0x434402 INC	%R12

(228) 0x434405 CMP	%R12D,0x28(%RSP)

(228) 0x43440a JLE	434430

(228) 0x43440c MOV	0x20(%RSP),%R13D

(228) 0x434411 MOV	0x24(%RSP),%R9D

(228) 0x434416 MOV	0x2c(%RSP),%R14D

(228) 0x43441b SUB	%EDI,%R13D

(228) 0x43441e MOV	%R9D,0x3c(%RSP)

(228) 0x434423 JMP	434070

0x434428 NOPL	(%RAX,%RAX,1)

0x434430 VZEROUPPER

0x434433 LEA	-0x28(%RBP),%RSP

0x434437 POP	%RBX

0x434438 POP	%R12

0x43443a POP	%R13

0x43443c POP	%R14

0x43443e POP	%R15

0x434440 POP	%RBP

0x434441 RET

0x434442 NOPW	%CS:(%RAX,%RAX,1)

0x43444d NOPL	(%RAX)

(228) 0x434450 MOV	0x3c(%RSP),%R13D

(228) 0x434455 XOR	%EAX,%EAX

(228) 0x434457 JMP	4342b8

0x43445c INC	%R13D

0x43445f XOR	%EDX,%EDX

0x434461 JMP	434010

0x434466 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.84+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.18+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:167	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:101	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.12+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:167	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:70	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:157-160
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:157-160

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.75 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.25 cycles (1.30x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:160

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	78
nb uops	76
loop length	284
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	1
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.25	4.25	4.25	4.25	0.00	1.00	1.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.25	4.25	4.25	4.25	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.50
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	7%
load	8%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	7%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (4.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 433f90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x1c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV 0x10(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x14(%R15),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
INC %EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %EDI,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EDX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 434433 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
SUB %EBX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 434433 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x2c(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
IMUL %R12D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 43445c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4cc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R13D,%EDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA (%R13,%RDI,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R8D,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R8D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 434433 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x24(%RSP),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
VMOVQ (%R15),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
DIVL 0x2c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ 0x8(%R15),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x30657(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM9,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB %R9D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 434010 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:157-160
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:157-160

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.75 cycles (6.86x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.25 cycles (1.30x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:159
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:160

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 52 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	78
nb uops	76
loop length	284
used x86 registers	14
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	1
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.25	4.25	4.25	4.25	0.00	1.00	1.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.25	4.25	4.25	4.25	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.50
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	7%
load	8%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	7%
load	9%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (4.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 433f90

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x1c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV 0x10(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x14(%R15),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x4,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
INC %EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA -0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %EDI,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EDX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 434433 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
SUB %EBX,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 434433 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R14D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ESI,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x2c(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
IMUL %R12D,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R13D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 43445c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4cc>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R13D,%EDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA (%R13,%RDI,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R8D,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R8D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 434433 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x4a3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x24(%RSP),%R9D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
VMOVQ (%R15),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
DIVL 0x2c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ 0x8(%R15),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x30657(%RIP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM9,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %EDX,%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB %R9D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 434010 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.8+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.32	0.49
▼Loop 228 - advec_mom.cpp:159-160 - exec–	0.00	0.01
○Loop 229 - advec_mom.cpp:160-160 - exec	1.32	0.48

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ASM code

Code clean check

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Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code