OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:167-172 [...]	Coverage (incl. loops): 3.12% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 167 - 172

--------------------------------------------------------------------------------

167: #pragma omp parallel for simd collapse(2)

168:       for (int j = (y_min - 1 + 1); j < (y_max + 2 + 2); j++) {

169:         for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

170:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

171:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

172:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i + 0, j - 1) + node_flux(i, j);

0x433790 PUSH	%RBP

0x433791 MOV	%RSP,%RBP

0x433794 PUSH	%R15

0x433796 PUSH	%R14

0x433798 PUSH	%R13

0x43379a PUSH	%R12

0x43379c PUSH	%RBX

0x43379d AND	$-0x40,%RSP

0x4337a1 ADD	$-0x80,%RSP

0x4337a5 MOV	0x34(%RDI),%EAX

0x4337a8 MOV	0x28(%RDI),%EBX

0x4337ab MOV	0x30(%RDI),%R14D

0x4337af MOV	0x2c(%RDI),%EDX

0x4337b2 ADD	$0x4,%EAX

0x4337b5 LEA	0x1(%RBX),%ESI

0x4337b8 MOV	%EAX,0x18(%RSP)

0x4337bc MOV	%ESI,0x14(%RSP)

0x4337c0 CMP	%EAX,%R14D

0x4337c3 JGE	433f53

0x4337c9 MOV	%EAX,%EBX

0x4337cb LEA	0x3(%RDX),%R15D

0x4337cf SUB	%R14D,%EBX

0x4337d2 CMP	%R15D,%ESI

0x4337d5 JGE	433f53

0x4337db MOV	%R15D,%ECX

0x4337de MOV	%RDI,%R13

0x4337e1 SUB	%ESI,%ECX

0x4337e3 MOV	%ECX,0x1c(%RSP)

0x4337e7 CALL	404630 <omp_get_num_threads@plt>

0x4337ec MOV	%EAX,%R12D

0x4337ef CALL	404520 <omp_get_thread_num@plt>

0x4337f4 XOR	%EDX,%EDX

0x4337f6 MOV	%EAX,%EDI

0x4337f8 MOV	0x1c(%RSP),%EAX

0x4337fc IMUL	%EBX,%EAX

0x4337ff DIV	%R12D

0x433802 MOV	%EAX,%R8D

0x433805 CMP	%EDX,%EDI

0x433807 JB	433f7b

0x43380d IMUL	%R8D,%EDI

0x433811 LEA	(%RDI,%RDX,1),%EBX

0x433814 LEA	(%R8,%RBX,1),%R9D

0x433818 MOV	%R9D,0x10(%RSP)

0x43381d CMP	%R9D,%EBX

0x433820 JAE	433f53

0x433826 MOV	%EBX,%EAX

0x433828 XOR	%EDX,%EDX

0x43382a MOV	0x14(%RSP),%R10D

0x43382f VMOVQ	(%R13),%XMM22

0x433836 DIVL	0x1c(%RSP)

0x43383a VMOVQ	0x20(%R13),%XMM21

0x433841 VMOVQ	0x10(%R13),%XMM20

0x433848 MOV	%R15D,%R11D

0x43384b VMOVQ	0x8(%R13),%XMM19

0x433852 VMOVQ	0x18(%R13),%XMM18

0x433859 VMOVSD	0x30e3d(%RIP),%XMM23

0x433863 MOV	%R8D,%ESI

0x433866 VBROADCASTSD	%XMM23,%YMM24

0x43386c VBROADCASTSD	%XMM23,%ZMM15

0x433872 ADD	%EDX,%R10D

0x433875 ADD	%R14D,%EAX

0x433878 SUB	%R10D,%R11D

0x43387b MOVSXD	%EAX,%R14

0x43387e MOV	%R10D,0x34(%RSP)

0x433883 MOV	%R11D,%EDI

0x433886 MOV	%R14,0x60(%RSP)

0x43388b NOPL	(%RAX,%RAX,1)

(226) 0x433890 CMP	%EDI,%ESI

(226) 0x433892 CMOVBE	%ESI,%EDI

(226) 0x433895 LEA	(%RBX,%RDI,1),%ESI

(226) 0x433898 MOV	%EDI,0x78(%RSP)

(226) 0x43389c MOV	%ESI,0x30(%RSP)

(226) 0x4338a0 CMP	%ESI,%EBX

(226) 0x4338a2 JAE	433f1b

(226) 0x4338a8 MOV	0x60(%RSP),%R11

(226) 0x4338ad VMOVQ	%XMM22,%R12

(226) 0x4338b3 VMOVQ	%XMM21,%RAX

(226) 0x4338b9 MOV	%EDI,%R9D

(226) 0x4338bc VMOVQ	%XMM19,%RSI

(226) 0x4338c2 MOV	(%R12),%R14

(226) 0x4338c6 MOV	0x10(%RAX),%R8

(226) 0x4338ca VMOVQ	%XMM20,%RCX

(226) 0x4338d0 LEA	-0x1(%R9),%R9D

(226) 0x4338d4 VMOVQ	0x10(%RCX),%XMM11

(226) 0x4338d9 VMOVQ	0x10(%RSI),%XMM2

(226) 0x4338de LEA	-0x1(%R11),%R13D

(226) 0x4338e2 MOV	%R11,%R10

(226) 0x4338e5 MOVSXD	%R13D,%RDI

(226) 0x4338e8 MOV	0x10(%R12),%R13

(226) 0x4338ed MOV	(%RAX),%R12

(226) 0x4338f0 MOV	(%RSI),%RAX

(226) 0x4338f3 MOV	%RDI,%RDX

(226) 0x4338f6 MOV	%RDI,%R15

(226) 0x4338f9 IMUL	%R14,%RDX

(226) 0x4338fd IMUL	%R11,%R14

(226) 0x433901 IMUL	%RAX,%RDI

(226) 0x433905 MOV	%RDX,0x28(%RSP)

(226) 0x43390a IMUL	%R12,%R15

(226) 0x43390e MOV	%R14,0x58(%RSP)

(226) 0x433913 IMUL	%R11,%R12

(226) 0x433917 IMUL	(%RCX),%R11

(226) 0x43391b MOV	%RDI,0x48(%RSP)

(226) 0x433920 VMOVQ	%XMM18,%RDI

(226) 0x433926 IMUL	%R10,%RAX

(226) 0x43392a IMUL	(%RDI),%R10

(226) 0x43392e VMOVQ	0x10(%RDI),%XMM10

(226) 0x433933 MOV	%R15,0x68(%RSP)

(226) 0x433938 MOV	%R12,0x70(%RSP)

(226) 0x43393d MOV	%RAX,0x50(%RSP)

(226) 0x433942 MOV	%R11,0x20(%RSP)

(226) 0x433947 MOV	%R10,0x38(%RSP)

(226) 0x43394c CMP	$0x6,%R9D

(226) 0x433950 JBE	433f70

(226) 0x433956 MOVSXD	0x34(%RSP),%RCX

(226) 0x43395b VMOVQ	%XMM11,%RSI

(226) 0x433960 LEA	(%R12,%RCX,1),%R12

(226) 0x433964 LEA	(%RDX,%RCX,1),%R10

(226) 0x433968 LEA	(%R14,%RCX,1),%RDI

(226) 0x43396c LEA	(%R11,%RCX,1),%R11

(226) 0x433970 SAL	$0x3,%R12

(226) 0x433974 SAL	$0x3,%R10

(226) 0x433978 LEA	(%R8,%R12,1),%R14

(226) 0x43397c LEA	(%R13,%R10,1),%RDX

(226) 0x433981 LEA	-0x8(%R8,%R12,1),%R9

(226) 0x433986 LEA	(%R15,%RCX,1),%R15

(226) 0x43398a VMOVQ	%R14,%XMM7

(226) 0x43398f LEA	-0x8(%R13,%R10,1),%R14

(226) 0x433994 MOV	0x48(%RSP),%R10

(226) 0x433999 LEA	(%RSI,%R11,8),%R12

(226) 0x43399d MOV	0x50(%RSP),%R11

(226) 0x4339a2 VMOVQ	%RDX,%XMM5

(226) 0x4339a7 VMOVQ	%R9,%XMM1

(226) 0x4339ac VMOVQ	%XMM2,%R9

(226) 0x4339b1 SAL	$0x3,%R15

(226) 0x4339b5 SAL	$0x3,%RDI

(226) 0x4339b9 LEA	(%R8,%R15,1),%RAX

(226) 0x4339bd LEA	-0x8(%R13,%RDI,1),%RDX

(226) 0x4339c2 LEA	(%R11,%RCX,1),%RSI

(226) 0x4339c6 LEA	-0x8(%R8,%R15,1),%R15

(226) 0x4339cb VMOVQ	%RAX,%XMM6

(226) 0x4339d0 LEA	(%R13,%RDI,1),%RAX

(226) 0x4339d5 LEA	(%R10,%RCX,1),%RDI

(226) 0x4339d9 LEA	(%R9,%RSI,8),%R11

(226) 0x4339dd LEA	(%R9,%RDI,8),%R10

(226) 0x4339e1 MOV	0x78(%RSP),%EDI

(226) 0x4339e5 MOV	0x38(%RSP),%R9

(226) 0x4339ea VMOVQ	%XMM10,%RSI

(226) 0x4339ef SHR	$0x3,%EDI

(226) 0x4339f2 ADD	%R9,%RCX

(226) 0x4339f5 LEA	(%RSI,%RCX,8),%R9

(226) 0x4339f9 MOV	%RDI,%RSI

(226) 0x4339fc XOR	%ECX,%ECX

(226) 0x4339fe SAL	$0x6,%RSI

(226) 0x433a02 AND	$0x1,%EDI

(226) 0x433a05 JE	433a84

(226) 0x433a07 VMOVQ	%XMM6,%RDI

(226) 0x433a0c VMOVQ	%XMM7,%RCX

(226) 0x433a11 VMOVUPD	(%RAX),%ZMM0

(226) 0x433a17 VMOVUPD	(%RDX),%ZMM25

(226) 0x433a1d VMOVUPD	(%RDI),%ZMM4

(226) 0x433a23 VMOVQ	%XMM1,%RDI

(226) 0x433a28 VMULPD	(%RCX),%ZMM0,%ZMM3

(226) 0x433a2e VMOVUPD	(%R15),%ZMM8

(226) 0x433a34 VMULPD	(%RDI),%ZMM25,%ZMM16

(226) 0x433a3a VMOVQ	%XMM5,%RCX

(226) 0x433a3f VFMADD231PD	(%RCX),%ZMM4,%ZMM3

(226) 0x433a45 VFMADD231PD	(%R14),%ZMM8,%ZMM16

(226) 0x433a4b VADDPD	%ZMM16,%ZMM3,%ZMM9

(226) 0x433a51 MOV	$0x40,%ECX

(226) 0x433a56 VMULPD	%ZMM15,%ZMM9,%ZMM12

(226) 0x433a5c VMOVUPD	%ZMM12,(%R12)

(226) 0x433a63 VMOVUPD	(%R11),%ZMM17

(226) 0x433a69 VSUBPD	(%R10),%ZMM17,%ZMM26

(226) 0x433a6f VADDPD	%ZMM12,%ZMM26,%ZMM13

(226) 0x433a75 VMOVUPD	%ZMM13,(%R9)

(226) 0x433a7b CMP	%RSI,%RCX

(226) 0x433a7e JE	433ba4

(226) 0x433a84 VMOVQ	%R8,%XMM14

(226) 0x433a89 VMOVQ	%R13,%XMM3

(226) 0x433a8e MOV	%EBX,0xc(%RSP)

(226) 0x433a92 MOV	%RSI,0x40(%RSP)

(226) 0x433a97 VMOVQ	%XMM7,%RBX

(226) 0x433a9c VMOVQ	%XMM6,%R13

(226) 0x433aa1 VMOVQ	%XMM5,%R8

(226) 0x433aa6 VMOVQ	%XMM1,%RSI

  (227) 0x433aab VMOVUPD	(%RAX,%RCX,1),%ZMM5

  (227) 0x433ab2 VMOVUPD	(%RDX,%RCX,1),%ZMM27

  (227) 0x433ab9 VMOVUPD	(%R13,%RCX,1),%ZMM7

  (227) 0x433ac1 VMOVUPD	(%R15,%RCX,1),%ZMM1

  (227) 0x433ac8 VMULPD	(%RBX,%RCX,1),%ZMM5,%ZMM6

  (227) 0x433acf VMULPD	(%RSI,%RCX,1),%ZMM27,%ZMM28

  (227) 0x433ad6 MOV	0x40(%RSP),%RDI

  (227) 0x433adb VFMADD231PD	(%R8,%RCX,1),%ZMM7,%ZMM6

  (227) 0x433ae2 VFMADD231PD	(%R14,%RCX,1),%ZMM1,%ZMM28

  (227) 0x433ae9 VADDPD	%ZMM28,%ZMM6,%ZMM0

  (227) 0x433aef VMULPD	%ZMM15,%ZMM0,%ZMM4

  (227) 0x433af5 VMOVUPD	%ZMM4,(%R12,%RCX,1)

  (227) 0x433afc VMOVUPD	(%R11,%RCX,1),%ZMM29

  (227) 0x433b03 VSUBPD	(%R10,%RCX,1),%ZMM29,%ZMM30

  (227) 0x433b0a VADDPD	%ZMM4,%ZMM30,%ZMM8

  (227) 0x433b10 VMOVUPD	%ZMM8,(%R9,%RCX,1)

  (227) 0x433b17 VMOVUPD	0x40(%RAX,%RCX,1),%ZMM9

  (227) 0x433b1f VMOVUPD	0x40(%RDX,%RCX,1),%ZMM31

  (227) 0x433b27 VMOVUPD	0x40(%R13,%RCX,1),%ZMM13

  (227) 0x433b2f VMULPD	0x40(%RBX,%RCX,1),%ZMM9,%ZMM12

  (227) 0x433b37 VMULPD	0x40(%RSI,%RCX,1),%ZMM31,%ZMM25

  (227) 0x433b3f VMOVUPD	0x40(%R15,%RCX,1),%ZMM5

  (227) 0x433b47 VFMADD231PD	0x40(%R8,%RCX,1),%ZMM13,%ZMM12

  (227) 0x433b4f VFMADD231PD	0x40(%R14,%RCX,1),%ZMM5,%ZMM25

  (227) 0x433b57 VADDPD	%ZMM25,%ZMM12,%ZMM6

  (227) 0x433b5d VMULPD	%ZMM15,%ZMM6,%ZMM7

  (227) 0x433b63 VMOVUPD	%ZMM7,0x40(%R12,%RCX,1)

  (227) 0x433b6b VMOVUPD	0x40(%R11,%RCX,1),%ZMM16

  (227) 0x433b73 VSUBPD	0x40(%R10,%RCX,1),%ZMM16,%ZMM17

  (227) 0x433b7b VADDPD	%ZMM7,%ZMM17,%ZMM1

  (227) 0x433b81 VMOVUPD	%ZMM1,0x40(%R9,%RCX,1)

  (227) 0x433b89 SUB	$-0x80,%RCX

  (227) 0x433b8d CMP	%RDI,%RCX

  (227) 0x433b90 JNE	433aab

(226) 0x433b96 MOV	0xc(%RSP),%EBX

(226) 0x433b9a VMOVQ	%XMM14,%R8

(226) 0x433b9f VMOVQ	%XMM3,%R13

(226) 0x433ba4 MOV	0x78(%RSP),%EAX

(226) 0x433ba8 MOV	0x34(%RSP),%ESI

(226) 0x433bac MOV	%EAX,%ECX

(226) 0x433bae AND	$-0x8,%ECX

(226) 0x433bb1 ADD	%ECX,%ESI

(226) 0x433bb3 ADD	%ECX,%EBX

(226) 0x433bb5 TEST	$0x7,%AL

(226) 0x433bb7 JE	433f17

(226) 0x433bbd MOV	0x78(%RSP),%EDX

(226) 0x433bc1 SUB	%ECX,%EDX

(226) 0x433bc3 LEA	-0x1(%RDX),%R14D

(226) 0x433bc7 CMP	$0x2,%R14D

(226) 0x433bcb JBE	433cc1

(226) 0x433bd1 MOVSXD	0x34(%RSP),%RAX

(226) 0x433bd6 MOV	0x68(%RSP),%R12

(226) 0x433bdb MOV	0x70(%RSP),%RDI

(226) 0x433be0 MOV	0x28(%RSP),%R15

(226) 0x433be5 MOV	0x20(%RSP),%R14

(226) 0x433bea MOV	0x58(%RSP),%R11

(226) 0x433bef LEA	(%R12,%RAX,1),%R9

(226) 0x433bf3 MOV	0x48(%RSP),%R12

(226) 0x433bf8 ADD	%RAX,%RDI

(226) 0x433bfb LEA	(%R15,%RAX,1),%R10

(226) 0x433bff ADD	%RCX,%RDI

(226) 0x433c02 LEA	(%R14,%RAX,1),%R15

(226) 0x433c06 LEA	(%R11,%RAX,1),%R11

(226) 0x433c0a ADD	%RCX,%R10

(226) 0x433c0d SAL	$0x3,%RDI

(226) 0x433c11 ADD	%RCX,%R11

(226) 0x433c14 ADD	%RCX,%R9

(226) 0x433c17 VMOVUPD	(%R8,%RDI,1),%YMM14

(226) 0x433c1d VMOVUPD	-0x8(%R8,%RDI,1),%YMM4

(226) 0x433c24 LEA	(%R12,%RAX,1),%R14

(226) 0x433c28 VMULPD	(%R13,%R11,8),%YMM14,%YMM0

(226) 0x433c2f VMULPD	-0x8(%R13,%R11,8),%YMM4,%YMM8

(226) 0x433c36 VMOVUPD	(%R13,%R10,8),%YMM3

(226) 0x433c3d LEA	(%R14,%RCX,1),%R12

(226) 0x433c41 MOV	0x50(%RSP),%R14

(226) 0x433c46 VMOVUPD	-0x8(%R13,%R10,8),%YMM9

(226) 0x433c4d VFMADD231PD	(%R8,%R9,8),%YMM3,%YMM0

(226) 0x433c53 MOV	%R12,0x78(%RSP)

(226) 0x433c58 MOV	0x38(%RSP),%R12

(226) 0x433c5d VFMADD231PD	-0x8(%R8,%R9,8),%YMM9,%YMM8

(226) 0x433c64 VADDPD	%YMM8,%YMM0,%YMM12

(226) 0x433c69 MOV	0x78(%RSP),%R9

(226) 0x433c6e ADD	%RCX,%R15

(226) 0x433c71 VMOVQ	%XMM2,%R10

(226) 0x433c76 VMOVQ	%XMM10,%R11

(226) 0x433c7b VMULPD	%YMM24,%YMM12,%YMM13

(226) 0x433c81 ADD	%RAX,%R14

(226) 0x433c84 ADD	%R12,%RAX

(226) 0x433c87 ADD	%RCX,%R14

(226) 0x433c8a ADD	%RCX,%RAX

(226) 0x433c8d VMOVQ	%XMM11,%RCX

(226) 0x433c92 VMOVUPD	%YMM13,(%RCX,%R15,8)

(226) 0x433c98 VMOVUPD	(%R10,%R14,8),%YMM5

(226) 0x433c9e VSUBPD	(%R10,%R9,8),%YMM5,%YMM6

(226) 0x433ca4 VADDPD	%YMM13,%YMM6,%YMM7

(226) 0x433ca9 VMOVUPD	%YMM7,(%R11,%RAX,8)

(226) 0x433caf MOV	%EDX,%EAX

(226) 0x433cb1 AND	$-0x4,%EAX

(226) 0x433cb4 ADD	%EAX,%ESI

(226) 0x433cb6 ADD	%EAX,%EBX

(226) 0x433cb8 AND	$0x3,%EDX

(226) 0x433cbb JE	433f17

(226) 0x433cc1 MOV	0x58(%RSP),%RCX

(226) 0x433cc6 MOV	0x28(%RSP),%R15

(226) 0x433ccb MOVSXD	%ESI,%RAX

(226) 0x433cce MOV	0x68(%RSP),%R14

(226) 0x433cd3 ADD	%RAX,%RCX

(226) 0x433cd6 LEA	(%R15,%RAX,1),%RDX

(226) 0x433cda LEA	(%R14,%RAX,1),%R12

(226) 0x433cde LEA	(%R13,%RCX,8),%R9

(226) 0x433ce3 MOV	0x70(%RSP),%RCX

(226) 0x433ce8 LEA	(%R13,%RDX,8),%RDI

(226) 0x433ced LEA	-0x1(%RSI),%EDX

(226) 0x433cf0 MOVSXD	%EDX,%RDX

(226) 0x433cf3 VMOVQ	%RDI,%XMM14

(226) 0x433cf8 LEA	(%R8,%R12,8),%RDI

(226) 0x433cfc LEA	(%RDX,%R14,1),%R12

(226) 0x433d00 VMOVQ	%XMM14,%R11

(226) 0x433d05 VMOVSD	(%RDI),%XMM3

(226) 0x433d09 VMOVSD	(%R8,%R12,8),%XMM9

(226) 0x433d0f VMOVQ	%XMM11,%R12

(226) 0x433d14 LEA	(%RDX,%RCX,1),%R14

(226) 0x433d18 LEA	(%RCX,%RAX,1),%R10

(226) 0x433d1c MOV	0x58(%RSP),%RCX

(226) 0x433d21 LEA	(%R8,%R10,8),%R10

(226) 0x433d25 VMOVSD	(%R8,%R14,8),%XMM4

(226) 0x433d2b MOV	0x38(%RSP),%R14

(226) 0x433d30 VMOVSD	(%R10),%XMM1

(226) 0x433d35 VMULSD	(%R9),%XMM1,%XMM0

(226) 0x433d3a VFMADD231SD	(%R11),%XMM3,%XMM0

(226) 0x433d3f LEA	(%RDX,%R15,1),%R11

(226) 0x433d43 ADD	%RCX,%RDX

(226) 0x433d46 VMULSD	(%R13,%RDX,8),%XMM4,%XMM8

(226) 0x433d4d MOV	0x20(%RSP),%RDX

(226) 0x433d52 VFMADD231SD	(%R13,%R11,8),%XMM9,%XMM8

(226) 0x433d59 VADDSD	%XMM8,%XMM0,%XMM12

(226) 0x433d5e VMULSD	%XMM23,%XMM12,%XMM13

(226) 0x433d64 LEA	(%RDX,%RAX,1),%R11

(226) 0x433d68 LEA	(%R14,%RAX,1),%RDX

(226) 0x433d6c VMOVQ	%XMM2,%R14

(226) 0x433d71 VMOVSD	%XMM13,(%R12,%R11,8)

(226) 0x433d77 MOV	0x48(%RSP),%R12

(226) 0x433d7c MOV	0x50(%RSP),%R11

(226) 0x433d81 ADD	%RAX,%R11

(226) 0x433d84 ADD	%R12,%RAX

(226) 0x433d87 LEA	0x1(%RBX),%R12D

(226) 0x433d8b VMOVSD	(%R14,%R11,8),%XMM5

(226) 0x433d91 VSUBSD	(%R14,%RAX,8),%XMM5,%XMM6

(226) 0x433d97 VMOVQ	%XMM10,%RAX

(226) 0x433d9c VADDSD	%XMM13,%XMM6,%XMM7

(226) 0x433da1 VMOVSD	%XMM7,(%RAX,%RDX,8)

(226) 0x433da6 MOV	0x30(%RSP),%EDX

(226) 0x433daa CMP	%EDX,%R12D

(226) 0x433dad JAE	433f17

(226) 0x433db3 MOV	0x68(%RSP),%R14

(226) 0x433db8 MOV	0x70(%RSP),%RDX

(226) 0x433dbd VMOVSD	(%R10),%XMM4

(226) 0x433dc2 VMOVSD	(%RDI),%XMM9

(226) 0x433dc6 MOV	0x20(%RSP),%R10

(226) 0x433dcb VMOVQ	%XMM14,%RDI

(226) 0x433dd0 VMULSD	(%R9),%XMM4,%XMM8

(226) 0x433dd5 LEA	0x1(%RSI),%EAX

(226) 0x433dd8 VFMADD231SD	(%RDI),%XMM9,%XMM8

(226) 0x433ddd MOV	0x50(%RSP),%RDI

(226) 0x433de2 CLTQ

(226) 0x433de4 VMOVQ	%XMM11,%R9

(226) 0x433de9 LEA	(%R15,%RAX,1),%R15

(226) 0x433ded LEA	(%RCX,%RAX,1),%RCX

(226) 0x433df1 ADD	$0x2,%EBX

(226) 0x433df4 LEA	(%R13,%R15,8),%R12

(226) 0x433df9 LEA	(%R13,%RCX,8),%R15

(226) 0x433dfe LEA	(%R14,%RAX,1),%R11

(226) 0x433e02 ADD	%RAX,%RDX

(226) 0x433e05 LEA	(%R10,%RAX,1),%RCX

(226) 0x433e09 LEA	(%R8,%RDX,8),%R14

(226) 0x433e0d LEA	(%R8,%R11,8),%R11

(226) 0x433e11 VMOVSD	(%R14),%XMM1

(226) 0x433e16 VMOVSD	(%R11),%XMM0

(226) 0x433e1b VMULSD	(%R15),%XMM1,%XMM3

(226) 0x433e20 VFMADD231SD	(%R12),%XMM0,%XMM3

(226) 0x433e26 VADDSD	%XMM3,%XMM8,%XMM14

(226) 0x433e2a VMULSD	%XMM23,%XMM14,%XMM12

(226) 0x433e30 VMOVSD	%XMM12,(%R9,%RCX,8)

(226) 0x433e36 LEA	(%RDI,%RAX,1),%RCX

(226) 0x433e3a MOV	0x38(%RSP),%R9

(226) 0x433e3f MOV	0x48(%RSP),%RDI

(226) 0x433e44 LEA	(%R9,%RAX,1),%RDX

(226) 0x433e48 ADD	%RDI,%RAX

(226) 0x433e4b VMOVQ	%XMM2,%RDI

(226) 0x433e50 VMOVSD	(%RDI,%RCX,8),%XMM13

(226) 0x433e55 VSUBSD	(%RDI,%RAX,8),%XMM13,%XMM5

(226) 0x433e5a VMOVQ	%XMM10,%RAX

(226) 0x433e5f VADDSD	%XMM12,%XMM5,%XMM6

(226) 0x433e64 VMOVSD	%XMM6,(%RAX,%RDX,8)

(226) 0x433e69 MOV	0x30(%RSP),%EDX

(226) 0x433e6d CMP	%EDX,%EBX

(226) 0x433e6f JAE	433f17

(226) 0x433e75 MOV	0x68(%RSP),%RBX

(226) 0x433e7a MOV	0x70(%RSP),%RAX

(226) 0x433e7f ADD	$0x2,%ESI

(226) 0x433e82 MOV	0x28(%RSP),%RDI

(226) 0x433e87 MOVSXD	%ESI,%RSI

(226) 0x433e8a MOV	0x58(%RSP),%RCX

(226) 0x433e8f VMOVSD	(%R12),%XMM8

(226) 0x433e95 MOV	0x48(%RSP),%R12

(226) 0x433e9a VMOVSD	(%R15),%XMM0

(226) 0x433e9f ADD	%RSI,%R10

(226) 0x433ea2 VMULSD	(%R14),%XMM0,%XMM4

(226) 0x433ea7 VMOVQ	%XMM2,%R15

(226) 0x433eac ADD	%RSI,%R9

(226) 0x433eaf VMOVQ	%XMM10,%R14

(226) 0x433eb4 VFMADD231SD	(%R11),%XMM8,%XMM4

(226) 0x433eb9 ADD	%RSI,%RBX

(226) 0x433ebc ADD	%RSI,%RAX

(226) 0x433ebf ADD	%RSI,%RDI

(226) 0x433ec2 VMOVSD	(%R8,%RAX,8),%XMM7

(226) 0x433ec8 VMOVSD	(%R8,%RBX,8),%XMM1

(226) 0x433ece MOV	0x50(%RSP),%R8

(226) 0x433ed3 ADD	%RSI,%RCX

(226) 0x433ed6 VMULSD	(%R13,%RCX,8),%XMM7,%XMM3

(226) 0x433edd ADD	%RSI,%R12

(226) 0x433ee0 VFMADD231SD	(%R13,%RDI,8),%XMM1,%XMM3

(226) 0x433ee7 VMOVQ	%XMM11,%R13

(226) 0x433eec VADDSD	%XMM4,%XMM3,%XMM9

(226) 0x433ef0 VMULSD	%XMM23,%XMM9,%XMM14

(226) 0x433ef6 VMOVSD	%XMM14,(%R13,%R10,8)

(226) 0x433efd ADD	%RSI,%R8

(226) 0x433f00 VMOVSD	(%R15,%R8,8),%XMM11

(226) 0x433f06 VSUBSD	(%R15,%R12,8),%XMM11,%XMM2

(226) 0x433f0c VADDSD	%XMM14,%XMM2,%XMM12

(226) 0x433f11 VMOVSD	%XMM12,(%R14,%R9,8)

(226) 0x433f17 MOV	0x30(%RSP),%EBX

(226) 0x433f1b INCQ	0x60(%RSP)

(226) 0x433f20 MOV	0x60(%RSP),%RDX

(226) 0x433f25 CMP	%EDX,0x18(%RSP)

(226) 0x433f29 JLE	433f50

(226) 0x433f2b MOV	0x10(%RSP),%ESI

(226) 0x433f2f MOV	0x14(%RSP),%EAX

(226) 0x433f33 MOV	0x1c(%RSP),%EDI

(226) 0x433f37 SUB	%EBX,%ESI

(226) 0x433f39 MOV	%EAX,0x34(%RSP)

(226) 0x433f3d JMP	433890

0x433f42 NOPW	%CS:(%RAX,%RAX,1)

0x433f4d NOPL	(%RAX)

0x433f50 VZEROUPPER

0x433f53 LEA	-0x28(%RBP),%RSP

0x433f57 POP	%RBX

0x433f58 POP	%R12

0x433f5a POP	%R13

0x433f5c POP	%R14

0x433f5e POP	%R15

0x433f60 POP	%RBP

0x433f61 RET

0x433f62 NOPW	%CS:(%RAX,%RAX,1)

0x433f6d NOPL	(%RAX)

(226) 0x433f70 MOV	0x34(%RSP),%ESI

(226) 0x433f74 XOR	%ECX,%ECX

(226) 0x433f76 JMP	433bbd

0x433f7b INC	%R8D

0x433f7e XOR	%EDX,%EDX

0x433f80 JMP	43380d

0x433f85 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.84+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.15+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:167	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:101	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.09+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:167	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:70	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.00 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.25 cycles (1.17x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.00 cycles (1.20x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:170

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	84
nb uops	82
loop length	323
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	1
used zmm registers	1
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.25 cycles
front end	10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	5.25	5.25	5.25	5.25	0.00	1.00	1.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	5.25	5.25	5.25	5.25	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.25
Dispatch	5.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 433790

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x28(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x30(%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RBX),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %ESI,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EAX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433f53 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x3(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433f53 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1c(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 433f7b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7eb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R8D,%EDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDI,%RDX,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA (%R8,%RBX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R9D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R9D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 433f53 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EBX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x14(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
VMOVQ (%R13),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
DIVL 0x1c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ 0x20(%R13),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %R15D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ 0x8(%R13),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x18(%R13),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x30e3d(%RIP),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %R8D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VBROADCASTSD %XMM23,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM23,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R10D,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R11D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43380d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:167-172
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:167-172

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.00 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 10.00 cycles (1.20x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:169
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:170

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	84
nb uops	82
loop length	323
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	1
used zmm registers	1
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.25 cycles
front end	10.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	5.25	5.25	5.25	5.25	0.00	1.00	1.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	5.25	5.25	5.25	5.25	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.25
Dispatch	5.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	8%

Vector efficiency ratios

INT

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 433790

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x34(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x28(%RDI),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x30(%RDI),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x4,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RBX),%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %ESI,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EAX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433f53 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EAX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x3(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433f53 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x1c(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 433f7b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7eb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R8D,%EDI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RDI,%RDX,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA (%R8,%RBX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R9D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R9D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 433f53 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7c3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EBX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x14(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
VMOVQ (%R13),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
DIVL 0x1c(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ 0x20(%R13),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %R15D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ 0x8(%R13),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x18(%R13),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x30e3d(%RIP),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %R8D,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VBROADCASTSD %XMM23,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM23,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB %R10D,%R11D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R14	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R10D,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R11D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 43380d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.9+0x7d>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.12	1.14
▼Loop 226 - advec_mom.cpp:169-172 - exec–	0.00	0.01
○Loop 227 - advec_mom.cpp:170-172 - exec	3.11	1.14

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