OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:146-149 [...]	Coverage (incl. loops): 4.39% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 146 - 149

--------------------------------------------------------------------------------

146: #pragma omp parallel for simd collapse(2)

147:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

148:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

149:         vel1(i, j) = (vel1(i, j) * node_mass_pre(i, j) + mom_flux(i - 1, j + 0) - mom_flux(i, j)) / node_mass_post(i, j);

0x433270 PUSH	%RBP

0x433271 MOV	%RSP,%RBP

0x433274 PUSH	%R15

0x433276 PUSH	%R14

0x433278 PUSH	%R13

0x43327a PUSH	%R12

0x43327c PUSH	%RBX

0x43327d AND	$-0x40,%RSP

0x433281 SUB	$0x40,%RSP

0x433285 MOV	0x28(%RDI),%EAX

0x433288 MOV	0x2c(%RDI),%EDX

0x43328b MOV	0x20(%RDI),%ESI

0x43328e MOV	0x24(%RDI),%ECX

0x433291 ADD	$0x3,%EDX

0x433294 INC	%ESI

0x433296 LEA	0x1(%RAX),%EBX

0x433299 MOV	%EDX,0x1c(%RSP)

0x43329d MOV	%ESI,0x18(%RSP)

0x4332a1 CMP	%EDX,%EBX

0x4332a3 JGE	433753

0x4332a9 MOV	%EDX,%R13D

0x4332ac LEA	0x3(%RCX),%R14D

0x4332b0 SUB	%EBX,%R13D

0x4332b3 CMP	%R14D,%ESI

0x4332b6 JGE	433753

0x4332bc MOV	%RDI,%R15

0x4332bf MOV	%R14D,%EDI

0x4332c2 SUB	%ESI,%EDI

0x4332c4 MOV	%EDI,0x38(%RSP)

0x4332c8 CALL	404630 <omp_get_num_threads@plt>

0x4332cd MOV	%EAX,%R12D

0x4332d0 CALL	404520 <omp_get_thread_num@plt>

0x4332d5 MOV	0x38(%RSP),%R8D

0x4332da XOR	%EDX,%EDX

0x4332dc MOV	%EAX,%ESI

0x4332de IMUL	%R8D,%R13D

0x4332e2 MOV	%R13D,%EAX

0x4332e5 DIV	%R12D

0x4332e8 MOV	%EAX,%R12D

0x4332eb CMP	%EDX,%ESI

0x4332ed JB	43377c

0x4332f3 IMUL	%R12D,%ESI

0x4332f7 ADD	%EDX,%ESI

0x4332f9 LEA	(%R12,%RSI,1),%R9D

0x4332fd MOV	%R9D,0x14(%RSP)

0x433302 CMP	%R9D,%ESI

0x433305 JAE	433753

0x43330b MOV	%ESI,%EAX

0x43330d XOR	%EDX,%EDX

0x43330f MOV	0x18(%RSP),%R10D

0x433314 VMOVQ	(%R15),%XMM3

0x433319 DIVL	0x38(%RSP)

0x43331d VMOVQ	0x10(%R15),%XMM11

0x433323 VMOVQ	0x18(%R15),%XMM10

0x433329 VMOVQ	0x8(%R15),%XMM2

0x43332f ADD	%EDX,%R10D

0x433332 ADD	%EBX,%EAX

0x433334 SUB	%R10D,%R14D

0x433337 MOVSXD	%EAX,%R9

0x43333a MOV	%R10D,0x3c(%RSP)

0x43333f NOP

(224) 0x433340 CMP	%R14D,%R12D

(224) 0x433343 MOV	%R14D,%EDX

(224) 0x433346 CMOVBE	%R12D,%EDX

(224) 0x43334a LEA	(%RSI,%RDX,1),%R12D

(224) 0x43334e CMP	%R12D,%ESI

(224) 0x433351 JAE	433727

(224) 0x433357 VMOVQ	%XMM3,%R11

(224) 0x43335c VMOVQ	%XMM11,%R14

(224) 0x433361 LEA	-0x1(%RDX),%EAX

(224) 0x433364 VMOVQ	%XMM2,%RDI

(224) 0x433369 MOV	(%R11),%RBX

(224) 0x43336c MOV	(%R14),%R15

(224) 0x43336f VMOVQ	%XMM10,%RCX

(224) 0x433374 MOV	(%RDI),%R8

(224) 0x433377 MOV	(%RCX),%R10

(224) 0x43337a VMOVQ	0x10(%R11),%XMM5

(224) 0x433380 VMOVQ	0x10(%R14),%XMM8

(224) 0x433386 VMOVQ	0x10(%RDI),%XMM4

(224) 0x43338b MOV	0x10(%RCX),%R13

(224) 0x43338f IMUL	%R9,%RBX

(224) 0x433393 IMUL	%R9,%R15

(224) 0x433397 IMUL	%R9,%R8

(224) 0x43339b IMUL	%R9,%R10

(224) 0x43339f MOV	%RBX,0x20(%RSP)

(224) 0x4333a4 MOV	%R15,0x28(%RSP)

(224) 0x4333a9 MOV	%R8,0x30(%RSP)

(224) 0x4333ae CMP	$0x6,%EAX

(224) 0x4333b1 JBE	433770

(224) 0x4333b7 MOVSXD	0x3c(%RSP),%R14

(224) 0x4333bc VMOVQ	%XMM8,%RCX

(224) 0x4333c1 LEA	(%R15,%R14,1),%RAX

(224) 0x4333c5 LEA	(%RBX,%R14,1),%R11

(224) 0x4333c9 VMOVQ	%XMM5,%RBX

(224) 0x4333ce LEA	(%RCX,%RAX,8),%R15

(224) 0x4333d2 LEA	(%R10,%R14,1),%RCX

(224) 0x4333d6 ADD	%R8,%R14

(224) 0x4333d9 VMOVQ	%XMM4,%R8

(224) 0x4333de LEA	(%RBX,%R11,8),%RDI

(224) 0x4333e2 LEA	(%R8,%R14,8),%RBX

(224) 0x4333e6 MOV	%EDX,%R14D

(224) 0x4333e9 XOR	%EAX,%EAX

(224) 0x4333eb SHR	$0x3,%R14D

(224) 0x4333ef SAL	$0x6,%R14

(224) 0x4333f3 LEA	-0x40(%R14),%R8

(224) 0x4333f7 SHR	$0x6,%R8

(224) 0x4333fb SAL	$0x3,%RCX

(224) 0x4333ff INC	%R8

(224) 0x433402 LEA	-0x8(%R13,%RCX,1),%R11

(224) 0x433407 ADD	%R13,%RCX

(224) 0x43340a AND	$0x3,%R8D

(224) 0x43340e JE	4334ae

(224) 0x433414 CMP	$0x1,%R8

(224) 0x433418 JE	433477

(224) 0x43341a CMP	$0x2,%R8

(224) 0x43341e JE	433449

(224) 0x433420 VMOVUPD	(%R15),%ZMM1

(224) 0x433426 VMOVUPD	(%RCX),%ZMM7

(224) 0x43342c VFMSUB132PD	(%RDI),%ZMM7,%ZMM1

(224) 0x433432 VADDPD	(%R11),%ZMM1,%ZMM0

(224) 0x433438 VDIVPD	(%RBX),%ZMM0,%ZMM6

(224) 0x43343e MOV	$0x40,%EAX

(224) 0x433443 VMOVUPD	%ZMM6,(%RDI)

(224) 0x433449 VMOVUPD	(%R15,%RAX,1),%ZMM9

(224) 0x433450 VMOVUPD	(%RCX,%RAX,1),%ZMM12

(224) 0x433457 VFMSUB132PD	(%RDI,%RAX,1),%ZMM12,%ZMM9

(224) 0x43345e VADDPD	(%R11,%RAX,1),%ZMM9,%ZMM13

(224) 0x433465 VDIVPD	(%RBX,%RAX,1),%ZMM13,%ZMM14

(224) 0x43346c VMOVUPD	%ZMM14,(%RDI,%RAX,1)

(224) 0x433473 ADD	$0x40,%RAX

(224) 0x433477 VMOVUPD	(%R15,%RAX,1),%ZMM15

(224) 0x43347e VMOVUPD	(%RCX,%RAX,1),%ZMM1

(224) 0x433485 VFMSUB132PD	(%RDI,%RAX,1),%ZMM1,%ZMM15

(224) 0x43348c VADDPD	(%R11,%RAX,1),%ZMM15,%ZMM7

(224) 0x433493 VDIVPD	(%RBX,%RAX,1),%ZMM7,%ZMM0

(224) 0x43349a VMOVUPD	%ZMM0,(%RDI,%RAX,1)

(224) 0x4334a1 ADD	$0x40,%RAX

(224) 0x4334a5 CMP	%R14,%RAX

(224) 0x4334a8 JE	433577

  (225) 0x4334ae VMOVUPD	(%RCX,%RAX,1),%ZMM6

  (225) 0x4334b5 VMOVUPD	(%R15,%RAX,1),%ZMM9

  (225) 0x4334bc VFMSUB132PD	(%RDI,%RAX,1),%ZMM6,%ZMM9

  (225) 0x4334c3 VADDPD	(%R11,%RAX,1),%ZMM9,%ZMM12

  (225) 0x4334ca VDIVPD	(%RBX,%RAX,1),%ZMM12,%ZMM13

  (225) 0x4334d1 VMOVUPD	%ZMM13,(%RDI,%RAX,1)

  (225) 0x4334d8 VMOVUPD	0x40(%RCX,%RAX,1),%ZMM15

  (225) 0x4334e0 VMOVUPD	0x40(%R15,%RAX,1),%ZMM14

  (225) 0x4334e8 VFMSUB132PD	0x40(%RDI,%RAX,1),%ZMM15,%ZMM14

  (225) 0x4334f0 VADDPD	0x40(%R11,%RAX,1),%ZMM14,%ZMM1

  (225) 0x4334f8 VDIVPD	0x40(%RBX,%RAX,1),%ZMM1,%ZMM7

  (225) 0x433500 VMOVUPD	%ZMM7,0x40(%RDI,%RAX,1)

  (225) 0x433508 VMOVUPD	0x80(%R15,%RAX,1),%ZMM0

  (225) 0x433510 VMOVUPD	0x80(%RCX,%RAX,1),%ZMM9

  (225) 0x433518 VFMSUB132PD	0x80(%RDI,%RAX,1),%ZMM9,%ZMM0

  (225) 0x433520 VADDPD	0x80(%R11,%RAX,1),%ZMM0,%ZMM6

  (225) 0x433528 VDIVPD	0x80(%RBX,%RAX,1),%ZMM6,%ZMM12

  (225) 0x433530 VMOVUPD	%ZMM12,0x80(%RDI,%RAX,1)

  (225) 0x433538 VMOVUPD	0xc0(%R15,%RAX,1),%ZMM13

  (225) 0x433540 VMOVUPD	0xc0(%RCX,%RAX,1),%ZMM14

  (225) 0x433548 VFMSUB132PD	0xc0(%RDI,%RAX,1),%ZMM14,%ZMM13

  (225) 0x433550 VADDPD	0xc0(%R11,%RAX,1),%ZMM13,%ZMM15

  (225) 0x433558 VDIVPD	0xc0(%RBX,%RAX,1),%ZMM15,%ZMM1

  (225) 0x433560 VMOVUPD	%ZMM1,0xc0(%RDI,%RAX,1)

  (225) 0x433568 ADD	$0x100,%RAX

  (225) 0x43356e CMP	%R14,%RAX

  (225) 0x433571 JNE	4334ae

(224) 0x433577 MOV	0x3c(%RSP),%ECX

(224) 0x43357b MOV	%EDX,%R15D

(224) 0x43357e AND	$-0x8,%R15D

(224) 0x433582 ADD	%R15D,%ESI

(224) 0x433585 ADD	%R15D,%ECX

(224) 0x433588 TEST	$0x7,%DL

(224) 0x43358b JE	433724

(224) 0x433591 SUB	%R15D,%EDX

(224) 0x433594 LEA	-0x1(%RDX),%EDI

(224) 0x433597 CMP	$0x2,%EDI

(224) 0x43359a JBE	433618

(224) 0x43359c MOVSXD	0x3c(%RSP),%RDI

(224) 0x4335a1 MOV	0x20(%RSP),%R11

(224) 0x4335a6 VMOVQ	%XMM5,%RBX

(224) 0x4335ab MOV	0x30(%RSP),%RAX

(224) 0x4335b0 LEA	(%R11,%RDI,1),%R14

(224) 0x4335b4 LEA	(%R10,%RDI,1),%R8

(224) 0x4335b8 ADD	%R15,%R14

(224) 0x4335bb ADD	%R15,%R8

(224) 0x4335be LEA	(%RBX,%R14,8),%R11

(224) 0x4335c2 MOV	0x28(%RSP),%RBX

(224) 0x4335c7 LEA	(%RAX,%RDI,1),%R14

(224) 0x4335cb VMOVUPD	-0x8(%R13,%R8,8),%YMM0

(224) 0x4335d2 ADD	%R15,%R14

(224) 0x4335d5 VMOVUPD	(%R11),%YMM7

(224) 0x4335da ADD	%RBX,%RDI

(224) 0x4335dd ADD	%R15,%RDI

(224) 0x4335e0 VMOVQ	%XMM8,%R15

(224) 0x4335e5 VFMADD132PD	(%R15,%RDI,8),%YMM0,%YMM7

(224) 0x4335eb VMOVQ	%XMM4,%RDI

(224) 0x4335f0 VSUBPD	(%R13,%R8,8),%YMM7,%YMM9

(224) 0x4335f7 VDIVPD	(%RDI,%R14,8),%YMM9,%YMM6

(224) 0x4335fd VMOVUPD	%YMM6,(%R11)

(224) 0x433602 MOV	%EDX,%R11D

(224) 0x433605 AND	$-0x4,%R11D

(224) 0x433609 ADD	%R11D,%ECX

(224) 0x43360c ADD	%R11D,%ESI

(224) 0x43360f AND	$0x3,%EDX

(224) 0x433612 JE	433724

(224) 0x433618 MOV	0x20(%RSP),%RBX

(224) 0x43361d MOVSXD	%ECX,%RAX

(224) 0x433620 MOV	0x28(%RSP),%R11

(224) 0x433625 VMOVQ	%XMM5,%R8

(224) 0x43362a LEA	-0x1(%RCX),%R15D

(224) 0x43362e LEA	(%RBX,%RAX,1),%RDX

(224) 0x433632 LEA	(%R11,%RAX,1),%RDI

(224) 0x433636 LEA	(%R8,%RDX,8),%R14

(224) 0x43363a MOVSXD	%R15D,%RDX

(224) 0x43363d MOV	0x30(%RSP),%R15

(224) 0x433642 VMOVQ	%XMM8,%R8

(224) 0x433647 VMOVSD	(%R8,%RDI,8),%XMM12

(224) 0x43364d ADD	%R10,%RDX

(224) 0x433650 LEA	(%R10,%RAX,1),%RDI

(224) 0x433654 VMOVQ	%XMM4,%R8

(224) 0x433659 VMOVSD	(%R13,%RDX,8),%XMM13

(224) 0x433660 LEA	(%R13,%RDI,8),%RDX

(224) 0x433665 VFMADD132SD	(%R14),%XMM13,%XMM12

(224) 0x43366a VSUBSD	(%RDX),%XMM12,%XMM14

(224) 0x43366e ADD	%R15,%RAX

(224) 0x433671 VDIVSD	(%R8,%RAX,8),%XMM14,%XMM15

(224) 0x433677 LEA	0x1(%RSI),%EAX

(224) 0x43367a VMOVSD	%XMM15,(%R14)

(224) 0x43367f CMP	%R12D,%EAX

(224) 0x433682 JAE	433724

(224) 0x433688 LEA	0x1(%RCX),%EAX

(224) 0x43368b VMOVQ	%XMM5,%RDI

(224) 0x433690 ADD	$0x2,%ESI

(224) 0x433693 CLTQ

(224) 0x433695 LEA	(%RBX,%RAX,1),%R14

(224) 0x433699 LEA	(%R10,%RAX,1),%R8

(224) 0x43369d LEA	(%RDI,%R14,8),%RDI

(224) 0x4336a1 LEA	(%R13,%R8,8),%R14

(224) 0x4336a6 VMOVQ	%XMM8,%R8

(224) 0x4336ab VMOVQ	%R14,%XMM1

(224) 0x4336b0 LEA	(%R11,%RAX,1),%R14

(224) 0x4336b4 ADD	%R15,%RAX

(224) 0x4336b7 VMOVSD	(%R8,%R14,8),%XMM7

(224) 0x4336bd VMOVQ	%XMM1,%R14

(224) 0x4336c2 VMOVSD	(%R14),%XMM0

(224) 0x4336c7 VFMSUB132SD	(%RDI),%XMM0,%XMM7

(224) 0x4336cc VADDSD	(%RDX),%XMM7,%XMM9

(224) 0x4336d0 VMOVQ	%XMM4,%RDX

(224) 0x4336d5 VDIVSD	(%RDX,%RAX,8),%XMM9,%XMM6

(224) 0x4336da VMOVSD	%XMM6,(%RDI)

(224) 0x4336de CMP	%R12D,%ESI

(224) 0x4336e1 JAE	433724

(224) 0x4336e3 ADD	$0x2,%ECX

(224) 0x4336e6 VMOVQ	%XMM5,%RSI

(224) 0x4336eb MOVSXD	%ECX,%RCX

(224) 0x4336ee ADD	%RCX,%R10

(224) 0x4336f1 ADD	%RCX,%RBX

(224) 0x4336f4 ADD	%RCX,%R11

(224) 0x4336f7 ADD	%RCX,%R15

(224) 0x4336fa VMOVSD	(%R13,%R10,8),%XMM5

(224) 0x433701 LEA	(%RSI,%RBX,8),%RBX

(224) 0x433705 VMOVQ	%XMM4,%R10

(224) 0x43370a VMOVSD	(%R8,%R11,8),%XMM8

(224) 0x433710 VFMSUB132SD	(%RBX),%XMM5,%XMM8

(224) 0x433715 VADDSD	(%R14),%XMM8,%XMM12

(224) 0x43371a VDIVSD	(%R10,%R15,8),%XMM12,%XMM4

(224) 0x433720 VMOVSD	%XMM4,(%RBX)

(224) 0x433724 MOV	%R12D,%ESI

(224) 0x433727 INC	%R9

(224) 0x43372a CMP	%R9D,0x1c(%RSP)

(224) 0x43372f JLE	433750

(224) 0x433731 MOV	0x14(%RSP),%R12D

(224) 0x433736 MOV	0x18(%RSP),%R11D

(224) 0x43373b MOV	0x38(%RSP),%R14D

(224) 0x433740 SUB	%ESI,%R12D

(224) 0x433743 MOV	%R11D,0x3c(%RSP)

(224) 0x433748 JMP	433340

0x43374d NOPL	(%RAX)

0x433750 VZEROUPPER

0x433753 LEA	-0x28(%RBP),%RSP

0x433757 POP	%RBX

0x433758 POP	%R12

0x43375a POP	%R13

0x43375c POP	%R14

0x43375e POP	%R15

0x433760 POP	%RBP

0x433761 RET

0x433762 NOPW	%CS:(%RAX,%RAX,1)

0x43376d NOPL	(%RAX)

(224) 0x433770 MOV	0x3c(%RSP),%ECX

(224) 0x433774 XOR	%R15D,%R15D

(224) 0x433777 JMP	433591

0x43377c INC	%R12D

0x43377f XOR	%EDX,%EDX

0x433781 JMP	4332f3

0x433786 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.86+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.25 cycles (1.30x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:149

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	77
nb uops	76
loop length	263
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.50
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	7%
load	9%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (5.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 433270

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ESI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 433753 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 433753 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x38(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R8D,%R13D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 43377c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x50c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R12D,%ESI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R12,%RSI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R9D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 433753 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x18(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%R15),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x38(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x10(%R15),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R15),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x8(%R15),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %R10D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R10D,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4332f3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:146-149
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:146-149

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.25 cycles (1.30x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:148
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:149

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 60 bytes. The binary function is storing 20 bytes.

General properties

nb instructions	77
nb uops	76
loop length	263
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.50 cycles
front end	9.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.50
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	7%
load	9%
store	6%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (5.00 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (1.67 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 433270

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
INC %ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %EDX,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ESI,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %EDX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 433753 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x3(%RCX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R14D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 433753 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %ESI,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %EDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV 0x38(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
IMUL %R8D,%R13D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JB 43377c <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x50c>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R12D,%ESI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R12,%RSI,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R9D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R9D,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 433753 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x4e3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x18(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ (%R15),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x38(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x10(%R15),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x18(%R15),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x8(%R15),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %R10D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R10D,0x3c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 4332f3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.7+0x83>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.39	1.61
▼Loop 224 - advec_mom.cpp:148-149 - exec–	0.00	0.00
○Loop 225 - advec_mom.cpp:149-149 - exec	4.39	1.61

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code