OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:85-88 [...]	Coverage (incl. loops): 1.34% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 85 - 88

--------------------------------------------------------------------------------

85: #pragma omp parallel for simd collapse(2)

86:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

87:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

88:           node_flux(i, j) = 0.25 * (mass_flux_x(i + 0, j - 1) + mass_flux_x(i, j) + mass_flux_x(i + 1, j - 1) + mass_flux_x(i + 1, j + 0));

0x432d80 PUSH	%RBP

0x432d81 MOV	%RSP,%RBP

0x432d84 PUSH	%R15

0x432d86 PUSH	%R14

0x432d88 PUSH	%R13

0x432d8a PUSH	%R12

0x432d8c PUSH	%RBX

0x432d8d AND	$-0x40,%RSP

0x432d91 SUB	$0x40,%RSP

0x432d95 MOV	0x18(%RDI),%EAX

0x432d98 MOV	0x1c(%RDI),%EDX

0x432d9b MOV	0x10(%RDI),%ECX

0x432d9e MOV	0x14(%RDI),%ESI

0x432da1 MOV	%RDI,0x38(%RSP)

0x432da6 ADD	$0x3,%EDX

0x432da9 DEC	%ECX

0x432dab LEA	0x1(%RAX),%EBX

0x432dae MOV	%EDX,0x30(%RSP)

0x432db2 MOV	%ECX,0x24(%RSP)

0x432db6 CMP	%EDX,%EBX

0x432db8 JGE	433233

0x432dbe MOV	%EDX,%R14D

0x432dc1 LEA	0x4(%RSI),%R15D

0x432dc5 SUB	%EBX,%R14D

0x432dc8 CMP	%R15D,%ECX

0x432dcb JGE	433233

0x432dd1 MOV	%R15D,%R13D

0x432dd4 SUB	%ECX,%R13D

0x432dd7 IMUL	%R13D,%R14D

0x432ddb MOV	%R13D,0x20(%RSP)

0x432de0 CALL	404630 <omp_get_num_threads@plt>

0x432de5 MOV	%EAX,%R12D

0x432de8 CALL	404520 <omp_get_thread_num@plt>

0x432ded XOR	%EDX,%EDX

0x432def MOV	0x38(%RSP),%RDI

0x432df4 MOV	%EAX,%ECX

0x432df6 MOV	%R14D,%EAX

0x432df9 DIV	%R12D

0x432dfc CMP	%EDX,%ECX

0x432dfe MOV	%EAX,%R8D

0x432e01 JB	43325d

0x432e07 IMUL	%R8D,%ECX

0x432e0b ADD	%EDX,%ECX

0x432e0d LEA	(%R8,%RCX,1),%R9D

0x432e11 MOV	%R9D,0x1c(%RSP)

0x432e16 CMP	%R9D,%ECX

0x432e19 JAE	433233

0x432e1f MOV	%ECX,%EAX

0x432e21 XOR	%EDX,%EDX

0x432e23 MOV	0x24(%RSP),%R10D

0x432e28 VMOVSD	0x31870(%RIP),%XMM10

0x432e30 DIVL	0x20(%RSP)

0x432e34 VMOVQ	(%RDI),%XMM4

0x432e38 VMOVQ	0x8(%RDI),%XMM3

0x432e3d VBROADCASTSD	%XMM10,%YMM11

0x432e42 VBROADCASTSD	%XMM10,%ZMM6

0x432e48 ADD	%EDX,%R10D

0x432e4b ADD	%EBX,%EAX

0x432e4d SUB	%R10D,%R15D

0x432e50 MOVSXD	%EAX,%R9

0x432e53 MOV	%R8D,%EAX

0x432e56 MOV	%R10D,0x38(%RSP)

0x432e5b MOV	%R15D,%EDI

0x432e5e XCHG	%AX,%AX

(222) 0x432e60 CMP	%EDI,%EAX

(222) 0x432e62 CMOVA	%EDI,%EAX

(222) 0x432e65 LEA	(%RCX,%RAX,1),%R11D

(222) 0x432e69 MOV	%R11D,0x34(%RSP)

(222) 0x432e6e CMP	%R11D,%ECX

(222) 0x432e71 JAE	433209

(222) 0x432e77 VMOVQ	%XMM3,%R13

(222) 0x432e7c VMOVQ	%XMM4,%RBX

(222) 0x432e81 LEA	-0x1(%R9),%R14D

(222) 0x432e85 LEA	-0x1(%RAX),%R12D

(222) 0x432e89 VMOVQ	0x10(%R13),%XMM5

(222) 0x432e8f MOV	(%R13),%R13

(222) 0x432e93 MOV	(%RBX),%RDI

(222) 0x432e96 MOVSXD	%R14D,%RSI

(222) 0x432e99 MOV	0x10(%RBX),%R15

(222) 0x432e9d IMUL	%R9,%R13

(222) 0x432ea1 IMUL	%RDI,%RSI

(222) 0x432ea5 IMUL	%R9,%RDI

(222) 0x432ea9 MOV	%R13,0x28(%RSP)

(222) 0x432eae CMP	$0x6,%R12D

(222) 0x432eb2 JBE	433250

(222) 0x432eb8 MOVSXD	0x38(%RSP),%R8

(222) 0x432ebd LEA	(%RSI,%R8,1),%RDX

(222) 0x432ec1 LEA	(%RDI,%R8,1),%R11

(222) 0x432ec5 ADD	%R13,%R8

(222) 0x432ec8 VMOVQ	%XMM5,%R13

(222) 0x432ecd SAL	$0x3,%RDX

(222) 0x432ed1 SAL	$0x3,%R11

(222) 0x432ed5 LEA	(%R15,%RDX,1),%RBX

(222) 0x432ed9 LEA	(%R15,%R11,1),%R14

(222) 0x432edd LEA	0x8(%R15,%RDX,1),%R12

(222) 0x432ee2 LEA	0x8(%R15,%R11,1),%RDX

(222) 0x432ee7 MOV	%EAX,%R11D

(222) 0x432eea LEA	(%R13,%R8,8),%R13

(222) 0x432eef XOR	%R8D,%R8D

(222) 0x432ef2 SHR	$0x3,%R11D

(222) 0x432ef6 SAL	$0x6,%R11

(222) 0x432efa LEA	-0x40(%R11),%R10

(222) 0x432efe SHR	$0x6,%R10

(222) 0x432f02 INC	%R10

(222) 0x432f05 AND	$0x3,%R10D

(222) 0x432f09 JE	432fbe

(222) 0x432f0f CMP	$0x1,%R10

(222) 0x432f13 JE	432f81

(222) 0x432f15 CMP	$0x2,%R10

(222) 0x432f19 JE	432f4d

(222) 0x432f1b VMOVUPD	(%RBX),%ZMM0

(222) 0x432f21 VMOVUPD	(%R12),%ZMM12

(222) 0x432f28 VADDPD	(%R14),%ZMM0,%ZMM1

(222) 0x432f2e MOV	$0x40,%R8D

(222) 0x432f34 VADDPD	(%RDX),%ZMM12,%ZMM2

(222) 0x432f3a VADDPD	%ZMM2,%ZMM1,%ZMM7

(222) 0x432f40 VMULPD	%ZMM6,%ZMM7,%ZMM8

(222) 0x432f46 VMOVUPD	%ZMM8,(%R13)

(222) 0x432f4d VMOVUPD	(%RBX,%R8,1),%ZMM9

(222) 0x432f54 VMOVUPD	(%R12,%R8,1),%ZMM14

(222) 0x432f5b VADDPD	(%R14,%R8,1),%ZMM9,%ZMM13

(222) 0x432f62 VADDPD	(%RDX,%R8,1),%ZMM14,%ZMM15

(222) 0x432f69 VADDPD	%ZMM15,%ZMM13,%ZMM0

(222) 0x432f6f VMULPD	%ZMM6,%ZMM0,%ZMM1

(222) 0x432f75 VMOVUPD	%ZMM1,(%R13,%R8,1)

(222) 0x432f7d ADD	$0x40,%R8

(222) 0x432f81 VMOVUPD	(%RBX,%R8,1),%ZMM12

(222) 0x432f88 VMOVUPD	(%R12,%R8,1),%ZMM7

(222) 0x432f8f VADDPD	(%R14,%R8,1),%ZMM12,%ZMM2

(222) 0x432f96 VADDPD	(%RDX,%R8,1),%ZMM7,%ZMM8

(222) 0x432f9d VADDPD	%ZMM8,%ZMM2,%ZMM9

(222) 0x432fa3 VMULPD	%ZMM6,%ZMM9,%ZMM13

(222) 0x432fa9 VMOVUPD	%ZMM13,(%R13,%R8,1)

(222) 0x432fb1 ADD	$0x40,%R8

(222) 0x432fb5 CMP	%R11,%R8

(222) 0x432fb8 JE	43309a

  (223) 0x432fbe VMOVUPD	(%RBX,%R8,1),%ZMM14

  (223) 0x432fc5 VMOVUPD	(%R12,%R8,1),%ZMM0

  (223) 0x432fcc VADDPD	(%R14,%R8,1),%ZMM14,%ZMM15

  (223) 0x432fd3 VADDPD	(%RDX,%R8,1),%ZMM0,%ZMM1

  (223) 0x432fda VADDPD	%ZMM1,%ZMM15,%ZMM12

  (223) 0x432fe0 VMULPD	%ZMM6,%ZMM12,%ZMM2

  (223) 0x432fe6 VMOVUPD	%ZMM2,(%R13,%R8,1)

  (223) 0x432fee VMOVUPD	0x40(%RBX,%R8,1),%ZMM7

  (223) 0x432ff6 VMOVUPD	0x40(%R12,%R8,1),%ZMM9

  (223) 0x432ffe VADDPD	0x40(%R14,%R8,1),%ZMM7,%ZMM8

  (223) 0x433006 VADDPD	0x40(%RDX,%R8,1),%ZMM9,%ZMM13

  (223) 0x43300e VADDPD	%ZMM13,%ZMM8,%ZMM14

  (223) 0x433014 VMULPD	%ZMM6,%ZMM14,%ZMM15

  (223) 0x43301a VMOVUPD	%ZMM15,0x40(%R13,%R8,1)

  (223) 0x433022 VMOVUPD	0x80(%RBX,%R8,1),%ZMM0

  (223) 0x43302a VMOVUPD	0x80(%R12,%R8,1),%ZMM12

  (223) 0x433032 VADDPD	0x80(%R14,%R8,1),%ZMM0,%ZMM1

  (223) 0x43303a VADDPD	0x80(%RDX,%R8,1),%ZMM12,%ZMM2

  (223) 0x433042 VADDPD	%ZMM2,%ZMM1,%ZMM7

  (223) 0x433048 VMULPD	%ZMM6,%ZMM7,%ZMM8

  (223) 0x43304e VMOVUPD	%ZMM8,0x80(%R13,%R8,1)

  (223) 0x433056 VMOVUPD	0xc0(%RBX,%R8,1),%ZMM9

  (223) 0x43305e VMOVUPD	0xc0(%R12,%R8,1),%ZMM14

  (223) 0x433066 VADDPD	0xc0(%R14,%R8,1),%ZMM9,%ZMM13

  (223) 0x43306e VADDPD	0xc0(%RDX,%R8,1),%ZMM14,%ZMM15

  (223) 0x433076 VADDPD	%ZMM15,%ZMM13,%ZMM0

  (223) 0x43307c VMULPD	%ZMM6,%ZMM0,%ZMM1

  (223) 0x433082 VMOVUPD	%ZMM1,0xc0(%R13,%R8,1)

  (223) 0x43308a ADD	$0x100,%R8

  (223) 0x433091 CMP	%R11,%R8

  (223) 0x433094 JNE	432fbe

(222) 0x43309a MOV	0x38(%RSP),%EBX

(222) 0x43309e MOV	%EAX,%R8D

(222) 0x4330a1 AND	$-0x8,%R8D

(222) 0x4330a5 ADD	%R8D,%ECX

(222) 0x4330a8 LEA	(%R8,%RBX,1),%R10D

(222) 0x4330ac TEST	$0x7,%AL

(222) 0x4330ae JE	433205

(222) 0x4330b4 SUB	%R8D,%EAX

(222) 0x4330b7 LEA	-0x1(%RAX),%R14D

(222) 0x4330bb CMP	$0x2,%R14D

(222) 0x4330bf JBE	433124

(222) 0x4330c1 MOVSXD	0x38(%RSP),%R12

(222) 0x4330c6 MOV	0x28(%RSP),%R11

(222) 0x4330cb MOV	%EAX,%EBX

(222) 0x4330cd AND	$-0x4,%EBX

(222) 0x4330d0 ADD	%EBX,%R10D

(222) 0x4330d3 ADD	%EBX,%ECX

(222) 0x4330d5 LEA	(%RDI,%R12,1),%R13

(222) 0x4330d9 LEA	(%RSI,%R12,1),%RDX

(222) 0x4330dd ADD	%R11,%R12

(222) 0x4330e0 ADD	%R8,%R13

(222) 0x4330e3 ADD	%R8,%RDX

(222) 0x4330e6 ADD	%R8,%R12

(222) 0x4330e9 VMOVQ	%XMM5,%R8

(222) 0x4330ee SAL	$0x3,%R13

(222) 0x4330f2 VMOVUPD	0x8(%R15,%R13,1),%YMM12

(222) 0x4330f9 VMOVUPD	(%R15,%R13,1),%YMM2

(222) 0x4330ff VADDPD	0x8(%R15,%RDX,8),%YMM12,%YMM7

(222) 0x433106 VADDPD	(%R15,%RDX,8),%YMM2,%YMM8

(222) 0x43310c VADDPD	%YMM8,%YMM7,%YMM9

(222) 0x433111 VMULPD	%YMM11,%YMM9,%YMM13

(222) 0x433116 VMOVUPD	%YMM13,(%R8,%R12,8)

(222) 0x43311c TEST	$0x3,%AL

(222) 0x43311e JE	433205

(222) 0x433124 LEA	0x1(%R10),%R14D

(222) 0x433128 MOVSXD	%R10D,%RAX

(222) 0x43312b MOVSXD	%R14D,%RDX

(222) 0x43312e MOV	0x28(%RSP),%R14

(222) 0x433133 LEA	(%RDI,%RAX,1),%RBX

(222) 0x433137 LEA	(%RDX,%RSI,1),%R12

(222) 0x43313b LEA	(%RDX,%RDI,1),%R13

(222) 0x43313f VMOVSD	(%R15,%RBX,8),%XMM14

(222) 0x433145 LEA	(%R15,%R12,8),%R8

(222) 0x433149 LEA	(%R15,%R13,8),%R11

(222) 0x43314d LEA	0x1(%RCX),%R13D

(222) 0x433151 VMOVSD	(%R8),%XMM0

(222) 0x433156 VADDSD	(%R11),%XMM0,%XMM1

(222) 0x43315b LEA	(%R14,%RAX,1),%R12

(222) 0x43315f ADD	%RSI,%RAX

(222) 0x433162 VADDSD	(%R15,%RAX,8),%XMM14,%XMM15

(222) 0x433168 VMOVQ	%XMM5,%RAX

(222) 0x43316d VADDSD	%XMM1,%XMM15,%XMM12

(222) 0x433171 VMULSD	%XMM10,%XMM12,%XMM7

(222) 0x433176 VMOVSD	%XMM7,(%RAX,%R12,8)

(222) 0x43317c MOV	0x34(%RSP),%R12D

(222) 0x433181 CMP	%R12D,%R13D

(222) 0x433184 JAE	433205

(222) 0x433186 LEA	0x2(%R10),%EAX

(222) 0x43318a VMOVSD	(%R11),%XMM2

(222) 0x43318f ADD	%R14,%RDX

(222) 0x433192 VADDSD	(%R8),%XMM2,%XMM8

(222) 0x433197 CLTQ

(222) 0x433199 VMOVQ	%XMM5,%R8

(222) 0x43319e ADD	$0x2,%ECX

(222) 0x4331a1 LEA	(%RSI,%RAX,1),%RBX

(222) 0x4331a5 LEA	(%RDI,%RAX,1),%R13

(222) 0x4331a9 LEA	(%R15,%RBX,8),%RBX

(222) 0x4331ad LEA	(%R15,%R13,8),%R13

(222) 0x4331b1 VMOVSD	(%R13),%XMM9

(222) 0x4331b7 VADDSD	(%RBX),%XMM9,%XMM13

(222) 0x4331bb VADDSD	%XMM13,%XMM8,%XMM14

(222) 0x4331c0 VMULSD	%XMM10,%XMM14,%XMM15

(222) 0x4331c5 VMOVSD	%XMM15,(%R8,%RDX,8)

(222) 0x4331cb CMP	%R12D,%ECX

(222) 0x4331ce JAE	433205

(222) 0x4331d0 ADD	$0x3,%R10D

(222) 0x4331d4 ADD	%RAX,%R14

(222) 0x4331d7 VMOVSD	(%RBX),%XMM1

(222) 0x4331db VADDSD	(%R13),%XMM1,%XMM7

(222) 0x4331e1 MOVSXD	%R10D,%RCX

(222) 0x4331e4 ADD	%RCX,%RSI

(222) 0x4331e7 ADD	%RDI,%RCX

(222) 0x4331ea VMOVSD	(%R15,%RSI,8),%XMM0

(222) 0x4331f0 VADDSD	(%R15,%RCX,8),%XMM0,%XMM12

(222) 0x4331f6 VADDSD	%XMM7,%XMM12,%XMM2

(222) 0x4331fa VMULSD	%XMM10,%XMM2,%XMM8

(222) 0x4331ff VMOVSD	%XMM8,(%R8,%R14,8)

(222) 0x433205 MOV	0x34(%RSP),%ECX

(222) 0x433209 INC	%R9

(222) 0x43320c CMP	%R9D,0x30(%RSP)

(222) 0x433211 JLE	433230

(222) 0x433213 MOV	0x1c(%RSP),%EAX

(222) 0x433217 MOV	0x24(%RSP),%ESI

(222) 0x43321b MOV	0x20(%RSP),%EDI

(222) 0x43321f SUB	%ECX,%EAX

(222) 0x433221 MOV	%ESI,0x38(%RSP)

(222) 0x433225 JMP	432e60

0x43322a NOPW	(%RAX,%RAX,1)

0x433230 VZEROUPPER

0x433233 LEA	-0x28(%RBP),%RSP

0x433237 POP	%RBX

0x433238 POP	%R12

0x43323a POP	%R13

0x43323c POP	%R14

0x43323e POP	%R15

0x433240 POP	%RBP

0x433241 RET

0x433242 NOPW	%CS:(%RAX,%RAX,1)

0x43324d NOPL	(%RAX)

(222) 0x433250 MOV	0x38(%RSP),%R10D

(222) 0x433255 XOR	%R8D,%R8D

(222) 0x433258 JMP	4330b4

0x43325d INC	%R8D

0x433260 XOR	%EDX,%EDX

0x433262 JMP	432e07

0x433267 NOPW	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.89+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.15+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:95	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:70	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.11+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:95	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:101	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:85-88
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:85-88

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.63 cycles (1.25x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:88

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	80
nb uops	79
loop length	281
used x86 registers	15
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	1
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.88 cycles
front end	9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	1.00	1.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.88
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	7%
load	8%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (4.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 432d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x1c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV 0x10(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x14(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
DEC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %ECX,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EDX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RSI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 43325d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4dd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R8D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%RCX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R9D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R9D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 433233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x24(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
VMOVSD 0x31870(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
DIVL 0x20(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ (%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x8(%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB %R10D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 432e07 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:85-88
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:85-88

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.63 cycles (7.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.63 cycles (1.25x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:87
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:88

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	80
nb uops	79
loop length	281
used x86 registers	15
used mmx registers	0
used xmm registers	3
used ymm registers	1
used zmm registers	1
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.88 cycles
front end	9.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	1.00	1.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.50	4.50	4.50	4.50	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.88
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	7%

Vector efficiency ratios

INT

all	7%
load	8%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

1% of peak load performance is reached (4.67 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 432d80

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x1c(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
MOV 0x10(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x14(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
DEC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %ECX,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EDX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EDX,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RSI),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 433233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 43325d <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4dd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R8D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA (%R8,%RCX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R9D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R9D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 433233 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x4b3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
MOV 0x24(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
VMOVSD 0x31870(%RIP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
DIVL 0x20(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ (%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x8(%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM10,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
SUB %R10D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOVSXD %EAX,%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10D,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R15D,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XCHG %AX,%AX	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	scal (6.3%)
JMP 432e07 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.4+0x87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	1.34	0.49
▼Loop 222 - advec_mom.cpp:87-88 - exec–	0.00	0.01
○Loop 223 - advec_mom.cpp:88-88 - exec	1.33	0.49

Report Configuration

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Vectorization

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Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code