OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:95-100 [...]	Coverage (incl. loops): 3.11% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 95 - 100

--------------------------------------------------------------------------------

95: #pragma omp parallel for simd collapse(2)

96:       for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

97:         for (int i = (x_min - 1 + 1); i < (x_max + 2 + 2); i++) {

98:           node_mass_post(i, j) = 0.25 * (density1(i + 0, j - 1) * post_vol(i + 0, j - 1) + density1(i, j) * post_vol(i, j) +

99:                                          density1(i - 1, j - 1) * post_vol(i - 1, j - 1) + density1(i - 1, j + 0) * post_vol(i - 1, j + 0));

100:           node_mass_pre(i, j) = node_mass_post(i, j) - node_flux(i - 1, j + 0) + node_flux(i, j);

0x4325b0 PUSH	%RBP

0x4325b1 MOV	%RSP,%RBP

0x4325b4 PUSH	%R15

0x4325b6 PUSH	%R14

0x4325b8 PUSH	%R13

0x4325ba PUSH	%R12

0x4325bc PUSH	%RBX

0x4325bd MOV	%RDI,%R13

0x4325c0 AND	$-0x40,%RSP

0x4325c4 ADD	$-0x80,%RSP

0x4325c8 MOV	0x30(%R13),%EAX

0x4325cc MOV	0x34(%R13),%EDX

0x4325d0 MOV	0x28(%RDI),%EDI

0x4325d3 MOV	0x2c(%R13),%EBX

0x4325d7 ADD	$0x3,%EDX

0x4325da LEA	0x1(%RAX),%R14D

0x4325de MOV	%EDI,0x20(%RSP)

0x4325e2 MOV	%EDX,0x24(%RSP)

0x4325e6 CMP	%EDX,%R14D

0x4325e9 JGE	432d43

0x4325ef LEA	0x4(%RBX),%R15D

0x4325f3 MOV	%EDX,%EBX

0x4325f5 SUB	%R14D,%EBX

0x4325f8 CMP	%R15D,%EDI

0x4325fb JGE	432d43

0x432601 MOV	%R15D,%ECX

0x432604 SUB	%EDI,%ECX

0x432606 MOV	%ECX,0x30(%RSP)

0x43260a CALL	404630 <omp_get_num_threads@plt>

0x43260f MOV	%EAX,%R12D

0x432612 CALL	404520 <omp_get_thread_num@plt>

0x432617 XOR	%EDX,%EDX

0x432619 MOV	%EAX,%ESI

0x43261b MOV	0x30(%RSP),%EAX

0x43261f IMUL	%EBX,%EAX

0x432622 DIV	%R12D

0x432625 MOV	%EAX,%R8D

0x432628 CMP	%EDX,%ESI

0x43262a JB	432d6b

0x432630 IMUL	%R8D,%ESI

0x432634 LEA	(%RSI,%RDX,1),%EBX

0x432637 LEA	(%R8,%RBX,1),%R9D

0x43263b MOV	%R9D,0x1c(%RSP)

0x432640 CMP	%R9D,%EBX

0x432643 JAE	432d43

0x432649 MOV	%EBX,%EAX

0x43264b XOR	%EDX,%EDX

0x43264d MOV	0x20(%RSP),%R10D

0x432652 VMOVQ	(%R13),%XMM21

0x432659 DIVL	0x30(%RSP)

0x43265d VMOVQ	0x20(%R13),%XMM20

0x432664 VMOVQ	0x10(%R13),%XMM19

0x43266b MOV	%R15D,%ECX

0x43266e VMOVQ	0x8(%R13),%XMM18

0x432675 VMOVQ	0x18(%R13),%XMM17

0x43267c VMOVSD	0x3201a(%RIP),%XMM22

0x432686 VBROADCASTSD	%XMM22,%YMM23

0x43268c VBROADCASTSD	%XMM22,%ZMM13

0x432692 ADD	%EDX,%R10D

0x432695 ADD	%R14D,%EAX

0x432698 MOVSXD	%EAX,%R11

0x43269b SUB	%R10D,%ECX

0x43269e MOV	%R8D,%EAX

0x4326a1 MOV	%R10D,0x78(%RSP)

0x4326a6 MOV	%R11,0x58(%RSP)

0x4326ab NOPL	(%RAX,%RAX,1)

(220) 0x4326b0 CMP	%ECX,%EAX

(220) 0x4326b2 CMOVBE	%EAX,%ECX

(220) 0x4326b5 LEA	(%RBX,%RCX,1),%R13D

(220) 0x4326b9 MOV	%ECX,0x7c(%RSP)

(220) 0x4326bd MOV	%R13D,0x34(%RSP)

(220) 0x4326c2 CMP	%R13D,%EBX

(220) 0x4326c5 JAE	432d10

(220) 0x4326cb MOV	0x58(%RSP),%R14

(220) 0x4326d0 VMOVQ	%XMM20,%R12

(220) 0x4326d6 VMOVQ	%XMM18,%R11

(220) 0x4326dc VMOVQ	%XMM21,%RCX

(220) 0x4326e2 MOV	0x10(%R12),%R9

(220) 0x4326e7 VMOVQ	%XMM17,%RDI

(220) 0x4326ed VMOVQ	0x10(%R11),%XMM2

(220) 0x4326f3 MOV	(%RCX),%R10

(220) 0x4326f6 VMOVQ	%XMM19,%RDX

(220) 0x4326fc MOV	0x10(%RCX),%R13

(220) 0x432700 MOV	0x7c(%RSP),%ECX

(220) 0x432704 VMOVQ	0x10(%RDX),%XMM12

(220) 0x432709 VMOVQ	0x10(%RDI),%XMM11

(220) 0x43270e LEA	-0x1(%R14),%R15D

(220) 0x432712 MOV	%R14,%RAX

(220) 0x432715 MOVSXD	%R15D,%RSI

(220) 0x432718 MOV	(%R12),%R15

(220) 0x43271c MOV	(%R11),%R12

(220) 0x43271f MOV	%RSI,%R8

(220) 0x432722 IMUL	%R10,%R8

(220) 0x432726 IMUL	%R14,%R10

(220) 0x43272a IMUL	%RAX,%R12

(220) 0x43272e IMUL	(%RDI),%RAX

(220) 0x432732 MOV	%R8,0x60(%RSP)

(220) 0x432737 MOV	%R10,0x70(%RSP)

(220) 0x43273c IMUL	%R15,%RSI

(220) 0x432740 IMUL	%R14,%R15

(220) 0x432744 IMUL	(%RDX),%R14

(220) 0x432748 MOV	%R12,0x50(%RSP)

(220) 0x43274d MOV	%RSI,0x68(%RSP)

(220) 0x432752 MOV	%R15,0x38(%RSP)

(220) 0x432757 MOV	%RAX,0x48(%RSP)

(220) 0x43275c LEA	-0x1(%RCX),%EAX

(220) 0x43275f MOV	%R14,0x28(%RSP)

(220) 0x432764 CMP	$0x6,%EAX

(220) 0x432767 JBE	432d60

(220) 0x43276d MOVSXD	0x78(%RSP),%RCX

(220) 0x432772 LEA	(%R8,%RCX,1),%R11

(220) 0x432776 LEA	(%R15,%RCX,1),%RDI

(220) 0x43277a LEA	(%R14,%RCX,1),%R14

(220) 0x43277e LEA	(%RSI,%RCX,1),%RDX

(220) 0x432782 SAL	$0x3,%R11

(220) 0x432786 SAL	$0x3,%RDI

(220) 0x43278a LEA	(%R13,%R11,1),%R8

(220) 0x43278f LEA	-0x8(%R13,%R11,1),%R15

(220) 0x432794 LEA	-0x8(%R9,%RDI,1),%R11

(220) 0x432799 LEA	(%R10,%RCX,1),%RAX

(220) 0x43279d VMOVQ	%R11,%XMM1

(220) 0x4327a2 MOV	0x48(%RSP),%R11

(220) 0x4327a7 VMOVQ	%R8,%XMM6

(220) 0x4327ac LEA	(%R9,%RDI,1),%R10

(220) 0x4327b0 VMOVQ	%XMM12,%R8

(220) 0x4327b5 LEA	(%R12,%RCX,1),%RDI

(220) 0x4327b9 VMOVQ	%R10,%XMM8

(220) 0x4327be LEA	(%R8,%R14,8),%R14

(220) 0x4327c2 VMOVQ	%XMM11,%R8

(220) 0x4327c7 SAL	$0x3,%RDX

(220) 0x4327cb ADD	%R11,%RCX

(220) 0x4327ce LEA	(%R9,%RDX,1),%RSI

(220) 0x4327d2 LEA	-0x8(%R9,%RDX,1),%R10

(220) 0x4327d7 VMOVQ	%XMM2,%RDX

(220) 0x4327dc LEA	(%R8,%RCX,8),%R11

(220) 0x4327e0 MOV	0x7c(%RSP),%R8D

(220) 0x4327e5 VMOVQ	%RSI,%XMM7

(220) 0x4327ea SAL	$0x3,%RDI

(220) 0x4327ee SAL	$0x3,%RAX

(220) 0x4327f2 SHR	$0x3,%R8D

(220) 0x4327f6 MOV	%R8,%RCX

(220) 0x4327f9 LEA	-0x8(%RDX,%RDI,1),%R12

(220) 0x4327fe ADD	%RDX,%RDI

(220) 0x432801 XOR	%EDX,%EDX

(220) 0x432803 SAL	$0x6,%RCX

(220) 0x432807 AND	$0x1,%R8D

(220) 0x43280b LEA	(%R13,%RAX,1),%RSI

(220) 0x432810 LEA	-0x8(%R13,%RAX,1),%RAX

(220) 0x432815 JE	432894

(220) 0x432817 VMOVQ	%XMM8,%RDX

(220) 0x43281c VMOVUPD	(%RSI),%ZMM0

(220) 0x432822 VMOVUPD	(%RAX),%ZMM24

(220) 0x432828 VMOVQ	%XMM6,%R8

(220) 0x43282d VMULPD	(%RDX),%ZMM0,%ZMM3

(220) 0x432833 VMOVQ	%XMM7,%RDX

(220) 0x432838 VMOVUPD	(%R10),%ZMM5

(220) 0x43283e VMOVUPD	(%RDX),%ZMM4

(220) 0x432844 VMOVQ	%XMM1,%RDX

(220) 0x432849 VMULPD	(%RDX),%ZMM24,%ZMM16

(220) 0x43284f VFMADD231PD	(%R8),%ZMM4,%ZMM3

(220) 0x432855 MOV	$0x40,%EDX

(220) 0x43285a VFMADD231PD	(%R15),%ZMM5,%ZMM16

(220) 0x432860 VADDPD	%ZMM16,%ZMM3,%ZMM9

(220) 0x432866 VMULPD	%ZMM13,%ZMM9,%ZMM10

(220) 0x43286c VMOVUPD	%ZMM10,(%R14)

(220) 0x432872 VMOVUPD	(%RDI),%ZMM25

(220) 0x432878 VSUBPD	(%R12),%ZMM25,%ZMM26

(220) 0x43287f VADDPD	%ZMM10,%ZMM26,%ZMM14

(220) 0x432885 VMOVUPD	%ZMM14,(%R11)

(220) 0x43288b CMP	%RCX,%RDX

(220) 0x43288e JE	4329b4

(220) 0x432894 VMOVQ	%R9,%XMM15

(220) 0x432899 VMOVQ	%R13,%XMM3

(220) 0x43289e MOV	%EBX,0x18(%RSP)

(220) 0x4328a2 MOV	%RCX,0x40(%RSP)

(220) 0x4328a7 VMOVQ	%XMM8,%RBX

(220) 0x4328ac VMOVQ	%XMM7,%R13

(220) 0x4328b1 VMOVQ	%XMM6,%R9

(220) 0x4328b6 VMOVQ	%XMM1,%RCX

  (221) 0x4328bb VMOVUPD	(%RSI,%RDX,1),%ZMM6

  (221) 0x4328c2 VMOVUPD	(%RAX,%RDX,1),%ZMM27

  (221) 0x4328c9 VMOVUPD	(%R13,%RDX,1),%ZMM8

  (221) 0x4328d1 VMOVUPD	(%R10,%RDX,1),%ZMM1

  (221) 0x4328d8 VMULPD	(%RBX,%RDX,1),%ZMM6,%ZMM7

  (221) 0x4328df VMULPD	(%RCX,%RDX,1),%ZMM27,%ZMM28

  (221) 0x4328e6 MOV	0x40(%RSP),%R8

  (221) 0x4328eb VFMADD231PD	(%R9,%RDX,1),%ZMM8,%ZMM7

  (221) 0x4328f2 VFMADD231PD	(%R15,%RDX,1),%ZMM1,%ZMM28

  (221) 0x4328f9 VADDPD	%ZMM28,%ZMM7,%ZMM0

  (221) 0x4328ff VMULPD	%ZMM13,%ZMM0,%ZMM4

  (221) 0x432905 VMOVUPD	%ZMM4,(%R14,%RDX,1)

  (221) 0x43290c VMOVUPD	(%RDI,%RDX,1),%ZMM29

  (221) 0x432913 VSUBPD	(%R12,%RDX,1),%ZMM29,%ZMM30

  (221) 0x43291a VADDPD	%ZMM4,%ZMM30,%ZMM5

  (221) 0x432920 VMOVUPD	%ZMM5,(%R11,%RDX,1)

  (221) 0x432927 VMOVUPD	0x40(%RSI,%RDX,1),%ZMM9

  (221) 0x43292f VMOVUPD	0x40(%RAX,%RDX,1),%ZMM31

  (221) 0x432937 VMOVUPD	0x40(%R13,%RDX,1),%ZMM14

  (221) 0x43293f VMULPD	0x40(%RBX,%RDX,1),%ZMM9,%ZMM10

  (221) 0x432947 VMULPD	0x40(%RCX,%RDX,1),%ZMM31,%ZMM24

  (221) 0x43294f VMOVUPD	0x40(%R10,%RDX,1),%ZMM6

  (221) 0x432957 VFMADD231PD	0x40(%R9,%RDX,1),%ZMM14,%ZMM10

  (221) 0x43295f VFMADD231PD	0x40(%R15,%RDX,1),%ZMM6,%ZMM24

  (221) 0x432967 VADDPD	%ZMM24,%ZMM10,%ZMM7

  (221) 0x43296d VMULPD	%ZMM13,%ZMM7,%ZMM8

  (221) 0x432973 VMOVUPD	%ZMM8,0x40(%R14,%RDX,1)

  (221) 0x43297b VMOVUPD	0x40(%RDI,%RDX,1),%ZMM16

  (221) 0x432983 VSUBPD	0x40(%R12,%RDX,1),%ZMM16,%ZMM25

  (221) 0x43298b VADDPD	%ZMM8,%ZMM25,%ZMM1

  (221) 0x432991 VMOVUPD	%ZMM1,0x40(%R11,%RDX,1)

  (221) 0x432999 SUB	$-0x80,%RDX

  (221) 0x43299d CMP	%R8,%RDX

  (221) 0x4329a0 JNE	4328bb

(220) 0x4329a6 MOV	0x18(%RSP),%EBX

(220) 0x4329aa VMOVQ	%XMM15,%R9

(220) 0x4329af VMOVQ	%XMM3,%R13

(220) 0x4329b4 MOV	0x7c(%RSP),%R15D

(220) 0x4329b9 MOV	0x78(%RSP),%ESI

(220) 0x4329bd MOV	%R15D,%ECX

(220) 0x4329c0 AND	$-0x8,%ECX

(220) 0x4329c3 LEA	(%RCX,%RSI,1),%EDI

(220) 0x4329c6 ADD	%ECX,%EBX

(220) 0x4329c8 TEST	$0x7,%R15B

(220) 0x4329cc JE	432d0c

(220) 0x4329d2 MOV	0x7c(%RSP),%EAX

(220) 0x4329d6 SUB	%ECX,%EAX

(220) 0x4329d8 LEA	-0x1(%RAX),%R10D

(220) 0x4329dc CMP	$0x2,%R10D

(220) 0x4329e0 JBE	432ac0

(220) 0x4329e6 MOVSXD	0x78(%RSP),%RDX

(220) 0x4329eb MOV	0x60(%RSP),%R14

(220) 0x4329f0 MOV	0x70(%RSP),%R8

(220) 0x4329f5 MOV	0x38(%RSP),%R15

(220) 0x4329fa MOV	0x68(%RSP),%R11

(220) 0x4329ff MOV	0x28(%RSP),%RSI

(220) 0x432a04 MOV	0x50(%RSP),%R10

(220) 0x432a09 LEA	(%R14,%RDX,1),%R12

(220) 0x432a0d LEA	(%R8,%RDX,1),%R14

(220) 0x432a11 LEA	(%R15,%RDX,1),%R8

(220) 0x432a15 ADD	%RCX,%R8

(220) 0x432a18 ADD	%RCX,%R14

(220) 0x432a1b LEA	(%R11,%RDX,1),%R11

(220) 0x432a1f ADD	%RCX,%R12

(220) 0x432a22 SAL	$0x3,%R8

(220) 0x432a26 ADD	%RCX,%R11

(220) 0x432a29 VMOVUPD	(%R9,%R8,1),%YMM15

(220) 0x432a2f VMOVUPD	-0x8(%R9,%R8,1),%YMM4

(220) 0x432a36 LEA	(%RSI,%RDX,1),%R15

(220) 0x432a3a VMULPD	(%R13,%R14,8),%YMM15,%YMM0

(220) 0x432a41 VMULPD	-0x8(%R13,%R14,8),%YMM4,%YMM5

(220) 0x432a48 MOV	0x48(%RSP),%RSI

(220) 0x432a4d VMOVUPD	(%R13,%R12,8),%YMM3

(220) 0x432a54 VMOVUPD	-0x8(%R13,%R12,8),%YMM9

(220) 0x432a5b VFMADD231PD	(%R9,%R11,8),%YMM3,%YMM0

(220) 0x432a61 VFMADD231PD	-0x8(%R9,%R11,8),%YMM9,%YMM5

(220) 0x432a68 VADDPD	%YMM5,%YMM0,%YMM10

(220) 0x432a6c LEA	(%R10,%RDX,1),%R10

(220) 0x432a70 ADD	%RCX,%R15

(220) 0x432a73 VMOVQ	%XMM2,%R12

(220) 0x432a78 VMOVQ	%XMM11,%R11

(220) 0x432a7d ADD	%RCX,%R10

(220) 0x432a80 VMULPD	%YMM23,%YMM10,%YMM14

(220) 0x432a86 ADD	%RSI,%RDX

(220) 0x432a89 ADD	%RCX,%RDX

(220) 0x432a8c VMOVQ	%XMM12,%RCX

(220) 0x432a91 VMOVUPD	%YMM14,(%RCX,%R15,8)

(220) 0x432a97 VMOVUPD	(%R12,%R10,8),%YMM6

(220) 0x432a9d VSUBPD	-0x8(%R12,%R10,8),%YMM6,%YMM7

(220) 0x432aa4 VADDPD	%YMM14,%YMM7,%YMM8

(220) 0x432aa9 VMOVUPD	%YMM8,(%R11,%RDX,8)

(220) 0x432aaf MOV	%EAX,%EDX

(220) 0x432ab1 AND	$-0x4,%EDX

(220) 0x432ab4 ADD	%EDX,%EDI

(220) 0x432ab6 ADD	%EDX,%EBX

(220) 0x432ab8 TEST	$0x3,%AL

(220) 0x432aba JE	432d0c

(220) 0x432ac0 MOV	0x68(%RSP),%RCX

(220) 0x432ac5 MOVSXD	%EDI,%RAX

(220) 0x432ac8 MOV	0x60(%RSP),%RSI

(220) 0x432acd MOV	0x38(%RSP),%RDX

(220) 0x432ad2 LEA	(%RCX,%RAX,1),%R15

(220) 0x432ad6 LEA	(%RSI,%RAX,1),%R14

(220) 0x432ada ADD	%RAX,%RDX

(220) 0x432add LEA	(%R9,%R15,8),%R10

(220) 0x432ae1 MOV	0x70(%RSP),%R15

(220) 0x432ae6 LEA	(%R13,%R14,8),%R8

(220) 0x432aeb LEA	-0x1(%RDI),%R14D

(220) 0x432aef VMOVSD	(%R10),%XMM0

(220) 0x432af4 LEA	(%R15,%RAX,1),%R12

(220) 0x432af8 LEA	(%R13,%R12,8),%R11

(220) 0x432afd LEA	(%R9,%RDX,8),%R12

(220) 0x432b01 MOVSXD	%R14D,%RDX

(220) 0x432b04 LEA	(%RDX,%RCX,1),%R14

(220) 0x432b08 LEA	(%RDX,%RSI,1),%RCX

(220) 0x432b0c MOV	0x38(%RSP),%RSI

(220) 0x432b11 ADD	%RDX,%R15

(220) 0x432b14 VMOVSD	(%R9,%R14,8),%XMM5

(220) 0x432b1a VMOVQ	%XMM12,%R14

(220) 0x432b1f VMOVSD	(%R12),%XMM1

(220) 0x432b25 VMULSD	(%R11),%XMM1,%XMM15

(220) 0x432b2a VFMADD231SD	(%R8),%XMM0,%XMM15

(220) 0x432b2f ADD	%RDX,%RSI

(220) 0x432b32 VMOVSD	(%R9,%RSI,8),%XMM3

(220) 0x432b38 VMULSD	(%R13,%R15,8),%XMM3,%XMM4

(220) 0x432b3f MOV	0x28(%RSP),%R15

(220) 0x432b44 MOV	0x50(%RSP),%RSI

(220) 0x432b49 VFMADD231SD	(%R13,%RCX,8),%XMM5,%XMM4

(220) 0x432b50 VADDSD	%XMM4,%XMM15,%XMM9

(220) 0x432b54 VMULSD	%XMM22,%XMM9,%XMM10

(220) 0x432b5a LEA	(%R15,%RAX,1),%RCX

(220) 0x432b5e VMOVQ	%XMM2,%R15

(220) 0x432b63 ADD	%RSI,%RDX

(220) 0x432b66 VMOVSD	%XMM10,(%R14,%RCX,8)

(220) 0x432b6c LEA	(%RSI,%RAX,1),%RCX

(220) 0x432b70 MOV	0x48(%RSP),%R14

(220) 0x432b75 LEA	(%R15,%RCX,8),%RCX

(220) 0x432b79 VMOVSD	(%RCX),%XMM14

(220) 0x432b7d VSUBSD	(%R15,%RDX,8),%XMM14,%XMM6

(220) 0x432b83 MOV	0x34(%RSP),%R15D

(220) 0x432b88 VMOVQ	%XMM11,%RDX

(220) 0x432b8d VADDSD	%XMM10,%XMM6,%XMM7

(220) 0x432b92 ADD	%R14,%RAX

(220) 0x432b95 VMOVSD	%XMM7,(%RDX,%RAX,8)

(220) 0x432b9a LEA	0x1(%RBX),%EAX

(220) 0x432b9d CMP	%R15D,%EAX

(220) 0x432ba0 JAE	432d0c

(220) 0x432ba6 MOV	0x60(%RSP),%R14

(220) 0x432bab LEA	0x1(%RDI),%EAX

(220) 0x432bae MOV	0x68(%RSP),%RDX

(220) 0x432bb3 VMOVSD	(%R12),%XMM3

(220) 0x432bb9 CLTQ

(220) 0x432bbb MOV	0x28(%RSP),%R12

(220) 0x432bc0 VMULSD	(%R11),%XMM3,%XMM4

(220) 0x432bc5 MOV	0x50(%RSP),%R11

(220) 0x432bca VMOVSD	(%R10),%XMM5

(220) 0x432bcf VFMADD231SD	(%R8),%XMM5,%XMM4

(220) 0x432bd4 VMOVQ	%XMM12,%R8

(220) 0x432bd9 ADD	$0x2,%EBX

(220) 0x432bdc LEA	(%R14,%RAX,1),%RSI

(220) 0x432be0 ADD	%RAX,%RDX

(220) 0x432be3 LEA	(%R13,%RSI,8),%R15

(220) 0x432be8 MOV	0x70(%RSP),%RSI

(220) 0x432bed LEA	(%R9,%RDX,8),%R14

(220) 0x432bf1 LEA	(%R12,%RAX,1),%R10

(220) 0x432bf5 VMOVSD	(%R14),%XMM0

(220) 0x432bfa ADD	%RAX,%RSI

(220) 0x432bfd LEA	(%R13,%RSI,8),%RDX

(220) 0x432c02 MOV	0x38(%RSP),%RSI

(220) 0x432c07 VMOVQ	%RDX,%XMM8

(220) 0x432c0c LEA	(%RSI,%RAX,1),%RDX

(220) 0x432c10 LEA	(%R9,%RDX,8),%RSI

(220) 0x432c14 VMOVQ	%XMM8,%RDX

(220) 0x432c19 VMOVSD	(%RSI),%XMM1

(220) 0x432c1d VMULSD	(%RDX),%XMM1,%XMM15

(220) 0x432c21 LEA	(%R11,%RAX,1),%RDX

(220) 0x432c25 VFMADD231SD	(%R15),%XMM0,%XMM15

(220) 0x432c2a VADDSD	%XMM15,%XMM4,%XMM9

(220) 0x432c2f VMULSD	%XMM22,%XMM9,%XMM10

(220) 0x432c35 VMOVSD	%XMM10,(%R8,%R10,8)

(220) 0x432c3b VMOVQ	%XMM2,%R10

(220) 0x432c40 LEA	(%R10,%RDX,8),%R8

(220) 0x432c44 MOV	0x48(%RSP),%RDX

(220) 0x432c49 VMOVSD	(%R8),%XMM14

(220) 0x432c4e VSUBSD	(%RCX),%XMM14,%XMM6

(220) 0x432c52 VMOVQ	%XMM11,%RCX

(220) 0x432c57 VADDSD	%XMM10,%XMM6,%XMM7

(220) 0x432c5c ADD	%RDX,%RAX

(220) 0x432c5f VMOVSD	%XMM7,(%RCX,%RAX,8)

(220) 0x432c64 MOV	0x34(%RSP),%EAX

(220) 0x432c68 CMP	%EAX,%EBX

(220) 0x432c6a JAE	432d0c

(220) 0x432c70 MOV	0x68(%RSP),%RBX

(220) 0x432c75 MOV	0x60(%RSP),%R10

(220) 0x432c7a MOV	0x38(%RSP),%RCX

(220) 0x432c7f MOV	0x70(%RSP),%RDX

(220) 0x432c84 VMOVSD	(%R15),%XMM4

(220) 0x432c89 MOV	0x48(%RSP),%R15

(220) 0x432c8e ADD	$0x2,%EDI

(220) 0x432c91 MOVSXD	%EDI,%RDI

(220) 0x432c94 ADD	%RDI,%R12

(220) 0x432c97 ADD	%RDI,%R11

(220) 0x432c9a ADD	%RDI,%RBX

(220) 0x432c9d ADD	%RDI,%R10

(220) 0x432ca0 ADD	%RDI,%RCX

(220) 0x432ca3 ADD	%RDI,%RDX

(220) 0x432ca6 VMOVSD	(%R9,%RCX,8),%XMM1

(220) 0x432cac VMOVSD	(%R9,%RBX,8),%XMM0

(220) 0x432cb2 VMULSD	(%R13,%RDX,8),%XMM1,%XMM15

(220) 0x432cb9 VFMADD231SD	(%R13,%R10,8),%XMM0,%XMM15

(220) 0x432cc0 VMOVQ	%XMM8,%R13

(220) 0x432cc5 VMOVQ	%XMM12,%R9

(220) 0x432cca ADD	%RDI,%R15

(220) 0x432ccd VMOVSD	(%R13),%XMM8

(220) 0x432cd3 VMULSD	(%RSI),%XMM8,%XMM3

(220) 0x432cd7 VMOVQ	%XMM11,%RSI

(220) 0x432cdc VFMADD231SD	(%R14),%XMM4,%XMM3

(220) 0x432ce1 VMOVQ	%XMM2,%R14

(220) 0x432ce6 VADDSD	%XMM3,%XMM15,%XMM5

(220) 0x432cea VMULSD	%XMM22,%XMM5,%XMM9

(220) 0x432cf0 VMOVSD	%XMM9,(%R9,%R12,8)

(220) 0x432cf6 VMOVSD	(%R14,%R11,8),%XMM12

(220) 0x432cfc VSUBSD	(%R8),%XMM12,%XMM2

(220) 0x432d01 VADDSD	%XMM9,%XMM2,%XMM10

(220) 0x432d06 VMOVSD	%XMM10,(%RSI,%R15,8)

(220) 0x432d0c MOV	0x34(%RSP),%EBX

(220) 0x432d10 INCQ	0x58(%RSP)

(220) 0x432d15 MOV	0x58(%RSP),%R8

(220) 0x432d1a CMP	%R8D,0x24(%RSP)

(220) 0x432d1f JLE	432d40

(220) 0x432d21 MOV	0x1c(%RSP),%EAX

(220) 0x432d25 MOV	0x20(%RSP),%EDI

(220) 0x432d29 MOV	0x30(%RSP),%ECX

(220) 0x432d2d SUB	%EBX,%EAX

(220) 0x432d2f MOV	%EDI,0x78(%RSP)

(220) 0x432d33 JMP	4326b0

0x432d38 NOPL	(%RAX,%RAX,1)

0x432d40 VZEROUPPER

0x432d43 LEA	-0x28(%RBP),%RSP

0x432d47 POP	%RBX

0x432d48 POP	%R12

0x432d4a POP	%R13

0x432d4c POP	%R14

0x432d4e POP	%R15

0x432d50 POP	%RBP

0x432d51 RET

0x432d52 NOPW	%CS:(%RAX,%RAX,1)

0x432d5d NOPL	(%RAX)

(220) 0x432d60 MOV	0x78(%RSP),%EDI

(220) 0x432d64 XOR	%ECX,%ECX

(220) 0x432d66 JMP	4329d2

0x432d6b INC	%R8D

0x432d6e XOR	%EDX,%EDX

0x432d70 JMP	432630

0x432d75 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.82+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.15+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:95	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:70	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.10+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:95	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:101	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.00 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 10.13 cycles (1.19x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:98

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	82
nb uops	81
loop length	317
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	1
used zmm registers	1
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	5.25	5.25	5.25	5.25	0.00	1.00	1.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	5.25	5.25	5.25	5.25	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	5.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	9%

Vector efficiency ratios

INT

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4325b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R13),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x34(%R13),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x2c(%R13),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %EDX,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 432d43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x793>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x4(%RBX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 432d43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x793>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x30(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 432d6b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x7bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R8D,%ESI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RSI,%RDX,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA (%R8,%RBX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R9D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R9D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 432d43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x793>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EBX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x20(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
VMOVQ (%R13),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
DIVL 0x30(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ 0x20(%R13),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ 0x8(%R13),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x18(%R13),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x3201a(%RIP),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM22,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM22,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R10D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10D,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R11,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 432630 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:95-100
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:95-100

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 2.00 cycles (6.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.88 cycles (1.22x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:96
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:98

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 76 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	82
nb uops	81
loop length	317
used x86 registers	16
used mmx registers	0
used xmm registers	6
used ymm registers	1
used zmm registers	1
nb stack references	7

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.13 cycles
front end	10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.50	5.50	5.50	5.50	5.50	5.50	5.25	5.25	5.25	5.25	0.00	1.00	1.00	0.00	0.00	0.00
cycles	5.50	5.50	5.50	5.50	5.50	5.50	5.25	5.25	5.25	5.25	0.00	1.00	1.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	10.13
Dispatch	5.50
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

INT

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	3%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	9%

Vector efficiency ratios

INT

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	8%
load	10%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (6.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4325b0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P11	P12	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
ADD $-0x80,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOV 0x30(%R13),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x34(%R13),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x28(%RDI),%EDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
MOV 0x2c(%R13),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
ADD $0x3,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
LEA 0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDI,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %EDX,0x24(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %EDX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 432d43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x793>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
LEA 0x4(%RBX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %EDX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %R14D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
CMP %R15D,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JGE 432d43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x793>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %EDI,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %ECX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x30(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	N/A
IMUL %EBX,%EAX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	0	0	10-17	6	scal (6.3%)
MOV %EAX,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CMP %EDX,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JB 432d6b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x7bb>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
IMUL %R8D,%ESI	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	3	0.33	N/A
LEA (%RSI,%RDX,1),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
LEA (%R8,%RBX,1),%R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
MOV %R9D,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
CMP %R9D,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
JAE 432d43 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x793>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50-1	N/A
MOV %EBX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x20(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	3	0.25	scal (6.3%)
VMOVQ (%R13),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
DIVL 0x30(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	0	0	10-17	6	scal (6.3%)
VMOVQ 0x20(%R13),%XMM20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x10(%R13),%XMM19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
MOV %R15D,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
VMOVQ 0x8(%R13),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVQ 0x18(%R13),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD 0x3201a(%RIP),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VBROADCASTSD %XMM22,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VBROADCASTSD %XMM22,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
ADD %EDX,%R10D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD %R14D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
MOVSXD %EAX,%R11	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R10D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %R8D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R10D,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (6.3%)
MOV %R11,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.50	scal (12.5%)
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 432630 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.5+0x80>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	3.11	1.14
▼Loop 220 - advec_mom.cpp:97-100 - exec–	0.00	0.01
○Loop 221 - advec_mom.cpp:98-100 - exec	3.10	1.14

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code