OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone ._omp

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:71-75 [...]	Coverage (incl. loops): 2.67% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 71 - 75

--------------------------------------------------------------------------------

71: #pragma omp parallel for simd collapse(2)

72:     for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

73:       for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

74:         post_vol(i, j) = volume(i, j);

75:         pre_vol(i, j) = post_vol(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j);

0x431f70 PUSH	%RBP

0x431f71 MOV	%RSP,%RBP

0x431f74 PUSH	%R15

0x431f76 PUSH	%R14

0x431f78 PUSH	%R13

0x431f7a PUSH	%R12

0x431f7c PUSH	%RBX

0x431f7d AND	$-0x40,%RSP

0x431f81 SUB	$0x40,%RSP

0x431f85 MOV	0x28(%RDI),%EAX

0x431f88 MOV	0x2c(%RDI),%ESI

0x431f8b MOV	0x20(%RDI),%ECX

0x431f8e MOV	0x24(%RDI),%EDX

0x431f91 MOV	%RDI,0x38(%RSP)

0x431f96 ADD	$0x4,%ESI

0x431f99 DEC	%ECX

0x431f9b LEA	-0x1(%RAX),%EBX

0x431f9e MOV	%ESI,0x1c(%RSP)

0x431fa2 MOV	%ECX,0x18(%RSP)

0x431fa6 CMP	%ESI,%EBX

0x431fa8 JGE	432573

0x431fae MOV	%ESI,%R14D

0x431fb1 LEA	0x4(%RDX),%R15D

0x431fb5 SUB	%EBX,%R14D

0x431fb8 CMP	%R15D,%ECX

0x431fbb JGE	432573

0x431fc1 MOV	%R15D,%R13D

0x431fc4 SUB	%ECX,%R13D

0x431fc7 IMUL	%R13D,%R14D

0x431fcb MOV	%R13D,0x14(%RSP)

0x431fd0 CALL	404630 <omp_get_num_threads@plt>

0x431fd5 MOV	%EAX,%R12D

0x431fd8 CALL	404520 <omp_get_thread_num@plt>

0x431fdd XOR	%EDX,%EDX

0x431fdf MOV	0x38(%RSP),%RDI

0x431fe4 MOV	%EAX,%ECX

0x431fe6 MOV	%R14D,%EAX

0x431fe9 DIV	%R12D

0x431fec CMP	%EDX,%ECX

0x431fee MOV	%EAX,%R9D

0x431ff1 JB	43259b

0x431ff7 IMUL	%R9D,%ECX

0x431ffb ADD	%EDX,%ECX

0x431ffd LEA	(%R9,%RCX,1),%R8D

0x432001 MOV	%R8D,0x10(%RSP)

0x432006 CMP	%R8D,%ECX

0x432009 JAE	432573

0x43200f MOV	%ECX,%EAX

0x432011 XOR	%EDX,%EDX

0x432013 MOV	0x18(%RSP),%R10D

0x432018 VMOVQ	0x8(%RDI),%XMM4

0x43201d DIVL	0x14(%RSP)

0x432021 VMOVQ	0x18(%RDI),%XMM5

0x432026 VMOVQ	(%RDI),%XMM3

0x43202a VMOVQ	0x10(%RDI),%XMM2

0x43202f ADD	%R10D,%EDX

0x432032 ADD	%EBX,%EAX

0x432034 SUB	%EDX,%R15D

0x432037 MOV	%EDX,0x38(%RSP)

0x43203b MOVSXD	%EAX,%R8

0x43203e MOV	%R9D,%EDX

0x432041 MOV	%R15D,%R12D

0x432044 NOPW	%CS:(%RAX,%RAX,1)

0x43204f NOP

(218) 0x432050 CMP	%R12D,%EDX

(218) 0x432053 CMOVA	%R12D,%EDX

(218) 0x432057 LEA	(%RCX,%RDX,1),%R12D

(218) 0x43205b CMP	%R12D,%ECX

(218) 0x43205e JAE	43254b

(218) 0x432064 VMOVQ	%XMM4,%R11

(218) 0x432069 VMOVQ	%XMM5,%RSI

(218) 0x43206e LEA	-0x1(%RDX),%EDI

(218) 0x432071 VMOVQ	%XMM2,%R9

(218) 0x432076 MOV	(%R11),%RBX

(218) 0x432079 MOV	(%RSI),%R13

(218) 0x43207c VMOVQ	%XMM3,%R14

(218) 0x432081 VMOVQ	0x10(%R9),%XMM7

(218) 0x432087 MOV	(%R9),%R9

(218) 0x43208a MOV	(%R14),%R10

(218) 0x43208d VMOVQ	0x10(%R11),%XMM9

(218) 0x432093 VMOVQ	0x10(%RSI),%XMM8

(218) 0x432098 MOV	0x10(%R14),%R15

(218) 0x43209c IMUL	%R8,%RBX

(218) 0x4320a0 IMUL	%R8,%R13

(218) 0x4320a4 IMUL	%R8,%R9

(218) 0x4320a8 IMUL	%R8,%R10

(218) 0x4320ac MOV	%RBX,0x20(%RSP)

(218) 0x4320b1 MOV	%R13,0x28(%RSP)

(218) 0x4320b6 MOV	%R9,0x30(%RSP)

(218) 0x4320bb CMP	$0x6,%EDI

(218) 0x4320be JBE	432590

(218) 0x4320c4 MOVSXD	0x38(%RSP),%RAX

(218) 0x4320c9 VMOVQ	%XMM8,%RSI

(218) 0x4320ce LEA	(%RBX,%RAX,1),%R11

(218) 0x4320d2 LEA	(%R13,%RAX,1),%R13

(218) 0x4320d7 LEA	0x1(%R10,%RAX,1),%RDI

(218) 0x4320dc ADD	%R9,%RAX

(218) 0x4320df VMOVQ	%XMM7,%R9

(218) 0x4320e4 LEA	(%RSI,%R13,8),%R13

(218) 0x4320e8 VMOVQ	%XMM9,%RBX

(218) 0x4320ed LEA	(%R9,%RAX,8),%RSI

(218) 0x4320f1 MOV	%EDX,%R9D

(218) 0x4320f4 LEA	(%RBX,%R11,8),%R14

(218) 0x4320f8 XOR	%EAX,%EAX

(218) 0x4320fa SHR	$0x3,%R9D

(218) 0x4320fe SAL	$0x3,%RDI

(218) 0x432102 SAL	$0x6,%R9

(218) 0x432106 LEA	(%R15,%RDI,1),%R11

(218) 0x43210a LEA	-0x8(%R15,%RDI,1),%RBX

(218) 0x43210f LEA	-0x40(%R9),%RDI

(218) 0x432113 SHR	$0x6,%RDI

(218) 0x432117 INC	%RDI

(218) 0x43211a AND	$0x7,%EDI

(218) 0x43211d JE	432274

(218) 0x432123 CMP	$0x1,%RDI

(218) 0x432127 JE	432243

(218) 0x43212d CMP	$0x2,%RDI

(218) 0x432131 JE	43221b

(218) 0x432137 CMP	$0x3,%RDI

(218) 0x43213b JE	4321f3

(218) 0x432141 CMP	$0x4,%RDI

(218) 0x432145 JE	4321cb

(218) 0x43214b CMP	$0x5,%RDI

(218) 0x43214f JE	4321a3

(218) 0x432151 CMP	$0x6,%RDI

(218) 0x432155 JE	43217b

(218) 0x432157 VMOVUPD	(%R14),%ZMM6

(218) 0x43215d MOV	$0x40,%EAX

(218) 0x432162 VMOVUPD	%ZMM6,(%R13)

(218) 0x432169 VADDPD	(%R11),%ZMM6,%ZMM0

(218) 0x43216f VSUBPD	(%RBX),%ZMM0,%ZMM1

(218) 0x432175 VMOVUPD	%ZMM1,(%RSI)

(218) 0x43217b VMOVUPD	(%R14,%RAX,1),%ZMM10

(218) 0x432182 VMOVUPD	%ZMM10,(%R13,%RAX,1)

(218) 0x43218a VADDPD	(%R11,%RAX,1),%ZMM10,%ZMM11

(218) 0x432191 VSUBPD	(%RBX,%RAX,1),%ZMM11,%ZMM12

(218) 0x432198 VMOVUPD	%ZMM12,(%RSI,%RAX,1)

(218) 0x43219f ADD	$0x40,%RAX

(218) 0x4321a3 VMOVUPD	(%R14,%RAX,1),%ZMM13

(218) 0x4321aa VMOVUPD	%ZMM13,(%R13,%RAX,1)

(218) 0x4321b2 VADDPD	(%R11,%RAX,1),%ZMM13,%ZMM14

(218) 0x4321b9 VSUBPD	(%RBX,%RAX,1),%ZMM14,%ZMM15

(218) 0x4321c0 VMOVUPD	%ZMM15,(%RSI,%RAX,1)

(218) 0x4321c7 ADD	$0x40,%RAX

(218) 0x4321cb VMOVUPD	(%R14,%RAX,1),%ZMM6

(218) 0x4321d2 VMOVUPD	%ZMM6,(%R13,%RAX,1)

(218) 0x4321da VADDPD	(%R11,%RAX,1),%ZMM6,%ZMM0

(218) 0x4321e1 VSUBPD	(%RBX,%RAX,1),%ZMM0,%ZMM1

(218) 0x4321e8 VMOVUPD	%ZMM1,(%RSI,%RAX,1)

(218) 0x4321ef ADD	$0x40,%RAX

(218) 0x4321f3 VMOVUPD	(%R14,%RAX,1),%ZMM10

(218) 0x4321fa VMOVUPD	%ZMM10,(%R13,%RAX,1)

(218) 0x432202 VADDPD	(%R11,%RAX,1),%ZMM10,%ZMM11

(218) 0x432209 VSUBPD	(%RBX,%RAX,1),%ZMM11,%ZMM12

(218) 0x432210 VMOVUPD	%ZMM12,(%RSI,%RAX,1)

(218) 0x432217 ADD	$0x40,%RAX

(218) 0x43221b VMOVUPD	(%R14,%RAX,1),%ZMM13

(218) 0x432222 VMOVUPD	%ZMM13,(%R13,%RAX,1)

(218) 0x43222a VADDPD	(%R11,%RAX,1),%ZMM13,%ZMM14

(218) 0x432231 VSUBPD	(%RBX,%RAX,1),%ZMM14,%ZMM15

(218) 0x432238 VMOVUPD	%ZMM15,(%RSI,%RAX,1)

(218) 0x43223f ADD	$0x40,%RAX

(218) 0x432243 VMOVUPD	(%R14,%RAX,1),%ZMM6

(218) 0x43224a VMOVUPD	%ZMM6,(%R13,%RAX,1)

(218) 0x432252 VADDPD	(%R11,%RAX,1),%ZMM6,%ZMM0

(218) 0x432259 VSUBPD	(%RBX,%RAX,1),%ZMM0,%ZMM1

(218) 0x432260 VMOVUPD	%ZMM1,(%RSI,%RAX,1)

(218) 0x432267 ADD	$0x40,%RAX

(218) 0x43226b CMP	%R9,%RAX

(218) 0x43226e JE	4323bf

  (219) 0x432274 VMOVUPD	(%R14,%RAX,1),%ZMM10

  (219) 0x43227b VMOVUPD	%ZMM10,(%R13,%RAX,1)

  (219) 0x432283 VADDPD	(%R11,%RAX,1),%ZMM10,%ZMM11

  (219) 0x43228a VSUBPD	(%RBX,%RAX,1),%ZMM11,%ZMM12

  (219) 0x432291 VMOVUPD	%ZMM12,(%RSI,%RAX,1)

  (219) 0x432298 VMOVUPD	0x40(%R14,%RAX,1),%ZMM13

  (219) 0x4322a0 VMOVUPD	%ZMM13,0x40(%R13,%RAX,1)

  (219) 0x4322a8 VADDPD	0x40(%R11,%RAX,1),%ZMM13,%ZMM14

  (219) 0x4322b0 VSUBPD	0x40(%RBX,%RAX,1),%ZMM14,%ZMM15

  (219) 0x4322b8 VMOVUPD	%ZMM15,0x40(%RSI,%RAX,1)

  (219) 0x4322c0 VMOVUPD	0x80(%R14,%RAX,1),%ZMM6

  (219) 0x4322c8 VMOVUPD	%ZMM6,0x80(%R13,%RAX,1)

  (219) 0x4322d0 VADDPD	0x80(%R11,%RAX,1),%ZMM6,%ZMM0

  (219) 0x4322d8 VSUBPD	0x80(%RBX,%RAX,1),%ZMM0,%ZMM1

  (219) 0x4322e0 VMOVUPD	%ZMM1,0x80(%RSI,%RAX,1)

  (219) 0x4322e8 VMOVUPD	0xc0(%R14,%RAX,1),%ZMM10

  (219) 0x4322f0 VMOVUPD	%ZMM10,0xc0(%R13,%RAX,1)

  (219) 0x4322f8 VADDPD	0xc0(%R11,%RAX,1),%ZMM10,%ZMM11

  (219) 0x432300 VSUBPD	0xc0(%RBX,%RAX,1),%ZMM11,%ZMM12

  (219) 0x432308 VMOVUPD	%ZMM12,0xc0(%RSI,%RAX,1)

  (219) 0x432310 VMOVUPD	0x100(%R14,%RAX,1),%ZMM13

  (219) 0x432318 VMOVUPD	%ZMM13,0x100(%R13,%RAX,1)

  (219) 0x432320 VADDPD	0x100(%R11,%RAX,1),%ZMM13,%ZMM14

  (219) 0x432328 VSUBPD	0x100(%RBX,%RAX,1),%ZMM14,%ZMM15

  (219) 0x432330 VMOVUPD	%ZMM15,0x100(%RSI,%RAX,1)

  (219) 0x432338 VMOVUPD	0x140(%R14,%RAX,1),%ZMM6

  (219) 0x432340 VMOVUPD	%ZMM6,0x140(%R13,%RAX,1)

  (219) 0x432348 VADDPD	0x140(%R11,%RAX,1),%ZMM6,%ZMM0

  (219) 0x432350 VSUBPD	0x140(%RBX,%RAX,1),%ZMM0,%ZMM1

  (219) 0x432358 VMOVUPD	%ZMM1,0x140(%RSI,%RAX,1)

  (219) 0x432360 VMOVUPD	0x180(%R14,%RAX,1),%ZMM10

  (219) 0x432368 VMOVUPD	%ZMM10,0x180(%R13,%RAX,1)

  (219) 0x432370 VADDPD	0x180(%R11,%RAX,1),%ZMM10,%ZMM11

  (219) 0x432378 VSUBPD	0x180(%RBX,%RAX,1),%ZMM11,%ZMM12

  (219) 0x432380 VMOVUPD	%ZMM12,0x180(%RSI,%RAX,1)

  (219) 0x432388 VMOVUPD	0x1c0(%R14,%RAX,1),%ZMM13

  (219) 0x432390 VMOVUPD	%ZMM13,0x1c0(%R13,%RAX,1)

  (219) 0x432398 VADDPD	0x1c0(%R11,%RAX,1),%ZMM13,%ZMM14

  (219) 0x4323a0 VSUBPD	0x1c0(%RBX,%RAX,1),%ZMM14,%ZMM15

  (219) 0x4323a8 VMOVUPD	%ZMM15,0x1c0(%RSI,%RAX,1)

  (219) 0x4323b0 ADD	$0x200,%RAX

  (219) 0x4323b6 CMP	%R9,%RAX

  (219) 0x4323b9 JNE	432274

(218) 0x4323bf MOV	0x38(%RSP),%R14D

(218) 0x4323c4 MOV	%EDX,%EAX

(218) 0x4323c6 AND	$-0x8,%EAX

(218) 0x4323c9 ADD	%EAX,%ECX

(218) 0x4323cb LEA	(%RAX,%R14,1),%EDI

(218) 0x4323cf TEST	$0x7,%DL

(218) 0x4323d2 JE	432548

(218) 0x4323d8 SUB	%EAX,%EDX

(218) 0x4323da LEA	-0x1(%RDX),%R13D

(218) 0x4323de CMP	$0x2,%R13D

(218) 0x4323e2 JBE	432459

(218) 0x4323e4 MOVSXD	0x38(%RSP),%RSI

(218) 0x4323e9 MOV	0x20(%RSP),%RBX

(218) 0x4323ee VMOVQ	%XMM9,%R13

(218) 0x4323f3 LEA	(%R10,%RSI,1),%R11

(218) 0x4323f7 LEA	(%RBX,%RSI,1),%R9

(218) 0x4323fb VMOVQ	%XMM8,%RBX

(218) 0x432400 LEA	0x1(%RAX,%R11,1),%R14

(218) 0x432405 ADD	%RAX,%R9

(218) 0x432408 MOV	0x28(%RSP),%R11

(218) 0x43240d VMOVUPD	(%R13,%R9,8),%YMM6

(218) 0x432414 LEA	(%R11,%RSI,1),%R9

(218) 0x432418 ADD	%RAX,%R9

(218) 0x43241b VMOVUPD	%YMM6,(%RBX,%R9,8)

(218) 0x432421 VMOVUPD	(%R15,%R14,8),%YMM0

(218) 0x432427 VSUBPD	-0x8(%R15,%R14,8),%YMM0,%YMM1

(218) 0x43242e MOV	0x30(%RSP),%R14

(218) 0x432433 ADD	%R14,%RSI

(218) 0x432436 ADD	%RAX,%RSI

(218) 0x432439 VMOVQ	%XMM7,%RAX

(218) 0x43243e VADDPD	%YMM6,%YMM1,%YMM10

(218) 0x432442 VMOVUPD	%YMM10,(%RAX,%RSI,8)

(218) 0x432447 MOV	%EDX,%ESI

(218) 0x432449 AND	$-0x4,%ESI

(218) 0x43244c ADD	%ESI,%EDI

(218) 0x43244e ADD	%ESI,%ECX

(218) 0x432450 AND	$0x3,%EDX

(218) 0x432453 JE	432548

(218) 0x432459 MOV	0x20(%RSP),%RBX

(218) 0x43245e MOV	0x28(%RSP),%R14

(218) 0x432463 MOVSXD	%EDI,%RDX

(218) 0x432466 VMOVQ	%XMM9,%R11

(218) 0x43246b VMOVQ	%XMM8,%RAX

(218) 0x432470 LEA	(%RBX,%RDX,1),%R13

(218) 0x432474 LEA	(%R14,%RDX,1),%R9

(218) 0x432478 VMOVSD	(%R11,%R13,8),%XMM11

(218) 0x43247e MOV	0x30(%RSP),%R13

(218) 0x432483 VMOVSD	%XMM11,(%RAX,%R9,8)

(218) 0x432489 LEA	0x1(%RDI),%EAX

(218) 0x43248c CLTQ

(218) 0x43248e LEA	0x1(%RCX),%R11D

(218) 0x432492 LEA	(%R10,%RAX,1),%RSI

(218) 0x432496 LEA	(%R15,%RSI,8),%RSI

(218) 0x43249a VMOVSD	(%RSI),%XMM12

(218) 0x43249e LEA	(%R13,%RDX,1),%R9

(218) 0x4324a3 ADD	%R10,%RDX

(218) 0x4324a6 VSUBSD	(%R15,%RDX,8),%XMM12,%XMM13

(218) 0x4324ac VMOVQ	%XMM7,%RDX

(218) 0x4324b1 VADDSD	%XMM11,%XMM13,%XMM14

(218) 0x4324b6 VMOVSD	%XMM14,(%RDX,%R9,8)

(218) 0x4324bc CMP	%R12D,%R11D

(218) 0x4324bf JAE	432548

(218) 0x4324c5 LEA	(%RAX,%RBX,1),%RDX

(218) 0x4324c9 VMOVQ	%XMM9,%R9

(218) 0x4324ce LEA	(%RAX,%R14,1),%R11

(218) 0x4324d2 ADD	$0x2,%ECX

(218) 0x4324d5 VMOVSD	(%R9,%RDX,8),%XMM15

(218) 0x4324db VMOVQ	%XMM8,%RDX

(218) 0x4324e0 LEA	0x2(%RDI),%R9D

(218) 0x4324e4 ADD	%R13,%RAX

(218) 0x4324e7 VMOVSD	%XMM15,(%RDX,%R11,8)

(218) 0x4324ed MOVSXD	%R9D,%RDX

(218) 0x4324f0 LEA	(%R10,%RDX,1),%R11

(218) 0x4324f4 LEA	(%R15,%R11,8),%R9

(218) 0x4324f8 VADDSD	(%R9),%XMM15,%XMM6

(218) 0x4324fd VSUBSD	(%RSI),%XMM6,%XMM0

(218) 0x432501 VMOVQ	%XMM7,%RSI

(218) 0x432506 VMOVSD	%XMM0,(%RSI,%RAX,8)

(218) 0x43250b CMP	%R12D,%ECX

(218) 0x43250e JAE	432548

(218) 0x432510 ADD	$0x3,%EDI

(218) 0x432513 ADD	%RDX,%RBX

(218) 0x432516 VMOVQ	%XMM9,%RCX

(218) 0x43251b ADD	%RDX,%R14

(218) 0x43251e MOVSXD	%EDI,%RDI

(218) 0x432521 VMOVSD	(%RCX,%RBX,8),%XMM9

(218) 0x432526 ADD	%RDX,%R13

(218) 0x432529 VMOVQ	%XMM8,%RBX

(218) 0x43252e ADD	%R10,%RDI

(218) 0x432531 VMOVSD	%XMM9,(%RBX,%R14,8)

(218) 0x432537 VADDSD	(%R15,%RDI,8),%XMM9,%XMM8

(218) 0x43253d VSUBSD	(%R9),%XMM8,%XMM1

(218) 0x432542 VMOVSD	%XMM1,(%RSI,%R13,8)

(218) 0x432548 MOV	%R12D,%ECX

(218) 0x43254b INC	%R8

(218) 0x43254e CMP	%R8D,0x1c(%RSP)

(218) 0x432553 JLE	432570

(218) 0x432555 MOV	0x10(%RSP),%EDX

(218) 0x432559 MOV	0x18(%RSP),%R10D

(218) 0x43255e MOV	0x14(%RSP),%R12D

(218) 0x432563 SUB	%ECX,%EDX

(218) 0x432565 MOV	%R10D,0x38(%RSP)

(218) 0x43256a JMP	432050

0x43256f NOP

0x432570 VZEROUPPER

0x432573 LEA	-0x28(%RBP),%RSP

0x432577 POP	%RBX

0x432578 POP	%R12

0x43257a POP	%R13

0x43257c POP	%R14

0x43257e POP	%R15

0x432580 POP	%RBP

0x432581 RET

0x432582 NOPW	%CS:(%RAX,%RAX,1)

0x43258d NOPL	(%RAX)

(218) 0x432590 MOV	0x38(%RSP),%EDI

(218) 0x432594 XOR	%EAX,%EAX

(218) 0x432596 JMP	4323d8

0x43259b INC	%R9D

0x43259e XOR	%EDX,%EDX

0x4325a0 JMP	431ff7

0x4325a5 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►96.94+	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►1.11+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:80	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:239	exec
○	advection(global_variables&)	advection.cpp:99	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec
►1.09+	GOMP_parallel	libgomp.h:982	libgomp.so.1.0.0
○	advec_mom_kernel(int, int, int[...]	advec_mom.cpp:80	exec
○	advec_mom_driver(global_variab[...]	advec_mom.cpp:234	exec
○	advection(global_variables&)	advection.cpp:101	exec
○	hydro(global_variables&, paral[...]	basic_string.h:1076	exec
○	main	new_allocator.h:104	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	new_allocator.h:104	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:71-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 7% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 12.00 to 0.75 cycles (16.00x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 9.75 cycles (1.23x speedup).

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:74

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	80
nb uops	78
loop length	278
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 431f70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x4,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
DEC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ESI,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 432573 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x603>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 432573 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x603>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 43259b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x62b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R8D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 432573 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x603>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x18(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ 0x8(%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x14(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x18(%RDI),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ (%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 431ff7 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_5

Source file and lines	advec_mom.cpp:71-75
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:71-75

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.00 to 1.50 cycles (8.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:

If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.00 to 9.50 cycles (1.26x speedup).

CALL instructions

Detected function call instructions.

Details

omp_get_num_threads@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73
omp_get_thread_num@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

DIV: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:73
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:74

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 28 bytes.

General properties

nb instructions	80
nb uops	78
loop length	278
used x86 registers	15
used mmx registers	0
used xmm registers	4
used ymm registers	0
used zmm registers	0
nb stack references	6

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	9.75 cycles
front end	9.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	5.67	5.67	5.67	5.67	5.67	5.67	4.75	4.75	4.75	4.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

12.00

Cycles summary

Front-end	9.75
Dispatch	5.67
DIV/SQRT	12.00
Overall L1	12.00

Vectorization ratios

all	3%
load	0%
store	0%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	0%
other	10%

Vector efficiency ratios

all	7%
load	9%
store	7%
mul	6%
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	6%
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.00 cycles. At this rate:

2% of peak load performance is reached (5.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
1% of peak store performance is reached (2.33 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 431f70

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB $0x40,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV 0x28(%RDI),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x2c(%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV 0x20(%RDI),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x24(%RDI),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
ADD $0x4,%ESI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
DEC %ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA -0x1(%RAX),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %ESI,0x1c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %ECX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %ESI,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 432573 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x603>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ESI,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
LEA 0x4(%RDX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
SUB %EBX,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JGE 432573 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x603>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R15D,%R13D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
SUB %ECX,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
IMUL %R13D,%R14D	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	scal (6.3%)
MOV %R13D,0x14(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CALL 404630 <omp_get_num_threads@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
MOV %EAX,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
CALL 404520 <omp_get_thread_num@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R14D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
DIV %R12D	2	0	0	0	2	0	0	0	0	0	0	10-17	6	scal (6.3%)
CMP %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EAX,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
JB 43259b <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x62b>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
IMUL %R9D,%ECX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	3	0.33	N/A
ADD %EDX,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
LEA (%R9,%RCX,1),%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV %R8D,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
CMP %R8D,%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
JAE 432573 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x603>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %ECX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
MOV 0x18(%RSP),%R10D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
VMOVQ 0x8(%RDI),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
DIVL 0x14(%RSP)	2	0	0	0	2	0	0	0.25	0.25	0.25	0.25	10-17	6	scal (6.3%)
VMOVQ 0x18(%RDI),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ (%RDI),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
VMOVQ 0x10(%RDI),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
ADD %R10D,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
ADD %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
SUB %EDX,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %EDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVSXD %EAX,%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
MOV %R9D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R15D,%R12D	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (6.3%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
INC %R9D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0.25	N/A
JMP 431ff7 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii._omp_fn.3+0x87>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	2.67	0.98
▼Loop 218 - advec_mom.cpp:73-75 - exec–	0.00	0.01
○Loop 219 - advec_mom.cpp:74-75 - exec	2.66	0.98

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Matching between your function (in the source code) and the binary function

General properties

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Vectorization ratios

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Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

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Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Expensive FP math instructions/calls

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code