OV - exec - Function advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer1D<double>&, clover::Buffer1D<double>&, int, int, int) [clone .extracted.7]

	Function: advec_mom_kernel(int, int, int, int, clover::Buffer2D<double>&, clover::Buffer2D<double>&, ...	Module: exec	Source: advec_mom.cpp:180-211 [...]	Coverage (incl. loops): 4.33% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 180 - 211

--------------------------------------------------------------------------------

180: #pragma omp parallel for simd collapse(2)

181:     for (int j = (y_min - 1 + 1); j < (y_max + 1 + 2); j++) {

182:       for (int i = (x_min + 1); i < (x_max + 1 + 2); i++)

183:         ({

184:           int upwind, donor, downwind, dif;

185:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

186:           if (node_flux(i, j) < 0.0) {

187:             upwind = j + 2;

188:             donor = j + 1;

189:             downwind = j;

190:             dif = donor;

191:           } else {

192:             upwind = j - 1;

193:             donor = j;

194:             downwind = j + 1;

195:             dif = upwind;

196:           }

197:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(i, donor));

198:           width = celldy[j];

199:           vdiffuw = vel1(i, donor) - vel1(i, upwind);

200:           vdiffdw = vel1(i, downwind) - vel1(i, donor);

201:           limiter = 0.0;

202:           if (vdiffuw * vdiffdw > 0.0) {

203:             auw = std::fabs(vdiffuw);

204:             adw = std::fabs(vdiffdw);

205:             wind = 1.0;

206:             if (vdiffdw <= 0.0) wind = -1.0;

207:             limiter =

208:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldy[dif]) / 6.0, auw), adw);

209:           }

210:           advec_vel_s = vel1(i, donor) + (1.0 - sigma) * limiter;

211:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

0x430350 PUSH	%RBP

0x430351 MOV	%RSP,%RBP

0x430354 PUSH	%R15

0x430356 PUSH	%R14

0x430358 PUSH	%R13

0x43035a PUSH	%R12

0x43035c PUSH	%RBX

0x43035d SUB	$0x68,%RSP

0x430361 MOV	%RCX,%R13

0x430364 MOV	0x38(%RBP),%RAX

0x430368 MOV	0x28(%RBP),%RBX

0x43036c MOV	0x20(%RBP),%RCX

0x430370 MOV	%RCX,-0x40(%RBP)

0x430374 MOV	0x10(%RBP),%RCX

0x430378 MOV	%RCX,-0x58(%RBP)

0x43037c MOV	0x18(%RBP),%ECX

0x43037f MOV	%ECX,-0x30(%RBP)

0x430382 MOVL	$0,-0x34(%RBP)

0x430389 TEST	%RAX,%RAX

0x43038c JS	43040a

0x43038e MOV	%R9,%R14

0x430391 MOV	%R8,%R12

0x430394 MOV	%RDX,%R15

0x430397 MOV	(%RDI),%ESI

0x430399 MOVQ	$0,-0x50(%RBP)

0x4303a1 MOV	%RAX,-0x48(%RBP)

0x4303a5 MOVQ	$0x1,-0x88(%RBP)

0x4303b0 SUB	$0x8,%RSP

0x4303b4 LEA	-0x88(%RBP),%RAX

0x4303bb LEA	-0x34(%RBP),%RCX

0x4303bf LEA	-0x50(%RBP),%R8

0x4303c3 LEA	-0x48(%RBP),%R9

0x4303c7 MOV	$0x491880,%EDI

0x4303cc MOV	%ESI,-0x2c(%RBP)

0x4303cf MOV	$0x22,%EDX

0x4303d4 PUSH	$0x1

0x4303d6 PUSH	$0x1

0x4303d8 PUSH	%RAX

0x4303d9 CALL	404230 <__kmpc_for_static_init_8@plt>

0x4303de ADD	$0x20,%RSP

0x4303e2 MOV	-0x50(%RBP),%RCX

0x4303e6 MOV	-0x48(%RBP),%RDI

0x4303ea CMP	%RDI,%RCX

0x4303ed JBE	430419

0x4303ef MOV	$0x4918a0,%EDI

0x4303f4 MOV	-0x2c(%RBP),%ESI

0x4303f7 ADD	$0x68,%RSP

0x4303fb POP	%RBX

0x4303fc POP	%R12

0x4303fe POP	%R13

0x430400 POP	%R14

0x430402 POP	%R15

0x430404 POP	%RBP

0x430405 JMP	404050

0x43040a ADD	$0x68,%RSP

0x43040e POP	%RBX

0x43040f POP	%R12

0x430411 POP	%R13

0x430413 POP	%R14

0x430415 POP	%R15

0x430417 POP	%RBP

0x430418 RET

0x430419 SUB	-0x40(%RBP),%EBX

0x43041c MOV	(%R13),%RAX

0x430420 MOV	%RAX,-0x80(%RBP)

0x430424 MOV	0x10(%R13),%RAX

0x430428 MOV	%RAX,-0x78(%RBP)

0x43042c MOV	(%R12),%RAX

0x430430 MOV	%RAX,-0x70(%RBP)

0x430434 MOV	0x10(%R12),%RAX

0x430439 MOV	%RAX,-0x68(%RBP)

0x43043d MOV	(%R15),%R13

0x430440 MOV	0x10(%R15),%R15

0x430444 MOV	(%R14),%RAX

0x430447 MOV	%RAX,-0x60(%RBP)

0x43044b MOV	0x10(%R14),%R14

0x43044f INC	%RDI

0x430452 XORPD	%XMM0,%XMM0

0x430456 MOVAPD	0x43672(%RIP),%XMM1

0x43045e MOVAPD	0x4366a(%RIP),%XMM2

0x430466 MOVSD	0x441f2(%RIP),%XMM3

0x43046e MOVSD	0x435f2(%RIP),%XMM4

0x430476 MOVSD	0x441ea(%RIP),%XMM5

0x43047e MOVAPD	0x441ca(%RIP),%XMM6

0x430486 MOV	-0x68(%RBP),%R12

0x43048a JMP	4304c3

0x43048c NOPL	(%RAX)

(287) 0x430490 MOVAPD	%XMM4,%XMM10

(287) 0x430495 SUBSD	%XMM8,%XMM10

(287) 0x43049a MULSD	%XMM12,%XMM10

(287) 0x43049f ADDSD	%XMM9,%XMM10

(287) 0x4304a4 MULSD	%XMM7,%XMM10

(287) 0x4304a9 IMUL	-0x60(%RBP),%R11

(287) 0x4304ae ADD	%RAX,%R11

(287) 0x4304b1 MOVSD	%XMM10,(%R14,%R11,8)

(287) 0x4304b7 INC	%RCX

(287) 0x4304ba CMP	%RCX,%RDI

(287) 0x4304bd JE	4303ef

(287) 0x4304c3 MOV	%RCX,%R8

(287) 0x4304c6 SHR	$0x20,%R8

(287) 0x4304ca JE	4304f0

(287) 0x4304cc MOV	%RCX,%RAX

(287) 0x4304cf XOR	%EDX,%EDX

(287) 0x4304d1 DIV	%RBX

(287) 0x4304d4 MOV	%RAX,%RSI

(287) 0x4304d7 TEST	%R8,%R8

(287) 0x4304da JE	4304fd

(287) 0x4304dc MOV	%RCX,%RAX

(287) 0x4304df CQTO

(287) 0x4304e1 IDIV	%RBX

(287) 0x4304e4 JMP	430503

0x4304e6 NOPW	%CS:(%RAX,%RAX,1)

(287) 0x4304f0 MOV	%ECX,%EAX

(287) 0x4304f2 XOR	%EDX,%EDX

(287) 0x4304f4 DIV	%EBX

(287) 0x4304f6 MOV	%EAX,%ESI

(287) 0x4304f8 TEST	%R8,%R8

(287) 0x4304fb JNE	4304dc

(287) 0x4304fd MOV	%ECX,%EAX

(287) 0x4304ff XOR	%EDX,%EDX

(287) 0x430501 DIV	%EBX

(287) 0x430503 ADD	-0x30(%RBP),%ESI

(287) 0x430506 ADD	-0x40(%RBP),%EDX

(287) 0x430509 MOVSXD	%EDX,%RAX

(287) 0x43050c MOVSXD	%ESI,%R11

(287) 0x43050f MOV	-0x80(%RBP),%RDX

(287) 0x430513 IMUL	%R11,%RDX

(287) 0x430517 ADD	%RAX,%RDX

(287) 0x43051a MOV	-0x78(%RBP),%R8

(287) 0x43051e MOVSD	(%R8,%RDX,8),%XMM7

(287) 0x430524 LEA	0x1(%R11),%R9D

(287) 0x430528 UCOMISD	%XMM7,%XMM0

(287) 0x43052c MOVSXD	%R9D,%R8

(287) 0x43052f JBE	430540

(287) 0x430531 ADD	$0x2,%ESI

(287) 0x430534 MOV	%R11,%RDX

(287) 0x430537 JMP	43054b

0x430539 NOPL	(%RAX)

(287) 0x430540 DEC	%ESI

(287) 0x430542 MOV	%R8,%RDX

(287) 0x430545 MOV	%R11,%R8

(287) 0x430548 MOV	%ESI,%R9D

(287) 0x43054b MOVAPD	%XMM7,%XMM8

(287) 0x430550 ANDPD	%XMM1,%XMM8

(287) 0x430555 MOV	-0x70(%RBP),%R10

(287) 0x430559 IMUL	%R8,%R10

(287) 0x43055d ADD	%RAX,%R10

(287) 0x430560 DIVSD	(%R12,%R10,8),%XMM8

(287) 0x430566 IMUL	%R13,%R8

(287) 0x43056a ADD	%RAX,%R8

(287) 0x43056d MOVSD	(%R15,%R8,8),%XMM9

(287) 0x430573 MOVSXD	%ESI,%RSI

(287) 0x430576 IMUL	%R13,%RSI

(287) 0x43057a ADD	%RAX,%RSI

(287) 0x43057d MOVAPD	%XMM9,%XMM10

(287) 0x430582 SUBSD	(%R15,%RSI,8),%XMM10

(287) 0x430588 IMUL	%R13,%RDX

(287) 0x43058c ADD	%RAX,%RDX

(287) 0x43058f MOVSD	(%R15,%RDX,8),%XMM11

(287) 0x430595 SUBSD	%XMM9,%XMM11

(287) 0x43059a MOVAPD	%XMM11,%XMM13

(287) 0x43059f MULSD	%XMM10,%XMM13

(287) 0x4305a4 XORPD	%XMM12,%XMM12

(287) 0x4305a9 UCOMISD	%XMM12,%XMM13

(287) 0x4305ae JBE	430490

(287) 0x4305b4 MOV	-0x58(%RBP),%RDX

(287) 0x4305b8 MOV	0x8(%RDX),%RDX

(287) 0x4305bc MOVSD	(%RDX,%R11,8),%XMM12

(287) 0x4305c2 ANDPD	%XMM2,%XMM10

(287) 0x4305c7 MOVAPD	%XMM11,%XMM13

(287) 0x4305cc ANDPD	%XMM2,%XMM13

(287) 0x4305d1 MOVAPD	%XMM3,%XMM14

(287) 0x4305d6 SUBSD	%XMM8,%XMM14

(287) 0x4305db MULSD	%XMM13,%XMM14

(287) 0x4305e0 DIVSD	%XMM12,%XMM14

(287) 0x4305e5 MOVAPD	%XMM8,%XMM15

(287) 0x4305ea ADDSD	%XMM4,%XMM15

(287) 0x4305ef MULSD	%XMM10,%XMM15

(287) 0x4305f4 MOVSXD	%R9D,%RSI

(287) 0x4305f7 DIVSD	(%RDX,%RSI,8),%XMM15

(287) 0x4305fd ADDSD	%XMM14,%XMM15

(287) 0x430602 MULSD	%XMM5,%XMM12

(287) 0x430607 MULSD	%XMM15,%XMM12

(287) 0x43060c MINSD	%XMM10,%XMM13

(287) 0x430611 MINSD	%XMM12,%XMM13

(287) 0x430616 XORPD	%XMM12,%XMM12

(287) 0x43061b CMPSD	$0x1,%XMM11,%XMM12

(287) 0x430621 MOVAPD	%XMM12,%XMM10

(287) 0x430626 ANDPD	%XMM13,%XMM10

(287) 0x43062b XORPD	%XMM6,%XMM13

(287) 0x430630 ANDNPD	%XMM13,%XMM12

(287) 0x430635 ORPD	%XMM10,%XMM12

(287) 0x43063a JMP	430490

0x43063f NOP

Coverage (%)	Name	Module
►47.69+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
○	__GI___clone3	libc.so.6
►39.84+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
►6.10+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]	libiomp5.so
○	start_thread	libc.so.6
►3.03+	__kmp_invoke_microtask	libiomp5.so
○	__kmp_invoke_task_func	libiomp5.so
○	__kmp_launch_thread	libiomp5.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_10

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.88 to 1.75 cycles (6.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 10.88 to 0.98 cycles (11.05x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 92 bytes.

General properties

nb instructions	90
nb uops	87
loop length	338
used x86 registers	14
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.88 cycles
front end	10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.67	3.67	3.67	3.67	3.67	3.67	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.67	3.67	3.67	3.67	3.67	3.67	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.88
Dispatch	9.75
Overall L1	10.88

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	57%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	11%
load	21%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	10%
load	9%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	19%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	13%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.88 cycles. At this rate:

7% of peak load performance is reached (19.13 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.46 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 10.88 to 9.75 cycles (1.12x speedup).

ASM code

In the binary file, the address of the function is: 430350

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x20(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %ECX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JS 43040a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0xba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x88(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x50(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x491880,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404230 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV -0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JBE 430419 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0xc9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV $0x4918a0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 404050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
SUB -0x40(%RBP),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R15),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R14),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD 0x43672(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVAPD 0x4366a(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD 0x441f2(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVSD 0x435f2(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVSD 0x441ea(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD 0x441ca(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOV -0x68(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 4304c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x173>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_10

Source file and lines	advec_mom.cpp:180-211
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180-211

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.88 to 1.75 cycles (6.21x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:180

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 208 bytes. The binary function is storing 92 bytes.

General properties

nb instructions	90
nb uops	87
loop length	338
used x86 registers	14
used mmx registers	0
used xmm registers	7
used ymm registers	0
used zmm registers	0
nb stack references	18

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	10.88 cycles
front end	10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.67	3.67	3.67	3.67	3.67	3.67	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.67	3.67	3.67	3.67	3.67	3.67	9.75	9.75	9.75	9.75	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.88
Dispatch	9.75
Overall L1	10.88

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	57%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	11%
load	21%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

Vector efficiency ratios

INT

all	10%
load	9%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	19%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	12%
load	13%
store	10%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	11%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.88 cycles. At this rate:

7% of peak load performance is reached (19.13 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.46 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 430350

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RCX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x28(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x20(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %RCX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV %RCX,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x18(%RBP),%ECX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOV %ECX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JS 43040a <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0xba>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOVQ $0,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0x88(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x34(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x50(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x48(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x491880,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (6.3%)
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404230 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x50(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV -0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
CMP %RDI,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JBE 430419 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0xc9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV $0x4918a0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x2c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 404050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD $0x68,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
SUB -0x40(%RBP),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	scal (6.3%)
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R15),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%R15),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R14),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R14),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
INC %RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
XORPD %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
MOVAPD 0x43672(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVAPD 0x4366a(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD 0x441f2(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVSD 0x435f2(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVSD 0x441ea(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD 0x441ca(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOV -0x68(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 4304c3 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.extracted.7+0x173>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clo...–	4.33	1.62
○Loop 287 - advec_mom.cpp:180-211 - exec	4.33	1.61

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