OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .extracted.7]

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:157-202 [...]	Coverage (incl. loops): 3.50% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 157 - 202

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:     for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) {

159:       for (int i = (x_min + 1); i < (x_max + 2); i++)

160:         ({

161:           int upwind, donor, downwind, dif;

162:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

163:           if (vol_flux_y(i, j) > 0.0) {

164:             upwind = j - 2;

165:             donor = j - 1;

166:             downwind = j;

167:             dif = donor;

168:           } else {

169:             upwind = std::min(j + 1, y_max + 2);

170:             donor = j;

171:             downwind = j - 1;

172:             dif = upwind;

173:           }

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x42e810 PUSH	%RBP

0x42e811 MOV	%RSP,%RBP

0x42e814 PUSH	%R15

0x42e816 PUSH	%R14

0x42e818 PUSH	%R13

0x42e81a PUSH	%R12

0x42e81c PUSH	%RBX

0x42e81d SUB	$0x98,%RSP

0x42e824 MOV	%RDX,-0x30(%RBP)

0x42e828 MOV	0x50(%RBP),%RAX

0x42e82c MOV	0x40(%RBP),%RSI

0x42e830 MOV	0x38(%RBP),%RDX

0x42e834 MOV	%RDX,-0x68(%RBP)

0x42e838 MOV	0x28(%RBP),%RBX

0x42e83c MOV	0x20(%RBP),%R15

0x42e840 MOV	0x18(%RBP),%R12

0x42e844 MOV	0x10(%RBP),%R13

0x42e848 MOV	0x30(%RBP),%EDX

0x42e84b MOV	%EDX,-0x50(%RBP)

0x42e84e MOVL	$0,-0x54(%RBP)

0x42e855 TEST	%RAX,%RAX

0x42e858 JS	42e8e7

0x42e85e MOV	%R9,%R14

0x42e861 MOV	%RCX,-0x38(%RBP)

0x42e865 MOV	%R8,-0x40(%RBP)

0x42e869 MOV	%RSI,-0x48(%RBP)

0x42e86d MOV	(%RDI),%ESI

0x42e86f MOVQ	$0,-0x80(%RBP)

0x42e877 MOV	%RAX,-0x78(%RBP)

0x42e87b MOVQ	$0x1,-0xb8(%RBP)

0x42e886 SUB	$0x8,%RSP

0x42e88a LEA	-0xb8(%RBP),%RAX

0x42e891 LEA	-0x54(%RBP),%RCX

0x42e895 LEA	-0x80(%RBP),%R8

0x42e899 LEA	-0x78(%RBP),%R9

0x42e89d MOV	$0x491580,%EDI

0x42e8a2 MOV	%ESI,-0x4c(%RBP)

0x42e8a5 MOV	$0x22,%EDX

0x42e8aa PUSH	$0x1

0x42e8ac PUSH	$0x1

0x42e8ae PUSH	%RAX

0x42e8af CALL	404230 <__kmpc_for_static_init_8@plt>

0x42e8b4 ADD	$0x20,%RSP

0x42e8b8 MOV	-0x80(%RBP),%RCX

0x42e8bc MOV	-0x78(%RBP),%RAX

0x42e8c0 MOV	%RAX,-0x60(%RBP)

0x42e8c4 CMP	%RAX,%RCX

0x42e8c7 JBE	42e8f9

0x42e8c9 MOV	$0x4915a0,%EDI

0x42e8ce MOV	-0x4c(%RBP),%ESI

0x42e8d1 ADD	$0x98,%RSP

0x42e8d8 POP	%RBX

0x42e8d9 POP	%R12

0x42e8db POP	%R13

0x42e8dd POP	%R14

0x42e8df POP	%R15

0x42e8e1 POP	%RBP

0x42e8e2 JMP	404050

0x42e8e7 ADD	$0x98,%RSP

0x42e8ee POP	%RBX

0x42e8ef POP	%R12

0x42e8f1 POP	%R13

0x42e8f3 POP	%R14

0x42e8f5 POP	%R15

0x42e8f7 POP	%RBP

0x42e8f8 RET

0x42e8f9 MOV	-0x48(%RBP),%RAX

0x42e8fd SUB	-0x68(%RBP),%EAX

0x42e900 MOV	%RAX,-0x48(%RBP)

0x42e904 MOV	(%R12),%RAX

0x42e908 MOV	%RAX,-0xb0(%RBP)

0x42e90f MOV	0x10(%R12),%RAX

0x42e914 MOV	%RAX,-0xa8(%RBP)

0x42e91b MOV	(%R15),%RAX

0x42e91e MOV	(%RAX),%RDX

0x42e921 MOV	%RDX,-0xa0(%RBP)

0x42e928 MOV	0x10(%RAX),%RAX

0x42e92c MOV	%RAX,-0x70(%RBP)

0x42e930 MOV	-0x38(%RBP),%RAX

0x42e934 MOV	0x8(%RAX),%RAX

0x42e938 MOV	%RAX,-0x98(%RBP)

0x42e93f MOV	-0x40(%RBP),%RAX

0x42e943 MOV	(%RAX),%RAX

0x42e946 MOV	%R14,%RDX

0x42e949 MOV	(%RAX),%R14

0x42e94c MOV	0x10(%RAX),%R12

0x42e950 MOV	(%R13),%RAX

0x42e954 MOV	%RAX,-0x40(%RBP)

0x42e958 MOV	0x10(%R13),%RAX

0x42e95c MOV	%RAX,-0x38(%RBP)

0x42e960 MOV	(%RDX),%R8

0x42e963 MOV	0x10(%RDX),%R10

0x42e967 MOV	(%RBX),%RAX

0x42e96a MOV	%RAX,-0x90(%RBP)

0x42e971 MOV	0x10(%RBX),%RAX

0x42e975 MOV	%RAX,-0x88(%RBP)

0x42e97c MOV	-0x30(%RBP),%RAX

0x42e980 ADD	$0x2,%EAX

0x42e983 MOV	%RAX,-0x30(%RBP)

0x42e987 INCQ	-0x60(%RBP)

0x42e98b MOVAPD	0x4513d(%RIP),%XMM1

0x42e993 MOVSD	0x450cd(%RIP),%XMM2

0x42e99b MOVSD	0x45cbd(%RIP),%XMM3

0x42e9a3 MOVAPD	0x45ca5(%RIP),%XMM4

0x42e9ab MOVAPD	0x4511d(%RIP),%XMM5

0x42e9b3 MOVSD	0x45cad(%RIP),%XMM6

0x42e9bb MOV	-0x38(%RBP),%R15

0x42e9bf JMP	42e9ff

0x42e9c1 NOPW	%CS:(%RAX,%RAX,1)

(279) 0x42e9d0 ADDSD	%XMM9,%XMM11

(279) 0x42e9d5 MULSD	%XMM10,%XMM11

(279) 0x42e9da IMUL	-0x90(%RBP),%R11

(279) 0x42e9e2 ADD	%RAX,%R11

(279) 0x42e9e5 MOV	-0x88(%RBP),%RAX

(279) 0x42e9ec MOVSD	%XMM11,(%RAX,%R11,8)

(279) 0x42e9f2 INC	%RCX

(279) 0x42e9f5 CMP	%RCX,-0x60(%RBP)

(279) 0x42e9f9 JE	42e8c9

(279) 0x42e9ff MOV	%RCX,%R9

(279) 0x42ea02 SHR	$0x20,%R9

(279) 0x42ea06 MOV	-0x48(%RBP),%RDI

(279) 0x42ea0a JE	42ea30

(279) 0x42ea0c MOV	%RCX,%RAX

(279) 0x42ea0f XOR	%EDX,%EDX

(279) 0x42ea11 DIV	%RDI

(279) 0x42ea14 MOV	%RAX,%RSI

(279) 0x42ea17 TEST	%R9,%R9

(279) 0x42ea1a JE	42ea3d

(279) 0x42ea1c MOV	%RCX,%RAX

(279) 0x42ea1f CQTO

(279) 0x42ea21 IDIV	%RDI

(279) 0x42ea24 JMP	42ea43

0x42ea26 NOPW	%CS:(%RAX,%RAX,1)

(279) 0x42ea30 MOV	%ECX,%EAX

(279) 0x42ea32 XOR	%EDX,%EDX

(279) 0x42ea34 DIV	%EDI

(279) 0x42ea36 MOV	%EAX,%ESI

(279) 0x42ea38 TEST	%R9,%R9

(279) 0x42ea3b JNE	42ea1c

(279) 0x42ea3d MOV	%ECX,%EAX

(279) 0x42ea3f XOR	%EDX,%EDX

(279) 0x42ea41 DIV	%EDI

(279) 0x42ea43 ADD	-0x50(%RBP),%ESI

(279) 0x42ea46 ADD	-0x68(%RBP),%EDX

(279) 0x42ea49 MOVSXD	%EDX,%RAX

(279) 0x42ea4c MOVSXD	%ESI,%R11

(279) 0x42ea4f MOV	-0xb0(%RBP),%RDX

(279) 0x42ea56 IMUL	%R11,%RDX

(279) 0x42ea5a ADD	%RAX,%RDX

(279) 0x42ea5d MOV	-0xa8(%RBP),%RDI

(279) 0x42ea64 MOVSD	(%RDI,%RDX,8),%XMM9

(279) 0x42ea6a XORPD	%XMM0,%XMM0

(279) 0x42ea6e UCOMISD	%XMM9,%XMM0

(279) 0x42ea73 JAE	42ea90

(279) 0x42ea75 LEA	-0x2(%RSI),%EDX

(279) 0x42ea78 DEC	%ESI

(279) 0x42ea7a MOVSXD	%ESI,%R13

(279) 0x42ea7d MOVSXD	%EDX,%R9

(279) 0x42ea80 MOV	%R11,%RSI

(279) 0x42ea83 MOV	%R13,%RDX

(279) 0x42ea86 JMP	42eaaa

0x42ea88 NOPL	(%RAX,%RAX,1)

(279) 0x42ea90 LEA	0x1(%RSI),%EDX

(279) 0x42ea93 MOV	-0x30(%RBP),%RDI

(279) 0x42ea97 CMP	%EDX,%EDI

(279) 0x42ea99 CMOVL	%EDI,%EDX

(279) 0x42ea9c DEC	%ESI

(279) 0x42ea9e MOVSXD	%ESI,%RSI

(279) 0x42eaa1 MOVSXD	%EDX,%R9

(279) 0x42eaa4 MOV	%R9,%R13

(279) 0x42eaa7 MOV	%R11,%RDX

(279) 0x42eaaa MOVAPD	%XMM9,%XMM13

(279) 0x42eaaf ANDPD	%XMM1,%XMM13

(279) 0x42eab4 MOV	-0xa0(%RBP),%RBX

(279) 0x42eabb IMUL	%RDX,%RBX

(279) 0x42eabf ADD	%RAX,%RBX

(279) 0x42eac2 MOV	-0x70(%RBP),%RDI

(279) 0x42eac6 DIVSD	(%RDI,%RBX,8),%XMM13

(279) 0x42eacc MOVAPD	%XMM13,%XMM7

(279) 0x42ead1 ADDSD	%XMM2,%XMM7

(279) 0x42ead5 MOV	-0x98(%RBP),%RDI

(279) 0x42eadc MULSD	(%RDI,%R11,8),%XMM7

(279) 0x42eae2 DIVSD	(%RDI,%R13,8),%XMM7

(279) 0x42eae8 MOVAPD	%XMM3,%XMM8

(279) 0x42eaed MOV	%R14,%R13

(279) 0x42eaf0 IMUL	%RDX,%R13

(279) 0x42eaf4 ADD	%RAX,%R13

(279) 0x42eaf7 MOVSD	(%R12,%R13,8),%XMM12

(279) 0x42eafd MOV	%R14,%RDI

(279) 0x42eb00 IMUL	%R9,%RDI

(279) 0x42eb04 ADD	%RAX,%RDI

(279) 0x42eb07 MOVAPD	%XMM12,%XMM15

(279) 0x42eb0c SUBSD	(%R12,%RDI,8),%XMM15

(279) 0x42eb12 SUBSD	%XMM13,%XMM8

(279) 0x42eb17 MOV	%R14,%RDI

(279) 0x42eb1a IMUL	%RSI,%RDI

(279) 0x42eb1e ADD	%RAX,%RDI

(279) 0x42eb21 MOVSD	(%R12,%RDI,8),%XMM14

(279) 0x42eb27 SUBSD	%XMM12,%XMM14

(279) 0x42eb2c MOVAPD	%XMM14,%XMM10

(279) 0x42eb31 MULSD	%XMM15,%XMM10

(279) 0x42eb36 XORPD	%XMM11,%XMM11

(279) 0x42eb3b UCOMISD	%XMM11,%XMM10

(279) 0x42eb40 XORPD	%XMM10,%XMM10

(279) 0x42eb45 JBE	42ebac

(279) 0x42eb47 MOVAPD	%XMM2,%XMM10

(279) 0x42eb4c SUBSD	%XMM13,%XMM10

(279) 0x42eb51 XORPD	%XMM13,%XMM13

(279) 0x42eb56 CMPSD	$0x1,%XMM14,%XMM13

(279) 0x42eb5c MOVAPD	%XMM13,%XMM0

(279) 0x42eb61 ANDPD	%XMM10,%XMM0

(279) 0x42eb66 XORPD	%XMM4,%XMM10

(279) 0x42eb6b ANDNPD	%XMM10,%XMM13

(279) 0x42eb70 ORPD	%XMM0,%XMM13

(279) 0x42eb75 ANDPD	%XMM5,%XMM15

(279) 0x42eb7a ANDPD	%XMM5,%XMM14

(279) 0x42eb7f MOVAPD	%XMM15,%XMM0

(279) 0x42eb84 MINSD	%XMM14,%XMM0

(279) 0x42eb89 MULSD	%XMM7,%XMM15

(279) 0x42eb8e MULSD	%XMM8,%XMM14

(279) 0x42eb93 ADDSD	%XMM15,%XMM14

(279) 0x42eb98 MULSD	%XMM6,%XMM14

(279) 0x42eb9d MINSD	%XMM0,%XMM14

(279) 0x42eba2 MULSD	%XMM13,%XMM14

(279) 0x42eba7 MOVAPD	%XMM14,%XMM10

(279) 0x42ebac ADDSD	%XMM12,%XMM10

(279) 0x42ebb1 MULSD	%XMM9,%XMM10

(279) 0x42ebb6 MOV	-0x40(%RBP),%RDI

(279) 0x42ebba IMUL	%R11,%RDI

(279) 0x42ebbe ADD	%RAX,%RDI

(279) 0x42ebc1 MOVSD	%XMM10,(%R15,%RDI,8)

(279) 0x42ebc7 IMUL	%R8,%RDX

(279) 0x42ebcb ADD	%RAX,%RDX

(279) 0x42ebce MOVSD	(%R10,%RDX,8),%XMM9

(279) 0x42ebd4 IMUL	%R8,%R9

(279) 0x42ebd8 ADD	%RAX,%R9

(279) 0x42ebdb MOVAPD	%XMM9,%XMM13

(279) 0x42ebe0 SUBSD	(%R10,%R9,8),%XMM13

(279) 0x42ebe6 IMUL	%R8,%RSI

(279) 0x42ebea ADD	%RAX,%RSI

(279) 0x42ebed MOVSD	(%R10,%RSI,8),%XMM12

(279) 0x42ebf3 SUBSD	%XMM9,%XMM12

(279) 0x42ebf8 MOVAPD	%XMM12,%XMM0

(279) 0x42ebfd MULSD	%XMM13,%XMM0

(279) 0x42ec02 UCOMISD	%XMM11,%XMM0

(279) 0x42ec07 JBE	42e9d0

(279) 0x42ec0d MOVAPD	%XMM10,%XMM0

(279) 0x42ec12 ANDPD	%XMM5,%XMM0

(279) 0x42ec16 MOV	-0x70(%RBP),%RDX

(279) 0x42ec1a MOVSD	(%RDX,%RBX,8),%XMM11

(279) 0x42ec20 MULSD	(%R12,%R13,8),%XMM11

(279) 0x42ec26 DIVSD	%XMM11,%XMM0

(279) 0x42ec2b MOVAPD	%XMM2,%XMM11

(279) 0x42ec30 SUBSD	%XMM0,%XMM11

(279) 0x42ec35 XORPD	%XMM0,%XMM0

(279) 0x42ec39 CMPSD	$0x1,%XMM12,%XMM0

(279) 0x42ec3f MOVAPD	%XMM0,%XMM14

(279) 0x42ec44 ANDPD	%XMM11,%XMM14

(279) 0x42ec49 XORPD	%XMM4,%XMM11

(279) 0x42ec4e ANDNPD	%XMM11,%XMM0

(279) 0x42ec53 ORPD	%XMM14,%XMM0

(279) 0x42ec58 ANDPD	%XMM5,%XMM13

(279) 0x42ec5d ANDPD	%XMM5,%XMM12

(279) 0x42ec62 MOVAPD	%XMM13,%XMM11

(279) 0x42ec67 MINSD	%XMM12,%XMM11

(279) 0x42ec6c MULSD	%XMM7,%XMM13

(279) 0x42ec71 MULSD	%XMM8,%XMM12

(279) 0x42ec76 ADDSD	%XMM13,%XMM12

(279) 0x42ec7b MULSD	%XMM6,%XMM12

(279) 0x42ec80 MINSD	%XMM11,%XMM12

(279) 0x42ec85 MULSD	%XMM0,%XMM12

(279) 0x42ec8a MOVAPD	%XMM12,%XMM11

(279) 0x42ec8f JMP	42e9d0

0x42ec94 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module
►47.78+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
○	__GI___clone3		libc.so.6
►39.75+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
►6.10+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
○	_INTERNALea951ae6::__kmp_launc[...]		libiomp5.so
○	start_thread		libc.so.6
►3.09+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_launch_thread		libiomp5.so
►1.41+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:157	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection	advection.cpp:81	exec
○	hydro	basic_string.h:1024	exec
○	main	clover_leaf.cpp:208	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	definitions.cpp:0	exec
►1.37+	__kmp_invoke_microtask		libiomp5.so
○	__kmp_invoke_task_func		libiomp5.so
○	__kmp_fork_call		libiomp5.so
○	__kmpc_fork_call		libiomp5.so
○	advec_cell_kernel(int, int, in[...]	advec_cell.cpp:157	exec
○	advec_cell_driver(global_varia[...]	advec_cell.cpp:232	exec
○	advection	advection.cpp:50	exec
○	hydro	basic_string.h:1024	exec
○	main	clover_leaf.cpp:208	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	definitions.cpp:0	exec

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_10

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-202
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 1.75 cycles (9.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.00 to 1.55 cycles (10.34x speedup).

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

23% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 16.00 to 13.63 cycles (1.17x speedup).

Workaround

Read less array elements
Write less array elements

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 328 bytes. The binary function is storing 180 bytes.

General properties

nb instructions	112
nb uops	109
loop length	478
used x86 registers	15
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.63 cycles
front end	13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	16.00	16.00	16.00	16.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	16.00	16.00	16.00	16.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.63
Dispatch	16.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	23%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	10%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	18%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	14%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

8% of peak load performance is reached (20.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (11.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42e810

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x40(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x38(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x28(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RBP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x54(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JS 42e8e7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xd7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOVQ $0,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xb8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x54(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x80(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x78(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x491580,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404230 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x80(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JBE 42e8f9 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xe9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV $0x4915a0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x4c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 404050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB -0x68(%RBP),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R15),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RAX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INCQ -0x60(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	N/A
MOVAPD 0x4513d(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD 0x450cd(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVSD 0x45cbd(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD 0x45ca5(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVAPD 0x4511d(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD 0x45cad(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 42e9ff <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x1ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run icx_10

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-202
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.00 to 1.75 cycles (9.14x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

23% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 16.00 to 13.63 cycles (1.17x speedup).

Workaround

Read less array elements
Write less array elements

No data for this section

CALL instructions

Detected function call instructions.

Details

__kmpc_for_static_init_8@plt: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 328 bytes. The binary function is storing 180 bytes.

General properties

nb instructions	112
nb uops	109
loop length	478
used x86 registers	15
used mmx registers	0
used xmm registers	6
used ymm registers	0
used zmm registers	0
nb stack references	27

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.63 cycles
front end	13.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	3.83	3.83	3.83	3.83	3.83	3.83	16.00	16.00	16.00	16.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.83	3.83	3.83	3.83	3.83	3.83	16.00	16.00	16.00	16.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.63
Dispatch	16.00
Overall L1	16.00

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	50%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	23%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	10%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	18%
load	18%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	14%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.00 cycles. At this rate:

8% of peak load performance is reached (20.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (11.25 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 42e810

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV %RDX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x40(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x38(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x28(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x20(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x18(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x10(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x30(%RBP),%EDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %EDX,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOVL $0,-0x54(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
TEST %RAX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JS 42e8e7 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xd7>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RCX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %R8,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV %RSI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
MOVQ $0,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOVQ $0x1,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
LEA -0xb8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x54(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x80(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
LEA -0x78(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.25	N/A
MOV $0x491580,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %ESI,-0x4c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 404230 <__kmpc_for_static_init_8@plt>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
MOV -0x80(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
CMP %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
JBE 42e8f9 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0xe9>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50-1	N/A
MOV $0x4915a0,%EDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV -0x4c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (6.3%)
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
JMP 404050 <__kmpc_for_static_fini@plt>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	scal (12.5%)
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	1	0.50	N/A
MOV -0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
SUB -0x68(%RBP),%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.25	N/A
MOV %RAX,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R12),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%R15),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RDX,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV 0x8(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x40(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %R14,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV (%RAX),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV (%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%R13),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV (%RDX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	scal (12.5%)
MOV (%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	1	0.17	N/A
MOV %RAX,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	4	0.50	scal (12.5%)
INCQ -0x60(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	1	0.50	N/A
MOVAPD 0x4513d(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD 0x450cd(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVSD 0x45cbd(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOVAPD 0x45ca5(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVAPD 0x4511d(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.50	vect (25.0%)
MOVSD 0x45cad(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.50	scal (12.5%)
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	3	0.25	N/A
JMP 42e9ff <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.extracted.7+0x1ef>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.50	1.31
○Loop 279 - advec_cell.cpp:157-202 - exec	3.50	1.31

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Code clean check

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CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code