OV - exec - Loop 208

	Loop Id: 208	Module: exec	Source: field_summary.cpp:76-91 [...]	Coverage: 0.29%

0x23d330 MOV	%EAX,0x94(%RSP)    [6]

0x23d337 VPEXTRD	$0x1,%XMM1,%EAX

0x23d33d VPEXTRD	$0x1,%XMM2,%ESI

0x23d343 VMOVAPD	%YMM8,0x1e0(%RSP)    [6]

0x23d34c VMOVD	%XMM2,%EDI

0x23d350 VMOVD	%XMM2,%R10D

0x23d355 VPCMPEQD	%YMM14,%YMM14,%YMM14

0x23d35a CLTD

0x23d35b IDIV	%ESI

0x23d35d MOV	%EAX,%ESI

0x23d35f VMOVD	%XMM1,%EAX

0x23d363 CLTD

0x23d364 IDIV	%EDI

0x23d366 VPEXTRD	$0x2,%XMM1,%EDX

0x23d36c VPEXTRD	$0x2,%XMM2,%EDI

0x23d372 VMOVD	%EAX,%XMM3

0x23d376 MOV	%EDX,%EAX

0x23d378 CLTD

0x23d379 IDIV	%EDI

0x23d37b VPINSRD	$0x1,%ESI,%XMM3,%XMM3

0x23d381 VPEXTRD	$0x3,%XMM2,%ESI

0x23d387 VPADDD	0x110(%RSP),%XMM1,%XMM4    [6]

0x23d390 MOV	%EAX,%EDI

0x23d392 VPEXTRD	$0x3,%XMM1,%EAX

0x23d398 VPINSRD	$0x2,%EDI,%XMM3,%XMM3

0x23d39e VPEXTRD	$0x1,%XMM2,%EDI

0x23d3a4 CLTD

0x23d3a5 IDIV	%ESI

0x23d3a7 MOV	%EAX,%ESI

0x23d3a9 VPEXTRD	$0x1,%XMM4,%EAX

0x23d3af VPINSRD	$0x3,%ESI,%XMM3,%XMM3

0x23d3b5 VPEXTRD	$0x2,%XMM2,%ESI

0x23d3bb CLTD

0x23d3bc VPMULLD	%XMM2,%XMM3,%XMM9

0x23d3c1 IDIV	%EDI

0x23d3c3 VPSUBD	%XMM9,%XMM1,%XMM9

0x23d3c8 MOV	%EAX,%EDI

0x23d3ca VMOVD	%XMM4,%EAX

0x23d3ce CLTD

0x23d3cf IDIV	%R10D

0x23d3d2 VPEXTRD	$0x2,%XMM4,%EDX

0x23d3d8 VMOVD	%EAX,%XMM8

0x23d3dc MOV	%EDX,%EAX

0x23d3de CLTD

0x23d3df IDIV	%ESI

0x23d3e1 VPINSRD	$0x1,%EDI,%XMM8,%XMM8

0x23d3e7 VPEXTRD	$0x3,%XMM2,%EDI

0x23d3ed MOV	%EAX,%ESI

0x23d3ef VPEXTRD	$0x3,%XMM4,%EAX

0x23d3f5 VPINSRD	$0x2,%ESI,%XMM8,%XMM8

0x23d3fb CLTD

0x23d3fc IDIV	%EDI

0x23d3fe VMOVDQA	0x120(%RSP),%XMM11    [6]

0x23d407 VPADDD	0x100(%RSP),%XMM1,%XMM1    [6]

0x23d410 VPADDD	%XMM3,%XMM11,%XMM3

0x23d414 VPMOVSXDQ	%XMM3,%YMM27

0x23d41a VPINSRD	$0x3,%EAX,%XMM8,%XMM8

0x23d420 VPMULLD	%XMM2,%XMM8,%XMM10

0x23d425 VPADDD	%XMM8,%XMM11,%XMM8

0x23d42a VPMOVSXDQ	%XMM8,%YMM24

0x23d430 VPSUBD	%XMM10,%XMM4,%XMM4

0x23d435 VMOVDQA	0x130(%RSP),%XMM10    [6]

0x23d43e VPMULLQ	%YMM24,%YMM6,%YMM16

0x23d444 VPADDD	%XMM9,%XMM10,%XMM9

0x23d449 VPADDD	%XMM4,%XMM10,%XMM3

0x23d44d VPMULLQ	%YMM24,%YMM5,%YMM10

0x23d453 VPMULLQ	%YMM27,%YMM6,%YMM4

0x23d459 VPMOVSXDQ	%XMM9,%YMM26

0x23d45f VPMULLQ	%YMM27,%YMM5,%YMM9

0x23d465 VPMOVSXDQ	%XMM3,%YMM25

0x23d46b VPADDQ	%YMM25,%YMM10,%YMM8

0x23d471 VPADDQ	%YMM25,%YMM16,%YMM17

0x23d477 VPSUBQ	%YMM14,%YMM25,%YMM29

0x23d47d VPSUBQ	%YMM14,%YMM26,%YMM30

0x23d483 VPADDQ	%YMM26,%YMM9,%YMM3

0x23d489 VMOVQ	%XMM8,0x20(%RSP)    [6]

0x23d48f VPEXTRQ	$0x1,%XMM8,0x18(%RSP)    [6]

0x23d497 VEXTRACTI128	$0x1,%YMM8,%XMM8

0x23d49d VPEXTRQ	$0x1,%XMM17,0x38(%RSP)    [6]

0x23d4a6 VMOVQ	%XMM17,%RSI

0x23d4ac VPADDQ	%YMM16,%YMM29,%YMM16

0x23d4b2 VMOVQ	%XMM3,%RDX

0x23d4b7 VPEXTRQ	$0x1,%XMM3,%RDI

0x23d4bd VEXTRACTI128	$0x1,%YMM3,%XMM3

0x23d4c3 VPEXTRQ	$0x1,%XMM8,0x28(%RSP)    [6]

0x23d4cb VMOVQ	%XMM3,%R10

0x23d4d0 VMOVSD	(%R14,%RDX,8),%XMM11    [5]

0x23d4d6 VPEXTRQ	$0x1,%XMM3,%R15

0x23d4dc VMOVSD	(%R14,%R10,8),%XMM3    [5]

0x23d4e2 VMOVHPD	(%R14,%RDI,8),%XMM11,%XMM11    [5]

0x23d4e8 MOV	0x20(%RSP),%RDI    [6]

0x23d4ed VMOVHPD	(%R14,%R15,8),%XMM3,%XMM3    [5]

0x23d4f3 VMOVQ	%XMM8,%R15

0x23d4f8 VEXTRACTI32X4	$0x1,%YMM17,%XMM8

0x23d4ff VPEXTRQ	$0x1,%XMM8,0x20(%RSP)    [6]

0x23d507 VMOVSD	(%R14,%R15,8),%XMM17    [5]

0x23d50e VINSERTF128	$0x1,%XMM3,%YMM11,%YMM3

0x23d514 VPADDQ	%YMM26,%YMM4,%YMM11

0x23d51a VPADDQ	%YMM4,%YMM30,%YMM4

0x23d520 VMOVQ	%XMM11,%R13

0x23d525 VPEXTRQ	$0x1,%XMM11,%R10

0x23d52b VEXTRACTI128	$0x1,%YMM11,%XMM11

0x23d531 VMOVQ	%XMM11,%RAX

0x23d536 VMOVSD	(%R12,%R13,8),%XMM28    [4]

0x23d53d VPEXTRQ	$0x1,%XMM11,%RDX

0x23d543 VMOVSD	(%R14,%RDI,8),%XMM11    [5]

0x23d549 VMOVQ	%XMM8,%RDI

0x23d54e VMULPD	%YMM3,%YMM3,%YMM3

0x23d552 MOV	0x28(%RSP),%R13    [6]

0x23d557 VMOVSD	(%R12,%RAX,8),%XMM8    [4]

0x23d55d VMOVHPD	(%R12,%R10,8),%XMM28,%XMM28    [4]

0x23d564 MOV	0x18(%RSP),%RAX    [6]

0x23d569 VPEXTRQ	$0x1,%XMM16,0x18(%RSP)    [6]

0x23d572 VMOVHPD	(%R12,%RDX,8),%XMM8,%XMM8    [4]

0x23d578 VMOVHPD	(%R14,%RAX,8),%XMM11,%XMM11    [5]

0x23d57e VINSERTF32X4	$0x1,%XMM8,%YMM28,%YMM8

0x23d585 VMOVSD	(%R12,%RSI,8),%XMM28    [4]

0x23d58c VFMADD213PD	%YMM3,%YMM8,%YMM8

0x23d591 VPADDQ	%YMM9,%YMM30,%YMM3

0x23d597 VPADDQ	%YMM10,%YMM29,%YMM9

0x23d59d VMOVSD	(%R12,%RDI,8),%XMM10    [4]

0x23d5a3 MOV	0x38(%RSP),%RDI    [6]

0x23d5a8 VMOVQ	%XMM3,%RAX

0x23d5ad VPEXTRQ	$0x1,%XMM3,%RDX

0x23d5b3 VEXTRACTI128	$0x1,%YMM3,%XMM3

0x23d5b9 VMOVQ	%XMM9,%R10

0x23d5be VPEXTRQ	$0x1,%XMM9,%R15

0x23d5c4 VPEXTRQ	$0x1,%XMM3,%RSI

0x23d5ca VMOVHPD	(%R12,%RDI,8),%XMM28,%XMM28    [4]

0x23d5d1 VMOVQ	%XMM3,%RDI

0x23d5d6 VEXTRACTI128	$0x1,%YMM9,%XMM3

0x23d5dc VMOVHPD	(%R14,%R13,8),%XMM17,%XMM9    [5]

0x23d5e3 VMOVSD	(%R14,%RAX,8),%XMM17    [5]

0x23d5ea VMOVQ	%XMM3,%R13

0x23d5ef VPEXTRQ	$0x1,%XMM3,0x28(%RSP)    [6]

0x23d5f7 VMOVSD	(%R14,%RDI,8),%XMM3    [5]

0x23d5fd VMOVHPD	(%R14,%RDX,8),%XMM17,%XMM17    [5]

0x23d604 VMOVQ	%XMM4,%RDI

0x23d609 VMOVHPD	(%R14,%RSI,8),%XMM3,%XMM3    [5]

0x23d60f MOV	0x28(%RSP),%RAX    [6]

0x23d614 VMOVSD	(%R14,%R13,8),%XMM31    [5]

0x23d61b MOV	0x20(%RSP),%RSI    [6]

0x23d620 VMOVHPD	(%R14,%RAX,8),%XMM31,%XMM31    [5]

0x23d627 VMOVHPD	(%R12,%RSI,8),%XMM10,%XMM10    [4]

0x23d62d VMOVQ	%XMM16,%RAX

0x23d633 VINSERTF128	$0x1,%XMM9,%YMM11,%YMM11

0x23d639 VMOVSD	(%R12,%RDI,8),%XMM9    [4]

0x23d63f VINSERTF32X4	$0x1,%XMM3,%YMM17,%YMM3

0x23d646 VMOVSD	(%R14,%R10,8),%XMM17    [5]

0x23d64d VPEXTRQ	$0x1,%XMM4,%R10

0x23d653 VEXTRACTI128	$0x1,%YMM4,%XMM4

0x23d659 VMULPD	%YMM11,%YMM11,%YMM11

0x23d65e VMOVHPD	(%R14,%R15,8),%XMM17,%XMM17    [5]

0x23d665 VMOVQ	%XMM4,%R15

0x23d66a VPEXTRQ	$0x1,%XMM4,%R13

0x23d670 VEXTRACTI32X4	$0x1,%YMM16,%XMM4

0x23d677 VMOVHPD	(%R12,%R10,8),%XMM9,%XMM9    [4]

0x23d67d VMOVSD	(%R12,%RAX,8),%XMM16    [4]

0x23d684 VMOVQ	%XMM4,%RDX

0x23d689 VPEXTRQ	$0x1,%XMM4,%RSI

0x23d68f VMOVSD	(%R12,%R15,8),%XMM4    [4]

0x23d695 VFMADD213PD	%YMM8,%YMM3,%YMM3

0x23d69a VPSUBQ	%YMM14,%YMM27,%YMM8

0x23d6a0 VMOVHPD	(%R12,%R13,8),%XMM4,%XMM4    [4]

0x23d6a6 VPMULLQ	%YMM5,%YMM8,%YMM15

0x23d6ac VPMULLQ	%YMM6,%YMM8,%YMM8

0x23d6b2 VINSERTF32X4	$0x1,%XMM31,%YMM17,%YMM31

0x23d6b9 VMOVSD	(%R12,%RDX,8),%XMM17    [4]

0x23d6c0 MOV	0x18(%RSP),%RDX    [6]

0x23d6c5 VMOVHPD	(%R12,%RSI,8),%XMM17,%XMM17    [4]

0x23d6cc VINSERTF128	$0x1,%XMM4,%YMM9,%YMM9

0x23d6d2 VINSERTF32X4	$0x1,%XMM10,%YMM28,%YMM4

0x23d6d9 VPSUBQ	%YMM14,%YMM24,%YMM28

0x23d6df VPMULLQ	%YMM5,%YMM28,%YMM10

0x23d6e5 VPMULLQ	%YMM6,%YMM28,%YMM18

0x23d6eb VFMADD231PD	%YMM9,%YMM9,%YMM3

0x23d6f0 VPADDQ	%YMM26,%YMM15,%YMM9

0x23d6f6 VFMADD213PD	%YMM11,%YMM4,%YMM4

0x23d6fb VMOVHPD	(%R12,%RDX,8),%XMM16,%XMM16    [4]

0x23d702 VMOVQ	%XMM9,%RAX

0x23d707 VPEXTRQ	$0x1,%XMM9,%RDI

0x23d70d VEXTRACTI128	$0x1,%YMM9,%XMM9

0x23d713 VMOVQ	%XMM9,%R13

0x23d718 VPEXTRQ	$0x1,%XMM9,%R10

0x23d71e VPADDQ	%YMM25,%YMM10,%YMM9

0x23d724 VPADDQ	%YMM10,%YMM29,%YMM10

0x23d72a VMOVQ	%XMM9,0x18(%RSP)    [6]

0x23d730 VPEXTRQ	$0x1,%XMM9,0x28(%RSP)    [6]

0x23d738 VEXTRACTI128	$0x1,%YMM9,%XMM9

0x23d73e VMOVSD	(%R14,%R13,8),%XMM14    [5]

0x23d744 VPEXTRQ	$0x1,%XMM10,%R13

0x23d74a VMOVQ	%XMM9,%R15

0x23d74f VPEXTRQ	$0x1,%XMM9,0x20(%RSP)    [6]

0x23d757 VMOVHPD	(%R14,%R10,8),%XMM14,%XMM14    [5]

0x23d75d MOV	0x18(%RSP),%R10    [6]

0x23d762 VFMADD213PD	%YMM4,%YMM31,%YMM31

0x23d768 VINSERTF32X4	$0x1,%XMM17,%YMM16,%YMM9

0x23d76f VMOVSD	(%R14,%RAX,8),%XMM16    [5]

0x23d776 VMOVHPD	(%R14,%RDI,8),%XMM16,%XMM16    [5]

0x23d77d VFMADD231PD	%YMM9,%YMM9,%YMM31

0x23d783 VINSERTF32X4	$0x1,%XMM14,%YMM16,%YMM16

0x23d78a VPADDQ	%YMM26,%YMM8,%YMM14

0x23d790 VPADDQ	%YMM8,%YMM30,%YMM8

0x23d796 VMOVQ	%XMM14,%RSI

0x23d79b VPEXTRQ	$0x1,%XMM14,%RDI

0x23d7a1 VEXTRACTI128	$0x1,%YMM14,%XMM14

0x23d7a7 VPEXTRQ	$0x1,%XMM14,%RDX

0x23d7ad VMOVQ	%XMM14,%RAX

0x23d7b2 VPADDQ	%YMM25,%YMM18,%YMM14

0x23d7b8 VFMADD213PD	%YMM3,%YMM16,%YMM16

0x23d7be VMOVSD	(%R14,%R15,8),%XMM3    [5]

0x23d7c4 VMOVQ	%XMM10,%R15

0x23d7c9 VEXTRACTI128	$0x1,%YMM10,%XMM10

0x23d7cf VMOVQ	%XMM14,0x38(%RSP)    [6]

0x23d7d5 VPEXTRQ	$0x1,%XMM14,0x50(%RSP)    [6]

0x23d7dd VEXTRACTI128	$0x1,%YMM14,%XMM14

0x23d7e3 VPEXTRQ	$0x1,%XMM10,0x18(%RSP)    [6]

0x23d7eb VMOVQ	%XMM14,0xc8(%RSP)    [6]

0x23d7f4 VPEXTRQ	$0x1,%XMM14,0xd0(%RSP)    [6]

0x23d7ff VMOVSD	(%R12,%RAX,8),%XMM14    [4]

0x23d805 VMOVHPD	(%R12,%RDX,8),%XMM14,%XMM11    [4]

0x23d80b VMOVSD	(%R12,%RSI,8),%XMM14    [4]

0x23d811 MOV	0x20(%RSP),%RSI    [6]

0x23d816 VMOVHPD	(%R12,%RDI,8),%XMM14,%XMM14    [4]

0x23d81c VMOVHPD	(%R14,%RSI,8),%XMM3,%XMM3    [5]

0x23d822 VINSERTF32X4	$0x1,%XMM11,%YMM14,%YMM17

0x23d829 VPADDQ	%YMM15,%YMM30,%YMM11

0x23d82f VMOVQ	%XMM11,%RAX

0x23d834 VPEXTRQ	$0x1,%XMM11,%RDX

0x23d83a VEXTRACTI128	$0x1,%YMM11,%XMM11

0x23d840 VMOVQ	%XMM11,%RSI

0x23d845 VPEXTRQ	$0x1,%XMM11,%RDI

0x23d84b VMOVSD	(%R14,%R10,8),%XMM11    [5]

0x23d851 MOV	0x28(%RSP),%R10    [6]

0x23d856 VFMADD231PD	%YMM17,%YMM17,%YMM16

0x23d85c VMOVSD	(%R14,%RSI,8),%XMM4    [5]

0x23d862 VMOVQ	%XMM8,%RSI

0x23d867 VMOVHPD	(%R14,%RDI,8),%XMM4,%XMM4    [5]

0x23d86d MOV	0x18(%RSP),%RDI    [6]

0x23d872 VMOVHPD	(%R14,%R10,8),%XMM11,%XMM11    [5]

0x23d878 VMOVQ	%XMM10,%R10

0x23d87d VMOVSD	(%R14,%RAX,8),%XMM10    [5]

0x23d883 MOV	0xc8(%RSP),%RAX    [6]

0x23d88b VMOVHPD	(%R14,%RDX,8),%XMM10,%XMM10    [5]

0x23d891 VPEXTRQ	$0x1,%XMM8,%RDX

0x23d897 VEXTRACTI128	$0x1,%YMM8,%XMM8

0x23d89d VMOVSD	(%R14,%R10,8),%XMM15    [5]

0x23d8a3 VMOVQ	%XMM8,%R10

0x23d8a8 VINSERTF32X4	$0x1,%XMM4,%YMM10,%YMM28

0x23d8af VMOVSD	(%R12,%RAX,8),%XMM4    [4]

0x23d8b5 MOV	0x38(%RSP),%RAX    [6]

0x23d8ba VFMADD213PD	%YMM16,%YMM28,%YMM28

0x23d8c0 VMOVSD	(%R12,%RAX,8),%XMM10    [4]

0x23d8c6 MOV	0x50(%RSP),%RAX    [6]

0x23d8cb VMOVHPD	(%R12,%RAX,8),%XMM10,%XMM14    [4]

0x23d8d1 MOV	0xd0(%RSP),%RAX    [6]

0x23d8d9 VPADDQ	%YMM18,%YMM29,%YMM10

0x23d8df VINSERTF32X4	$0x1,%XMM3,%YMM11,%YMM29

0x23d8e6 VMOVDQA64	0x180(%RSP),%YMM18    [6]

0x23d8ee VEXTRACTI128	$0x1,%YMM10,%XMM9

0x23d8f4 VMOVQ	%XMM10,0x28(%RSP)    [6]

0x23d8fa VPEXTRQ	$0x1,%XMM10,0x20(%RSP)    [6]

0x23d902 VMOVHPD	(%R14,%RDI,8),%XMM15,%XMM10    [5]

0x23d908 VMOVSD	(%R12,%RSI,8),%XMM15    [4]

0x23d90e VMOVQ	%XMM9,0x38(%RSP)    [6]

0x23d914 VPEXTRQ	$0x1,%XMM9,0x18(%RSP)    [6]

0x23d91c VMOVSD	(%R12,%R10,8),%XMM9    [4]

0x23d922 VMOVHPD	(%R12,%RDX,8),%XMM15,%XMM3    [4]

0x23d928 VFMADD213PD	%YMM31,%YMM29,%YMM29

0x23d92e VMOVHPD	(%R12,%RAX,8),%XMM4,%XMM4    [4]

0x23d934 VPEXTRQ	$0x1,%XMM8,%RAX

0x23d93a VMOVSD	(%R14,%R15,8),%XMM8    [5]

0x23d940 VMOVHPD	(%R12,%RAX,8),%XMM9,%XMM9    [4]

0x23d946 VMOVHPD	(%R14,%R13,8),%XMM8,%XMM8    [5]

0x23d94c VINSERTF32X4	$0x1,%XMM4,%YMM14,%YMM17

0x23d953 VMOVDQA	0x1a0(%RSP),%YMM14    [6]

0x23d95c VINSERTF32X4	$0x1,%XMM9,%YMM3,%YMM30

0x23d963 VMOVDQA	0x1c0(%RSP),%YMM9    [6]

0x23d96c VINSERTF32X4	$0x1,%XMM10,%YMM8,%YMM31

0x23d973 VFMADD231PD	%YMM17,%YMM17,%YMM29

0x23d979 VFMADD231PD	%YMM30,%YMM30,%YMM28

0x23d97f VFMADD213PD	%YMM29,%YMM31,%YMM31

0x23d985 VPMULLQ	%YMM27,%YMM14,%YMM11

0x23d98b VPMULLQ	%YMM24,%YMM14,%YMM14

0x23d991 VPMULLQ	%YMM27,%YMM9,%YMM3

0x23d997 VPMULLQ	%YMM24,%YMM9,%YMM9

0x23d99d VPADDQ	%YMM26,%YMM11,%YMM11

0x23d9a3 VPADDQ	%YMM26,%YMM3,%YMM3

0x23d9a9 VPADDQ	%YMM25,%YMM9,%YMM9

0x23d9af VPEXTRQ	$0x1,%XMM11,0x50(%RSP)    [6]

0x23d9b7 VMOVQ	%XMM3,%R15

0x23d9bc VPEXTRQ	$0x1,%XMM3,%RDX

0x23d9c2 VEXTRACTI128	$0x1,%YMM3,%XMM3

0x23d9c8 VMOVQ	%XMM9,%RDI

0x23d9cd VPEXTRQ	$0x1,%XMM9,%R13

0x23d9d3 VMOVQ	%XMM3,%R10

0x23d9d8 VMOVSD	(%RBX,%R15,8),%XMM4    [7]

0x23d9de VPEXTRQ	$0x1,%XMM3,%RSI

0x23d9e4 VEXTRACTI128	$0x1,%YMM9,%XMM3

0x23d9ea VMOVSD	(%RBX,%R10,8),%XMM9    [7]

0x23d9f0 VMOVHPD	(%RBX,%RDX,8),%XMM4,%XMM4    [7]

0x23d9f5 VMOVQ	%XMM3,%RAX

0x23d9fa VPEXTRQ	$0x1,%XMM3,%R10

0x23da00 VMOVQ	%XMM11,%RDX

0x23da05 VMOVHPD	(%RBX,%RSI,8),%XMM9,%XMM3    [7]

0x23da0a VMOVSD	(%RBX,%RDI,8),%XMM9    [7]

0x23da0f VMOVHPD	(%RBX,%R13,8),%XMM9,%XMM15    [7]

0x23da15 VEXTRACTI128	$0x1,%YMM11,%XMM9

0x23da1b VMOVQ	%XMM9,%RSI

0x23da20 VPEXTRQ	$0x1,%XMM9,%RDI

0x23da26 VPADDQ	%YMM25,%YMM14,%YMM9

0x23da2c VMOVSD	(%R8,%RDX,8),%XMM14    [1]

0x23da32 MOV	0x50(%RSP),%RDX    [6]

0x23da37 VMOVQ	%XMM9,%R15

0x23da3c VPEXTRQ	$0x1,%XMM9,%R13

0x23da42 VEXTRACTI128	$0x1,%YMM9,%XMM9

0x23da48 VMOVHPD	(%R8,%RDX,8),%XMM14,%XMM14    [1]

0x23da4e VINSERTF128	$0x1,%XMM3,%YMM4,%YMM3

0x23da54 VMOVSD	(%RBX,%RAX,8),%XMM4    [7]

0x23da59 MOV	0x38(%RSP),%RAX    [6]

0x23da5e VMOVHPD	(%RBX,%R10,8),%XMM4,%XMM4    [7]

0x23da64 VMOVQ	%XMM9,%R10

0x23da69 VADDPD	%YMM0,%YMM3,%YMM0

0x23da6d VMOVSD	(%R12,%RAX,8),%XMM11    [4]

0x23da73 VPEXTRQ	$0x1,%XMM9,%RAX

0x23da79 VMOVSD	(%R8,%RSI,8),%XMM9    [1]

0x23da7f MOV	0x18(%RSP),%RSI    [6]

0x23da84 VMOVHPD	(%R8,%RDI,8),%XMM9,%XMM9    [1]

0x23da8a VINSERTF32X4	$0x1,%XMM4,%YMM15,%YMM16

0x23da91 VMOVSD	(%R8,%R15,8),%XMM4    [1]

0x23da97 VMOVDQA	0x160(%RSP),%YMM15    [6]

0x23daa0 VMOVHPD	(%R8,%R13,8),%XMM4,%XMM4    [1]

0x23daa6 VMOVHPD	(%R12,%RSI,8),%XMM11,%XMM10    [4]

0x23daac VADDPD	%YMM7,%YMM16,%YMM7

0x23dab2 VINSERTF128	$0x1,%XMM9,%YMM14,%YMM9

0x23dab8 VMOVSD	(%R8,%R10,8),%XMM14    [1]

0x23dabe VMOVHPD	(%R8,%RAX,8),%XMM14,%XMM14    [1]

0x23dac4 MOV	0x28(%RSP),%RAX    [6]

0x23dac9 VPMULLQ	%YMM27,%YMM15,%YMM8

0x23dacf VPADDQ	%YMM26,%YMM8,%YMM8

0x23dad5 VPEXTRQ	$0x1,%XMM8,%RDX

0x23dadb VINSERTF128	$0x1,%XMM14,%YMM4,%YMM4

0x23dae1 VMOVSD	(%R12,%RAX,8),%XMM14    [4]

0x23dae7 MOV	0x20(%RSP),%RAX    [6]

0x23daec VMULPD	%YMM16,%YMM4,%YMM4

0x23daf2 VMOVHPD	(%R12,%RAX,8),%XMM14,%XMM14    [4]

0x23daf8 VMOVQ	%XMM8,%RAX

0x23dafd VEXTRACTI128	$0x1,%YMM8,%XMM8

0x23db03 VADDPD	%YMM4,%YMM13,%YMM13

0x23db07 VMOVQ	%XMM8,%RSI

0x23db0c VMOVSD	(%R9,%RAX,8),%XMM11    [2]

0x23db12 VPEXTRQ	$0x1,%XMM8,%RDI

0x23db18 VMOVSD	(%R9,%RSI,8),%XMM8    [2]

0x23db1e VMOVHPD	(%R9,%RDX,8),%XMM11,%XMM11    [2]

0x23db24 VMOVHPD	(%R9,%RDI,8),%XMM8,%XMM8    [2]

0x23db2a VINSERTF128	$0x1,%XMM10,%YMM14,%YMM10

0x23db30 VMOVAPD	0x140(%RSP),%YMM14    [6]

0x23db39 VFMADD231PD	%YMM10,%YMM10,%YMM31

0x23db3f VINSERTF128	$0x1,%XMM8,%YMM11,%YMM8

0x23db45 VFMADD231PD	%YMM8,%YMM3,%YMM22

0x23db4b VMULPD	%YMM3,%YMM9,%YMM8

0x23db4f VPMULLQ	%YMM27,%YMM18,%YMM3

0x23db55 VPADDQ	%YMM26,%YMM3,%YMM3

0x23db5b VADDPD	%YMM12,%YMM8,%YMM12

0x23db60 VMOVQ	%XMM3,%RAX

0x23db65 VPEXTRQ	$0x1,%XMM3,%RDX

0x23db6b VEXTRACTI128	$0x1,%YMM3,%XMM3

0x23db71 VMOVQ	%XMM3,%RSI

0x23db76 VMOVSD	(%R11,%RAX,8),%XMM9    [3]

0x23db7c VPEXTRQ	$0x1,%XMM3,%RDI

0x23db82 VMOVSD	(%R11,%RSI,8),%XMM3    [3]

0x23db88 VMOVHPD	(%R11,%RDX,8),%XMM9,%XMM9    [3]

0x23db8e VMOVHPD	(%R11,%RDI,8),%XMM3,%XMM3    [3]

0x23db94 VINSERTF128	$0x1,%XMM3,%YMM9,%YMM3

0x23db9a VFMADD231PD	%YMM3,%YMM8,%YMM19

0x23dba0 VMULPD	%YMM14,%YMM28,%YMM3

0x23dba6 VFMADD231PD	%YMM3,%YMM8,%YMM20

0x23dbac VPMULLQ	%YMM24,%YMM18,%YMM3

0x23dbb2 VPADDQ	%YMM25,%YMM3,%YMM3

0x23dbb8 VMOVQ	%XMM3,%RDX

0x23dbbd VPEXTRQ	$0x1,%XMM3,%RAX

0x23dbc3 VEXTRACTI128	$0x1,%YMM3,%XMM3

0x23dbc9 VMOVQ	%XMM3,%RSI

0x23dbce VMOVSD	(%R11,%RDX,8),%XMM8    [3]

0x23dbd4 VPEXTRQ	$0x1,%XMM3,%RDI

0x23dbda VMOVSD	(%R11,%RSI,8),%XMM3    [3]

0x23dbe0 VMOVHPD	(%R11,%RAX,8),%XMM8,%XMM8    [3]

0x23dbe6 VMOVHPD	(%R11,%RDI,8),%XMM3,%XMM3    [3]

0x23dbec VINSERTF128	$0x1,%XMM3,%YMM8,%YMM3

0x23dbf2 VPMULLQ	%YMM24,%YMM15,%YMM8

0x23dbf8 VPADDQ	%YMM25,%YMM8,%YMM8

0x23dbfe VMOVQ	%XMM8,%RAX

0x23dc03 VPEXTRQ	$0x1,%XMM8,%RDX

0x23dc09 VEXTRACTI128	$0x1,%YMM8,%XMM8

0x23dc0f VMOVQ	%XMM8,%RSI

0x23dc14 VMOVSD	(%R9,%RAX,8),%XMM9    [2]

0x23dc1a VPEXTRQ	$0x1,%XMM8,%RDI

0x23dc20 MOV	0x94(%RSP),%EAX    [6]

0x23dc27 VMOVSD	(%R9,%RSI,8),%XMM8    [2]

0x23dc2d VMOVHPD	(%R9,%RDX,8),%XMM9,%XMM9    [2]

0x23dc33 VMOVHPD	(%R9,%RDI,8),%XMM8,%XMM8    [2]

0x23dc39 ADD	$-0x8,%EAX

0x23dc3c VINSERTF128	$0x1,%XMM8,%YMM9,%YMM8

0x23dc42 VMULPD	%YMM14,%YMM31,%YMM9

0x23dc48 VFMADD231PD	%YMM8,%YMM16,%YMM23

0x23dc4e VMOVAPD	0x1e0(%RSP),%YMM8    [6]

0x23dc57 VFMADD231PD	%YMM9,%YMM4,%YMM21

0x23dc5d VFMADD231PD	%YMM3,%YMM4,%YMM8

0x23dc62 JNE	23d330

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp: 76 - 91

--------------------------------------------------------------------------------

76:     for (int idx = (0); idx < ((ymax - ymin + 1) * (xmax - xmin + 1)); idx++) {

77:       const int j = xmin + 1 + idx % (xmax - xmin + 1);

78:       const int k = ymin + 1 + idx / (xmax - xmin + 1);

79:       double vsqrd = 0.0;

80:       for (int kv = k; kv <= k + 1; ++kv) {

81:         for (int jv = j; jv <= j + 1; ++jv) {

82:           vsqrd += 0.25 * (field.xvel0(jv, kv) * field.xvel0(jv, kv) + field.yvel0(jv, kv) * field.yvel0(jv, kv));

83:         }

84:       }

85:       double cell_vol = field.volume(j, k);

86:       double cell_mass = cell_vol * field.density0(j, k);

87:       vol += cell_vol;

88:       mass += cell_mass;

89:       ie += cell_mass * field.energy0(j, k);

90:       ke += cell_mass * 0.5 * vsqrd;

91:       press += cell_vol * field.pressure(j, k);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	3.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P10, P11, P12, P13,
Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source	context.h:69-69,field_summary.cpp:76-91
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	low
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	62.75
CQA cycles if no scalar integer	62.75
CQA cycles if FP arith vectorized	58.50
CQA cycles if fully vectorized	16.34
Front-end cycles	59.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.00
P3 cycles	16.00
P4 cycles	0.67
P5 cycles	0.33
P6 cycles	37.25
P7 cycles	37.25
P8 cycles	37.25
P9 cycles	37.25
P10 cycles	62.75
P11 cycles	62.75
P12 cycles	62.75
P13 cycles	62.75
P14 cycles	56.50
P15 cycles	56.50
DIV/SQRT cycles	48.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	409.00
Nb uops	475.00
Nb loads	129.00
Nb stores	22.00
Nb stack references	18.00
FLOP/cycle	3.19
Nb FLOP add-sub	16.00
Nb FLOP mul	24.00
Nb FLOP fma	80.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.06
Bytes prefetched	0.00
Bytes loaded	1188.00
Bytes stored	196.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	6.00
Vectorization ratio all	38.52
Vectorization ratio load	9.43
Vectorization ratio store	4.55
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	32.92
Vector-efficiency ratio all	22.05
Vector-efficiency ratio load	15.09
Vector-efficiency ratio store	13.92
Vector-efficiency ratio mul	47.92
Vector-efficiency ratio add_sub	45.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	15.53

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.07
CQA speedup if fully vectorized	3.84
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.06
Bottlenecks	P10, P11, P12, P13,
Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source	context.h:69-69,field_summary.cpp:76-91
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	low
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	62.75
CQA cycles if no scalar integer	62.75
CQA cycles if FP arith vectorized	58.50
CQA cycles if fully vectorized	16.34
Front-end cycles	59.38
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.00
P3 cycles	16.00
P4 cycles	0.67
P5 cycles	0.33
P6 cycles	37.25
P7 cycles	37.25
P8 cycles	37.25
P9 cycles	37.25
P10 cycles	62.75
P11 cycles	62.75
P12 cycles	62.75
P13 cycles	62.75
P14 cycles	56.50
P15 cycles	56.50
DIV/SQRT cycles	48.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	409.00
Nb uops	475.00
Nb loads	129.00
Nb stores	22.00
Nb stack references	18.00
FLOP/cycle	3.19
Nb FLOP add-sub	16.00
Nb FLOP mul	24.00
Nb FLOP fma	80.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.06
Bytes prefetched	0.00
Bytes loaded	1188.00
Bytes stored	196.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	6.00
Vectorization ratio all	38.52
Vectorization ratio load	9.43
Vectorization ratio store	4.55
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	0.00
Vectorization ratio other	32.92
Vector-efficiency ratio all	22.05
Vector-efficiency ratio load	15.09
Vector-efficiency ratio store	13.92
Vector-efficiency ratio mul	47.92
Vector-efficiency ratio add_sub	45.00
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	6.25
Vector-efficiency ratio other	15.53

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source file and lines	field_summary.cpp:76-91
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76-91

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions).

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

9% of SSE/AVX loads are used in vector version.
4% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
32% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 62.75 to 59.38 cycles (1.06x speedup).

Workaround

Reduce the number of FP add instructions
Reduce the number of FP multiply/FMA instructions

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 80 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
VPEXTRD: 12 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
VPEXTRQ: 48 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
VPINSRD: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 24 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 11 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:85
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:86
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:91
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:89
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
VINSERTF32X4: 13 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

30 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 200 FP arithmetical operations:

96: addition or subtraction (80 inside FMA instructions)
104: multiply (80 inside FMA instructions)

The binary loop is loading 1188 bytes (148 double precision FP elements). The binary loop is storing 196 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	409
nb uops	475
loop length	2360
used x86 registers	14
used mmx registers	0
used xmm registers	14
used ymm registers	30
used zmm registers	0
nb stack references	18
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	59.38 cycles
front end	59.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	2.00	16.00	0.67	0.33	37.25	37.25	37.25	37.25	62.75	62.75	62.75	62.75	56.50	56.50
cycles	0.50	0.50	2.00	16.00	0.67	0.33	37.25	37.25	37.25	37.25	62.75	62.75	62.75	62.75	56.50	56.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	48.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	59.38
Dispatch	62.75
DIV/SQRT	48.00
Data deps.	4.00
Overall L1	62.75

Vectorization ratios

INT

all	39%
load	100%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	37%
load	2%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	38%
load	9%
store	4%
mul	100%
add-sub	100%
fma	100%
div/sqrt	0%
other	32%

Vector efficiency ratios

INT

all	21%
load	37%
store	12%
mul	47%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	22%
load	13%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	22%
load	15%
store	13%
mul	47%
add-sub	45%
fma	50%
div/sqrt	6%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 62.75 cycles. At this rate:

7% of peak load performance is reached (18.93 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 23d330

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV %EAX,0x94(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VPEXTRD $0x1,%XMM1,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPEXTRD $0x1,%XMM2,%ESI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VMOVAPD %YMM8,0x1e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVD %XMM2,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
VMOVD %XMM2,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
VPCMPEQD %YMM14,%YMM14,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
CLTD																				scal (6.3%)
IDIV %ESI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVD %XMM1,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
CLTD																				scal (6.3%)
IDIV %EDI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VPEXTRD $0x2,%XMM1,%EDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPEXTRD $0x2,%XMM2,%EDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VMOVD %EAX,%XMM3	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5	1	scal (6.3%)
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CLTD																				scal (6.3%)
IDIV %EDI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VPINSRD $0x1,%ESI,%XMM3,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
VPEXTRD $0x3,%XMM2,%ESI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPADDD 0x110(%RSP),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPEXTRD $0x3,%XMM1,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPINSRD $0x2,%EDI,%XMM3,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
VPEXTRD $0x1,%XMM2,%EDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
CLTD																				scal (6.3%)
IDIV %ESI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPEXTRD $0x1,%XMM4,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPINSRD $0x3,%ESI,%XMM3,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
VPEXTRD $0x2,%XMM2,%ESI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
CLTD																				scal (6.3%)
VPMULLD %XMM2,%XMM3,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
IDIV %EDI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VPSUBD %XMM9,%XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVD %XMM4,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
CLTD																				scal (6.3%)
IDIV %R10D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VPEXTRD $0x2,%XMM4,%EDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VMOVD %EAX,%XMM8	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5	1	scal (6.3%)
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CLTD																				scal (6.3%)
IDIV %ESI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VPINSRD $0x1,%EDI,%XMM8,%XMM8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
VPEXTRD $0x3,%XMM2,%EDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPEXTRD $0x3,%XMM4,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPINSRD $0x2,%ESI,%XMM8,%XMM8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
CLTD																				scal (6.3%)
IDIV %EDI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VMOVDQA 0x120(%RSP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPADDD 0x100(%RSP),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
VPADDD %XMM3,%XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM3,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPINSRD $0x3,%EAX,%XMM8,%XMM8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
VPMULLD %XMM2,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VPADDD %XMM8,%XMM11,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM8,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBD %XMM10,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVDQA 0x130(%RSP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPMULLQ %YMM24,%YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDD %XMM9,%XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM4,%XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMULLQ %YMM24,%YMM5,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM27,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXDQ %XMM9,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMULLQ %YMM27,%YMM5,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXDQ %XMM3,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPADDQ %YMM25,%YMM10,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM25,%YMM16,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSUBQ %YMM14,%YMM25,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSUBQ %YMM14,%YMM26,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM26,%YMM9,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM8,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,0x18(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM17,0x38(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM17,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPADDQ %YMM16,%YMM29,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM3,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM8,0x28(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM3,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R14,%RDX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%R15	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDI,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R14,%R15,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM17,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM8,0x20(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%R15,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM3,%YMM11,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPADDQ %YMM26,%YMM4,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM4,%YMM30,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM11,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM11,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R12,%R13,8),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM11,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%RDI,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULPD %YMM3,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
MOV 0x28(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R12,%RAX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R12,%R10,8),%XMM28,%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPEXTRQ $0x1,%XMM16,0x18(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R12,%RDX,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R14,%RAX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM8,%YMM28,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R12,%RSI,8),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213PD %YMM3,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPADDQ %YMM9,%YMM30,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM10,%YMM29,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVSD (%R12,%RDI,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R15	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R12,%RDI,8),%XMM28,%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM3,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVHPD (%R14,%R13,8),%XMM17,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R14,%RAX,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM3,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,0x28(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDX,8),%XMM17,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM4,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RSI,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R14,%R13,8),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R14,%RAX,8),%XMM31,%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R12,%RSI,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM16,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM9,%YMM11,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R12,%RDI,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM3,%YMM17,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R14,%R10,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMULPD %YMM11,%YMM11,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVHPD (%R14,%R15,8),%XMM17,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM4,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM16,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVHPD (%R12,%R10,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R12,%RAX,8),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R12,%R15,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213PD %YMM8,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPSUBQ %YMM14,%YMM27,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVHPD (%R12,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPMULLQ %YMM5,%YMM8,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM6,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM31,%YMM17,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R12,%RDX,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R12,%RSI,8),%XMM17,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VINSERTF32X4 $0x1,%XMM10,%YMM28,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPSUBQ %YMM14,%YMM24,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMULLQ %YMM5,%YMM28,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM6,%YMM28,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM9,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPADDQ %YMM26,%YMM15,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VFMADD213PD %YMM11,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVHPD (%R12,%RDX,8),%XMM16,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPADDQ %YMM25,%YMM10,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM10,%YMM29,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM9,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,0x28(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R14,%R13,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM10,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,0x20(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R14,%R10,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x18(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD213PD %YMM4,%YMM31,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM17,%YMM16,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R14,%RAX,8),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDI,8),%XMM16,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VFMADD231PD %YMM9,%YMM9,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM14,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPADDQ %YMM26,%YMM8,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM8,%YMM30,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM14,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM14,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPADDQ %YMM25,%YMM18,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VFMADD213PD %YMM3,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%R14,%R15,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM10,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM14,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM14,0x50(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM10,0x18(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM14,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM14,0xd0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R12,%RAX,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R12,%RDX,8),%XMM14,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R12,%RSI,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R12,%RDI,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R14,%RSI,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM11,%YMM14,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPADDQ %YMM15,%YMM30,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM11,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM11,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%R10,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD231PD %YMM17,%YMM17,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%R14,%RSI,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x18(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R14,%R10,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM10,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R14,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R14,%RDX,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R14,%R10,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM4,%YMM10,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R12,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD213PD %YMM16,%YMM28,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%R12,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R12,%RAX,8),%XMM10,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPADDQ %YMM18,%YMM29,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VINSERTF32X4 $0x1,%XMM3,%YMM11,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVDQA64 0x180(%RSP),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VEXTRACTI128 $0x1,%YMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM10,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM10,0x20(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R14,%RDI,8),%XMM15,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R12,%RSI,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM9,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,0x18(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R12,%R10,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R12,%RDX,8),%XMM15,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VFMADD213PD %YMM31,%YMM29,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVHPD (%R12,%RAX,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%R15,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R12,%RAX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R14,%R13,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM4,%YMM14,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVDQA 0x1a0(%RSP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM9,%YMM3,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVDQA 0x1c0(%RSP),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM10,%YMM8,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VFMADD231PD %YMM17,%YMM17,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM30,%YMM30,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM29,%YMM31,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM27,%YMM14,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM24,%YMM14,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM27,%YMM9,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM24,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM26,%YMM11,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM26,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM25,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPEXTRQ $0x1,%XMM11,0x50(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM3,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM9,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM3,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RBX,%R15,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RBX,%R10,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RDX,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RSI,8),%XMM9,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%RBX,%RDI,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%R13,8),%XMM9,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPADDQ %YMM25,%YMM14,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVSD (%R8,%RDX,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVHPD (%R8,%RDX,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM3,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%RBX,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%RBX,%R10,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDPD %YMM0,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVSD (%R12,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R8,%RSI,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RDI,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM4,%YMM15,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R8,%R15,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x160(%RSP),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVHPD (%R8,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R12,%RSI,8),%XMM11,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VADDPD %YMM7,%YMM16,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM9,%YMM14,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R8,%R10,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R8,%RAX,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPMULLQ %YMM27,%YMM15,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM26,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPEXTRQ $0x1,%XMM8,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM14,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R12,%RAX,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULPD %YMM16,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVHPD (%R12,%RAX,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %YMM4,%YMM13,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVQ %XMM8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R9,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R9,%RSI,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9,%RDX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R9,%RDI,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM10,%YMM14,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD 0x140(%RSP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM10,%YMM10,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM8,%YMM11,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VFMADD231PD %YMM8,%YMM3,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM3,%YMM9,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM27,%YMM18,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM26,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VADDPD %YMM12,%YMM8,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM3,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R11,%RAX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%RSI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM3,%YMM9,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VFMADD231PD %YMM3,%YMM8,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM28,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM3,%YMM8,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM24,%YMM18,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM25,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM3,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM3,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R11,%RDX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%RSI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RAX,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM3,%YMM8,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPMULLQ %YMM24,%YMM15,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM25,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R9,%RAX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
MOV 0x94(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R9,%RSI,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9,%RDX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R9,%RDI,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
ADD $-0x8,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VINSERTF128 $0x1,%XMM8,%YMM9,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMULPD %YMM14,%YMM31,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM16,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x1e0(%RSP),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM4,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM3,%YMM4,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
JNE 23d330 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Function	field_summary(global_variables&, parallel_&) [clone .omp_outlined]
Source file and lines	field_summary.cpp:76-91
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76-91

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 22% of vector register length is used (average across all SSE/AVX instructions).

Details

38% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

9% of SSE/AVX loads are used in vector version.
4% of SSE/AVX stores are used in vector version.
0% of SSE/AVX divide and square root instructions are used in vector version.
32% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

execution of FP add operations (the FP add unit is a bottleneck)
execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 62.75 to 59.38 cycles (1.06x speedup).

Workaround

Reduce the number of FP add instructions
Reduce the number of FP multiply/FMA instructions

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

FMA

Detected 80 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
VPEXTRD: 12 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
VPEXTRQ: 48 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
VPINSRD: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 6 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 24 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 11 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:85
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:86
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:91
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:89
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
VINSERTF32X4: 13 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:82
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:76
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CLTD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/field_summary.cpp:78

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

30 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 200 FP arithmetical operations:

96: addition or subtraction (80 inside FMA instructions)
104: multiply (80 inside FMA instructions)

The binary loop is loading 1188 bytes (148 double precision FP elements). The binary loop is storing 196 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.14 FP operations per loaded or stored byte.

General properties

nb instructions	409
nb uops	475
loop length	2360
used x86 registers	14
used mmx registers	0
used xmm registers	14
used ymm registers	30
used zmm registers	0
nb stack references	18
ADD-SUB / MUL ratio	0.67

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	59.38 cycles
front end	59.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	2.00	16.00	0.67	0.33	37.25	37.25	37.25	37.25	62.75	62.75	62.75	62.75	56.50	56.50
cycles	0.50	0.50	2.00	16.00	0.67	0.33	37.25	37.25	37.25	37.25	62.75	62.75	62.75	62.75	56.50	56.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	48.00
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	59.38
Dispatch	62.75
DIV/SQRT	48.00
Data deps.	4.00
Overall L1	62.75

Vectorization ratios

INT

all	39%
load	100%
store	0%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	20%

all	37%
load	2%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	38%
load	9%
store	4%
mul	100%
add-sub	100%
fma	100%
div/sqrt	0%
other	32%

Vector efficiency ratios

INT

all	21%
load	37%
store	12%
mul	47%
add-sub	44%
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	22%
load	13%
store	50%
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	22%
load	15%
store	13%
mul	47%
add-sub	45%
fma	50%
div/sqrt	6%
other	15%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 62.75 cycles. At this rate:

7% of peak load performance is reached (18.93 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.12 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 23d330

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
MOV %EAX,0x94(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
VPEXTRD $0x1,%XMM1,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPEXTRD $0x1,%XMM2,%ESI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VMOVAPD %YMM8,0x1e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVD %XMM2,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
VMOVD %XMM2,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
VPCMPEQD %YMM14,%YMM14,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
CLTD																				scal (6.3%)
IDIV %ESI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVD %XMM1,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
CLTD																				scal (6.3%)
IDIV %EDI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VPEXTRD $0x2,%XMM1,%EDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPEXTRD $0x2,%XMM2,%EDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VMOVD %EAX,%XMM3	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5	1	scal (6.3%)
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CLTD																				scal (6.3%)
IDIV %EDI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VPINSRD $0x1,%ESI,%XMM3,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
VPEXTRD $0x3,%XMM2,%ESI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPADDD 0x110(%RSP),%XMM1,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPEXTRD $0x3,%XMM1,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPINSRD $0x2,%EDI,%XMM3,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
VPEXTRD $0x1,%XMM2,%EDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
CLTD																				scal (6.3%)
IDIV %ESI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPEXTRD $0x1,%XMM4,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPINSRD $0x3,%ESI,%XMM3,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
VPEXTRD $0x2,%XMM2,%ESI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
CLTD																				scal (6.3%)
VPMULLD %XMM2,%XMM3,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
IDIV %EDI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VPSUBD %XMM9,%XMM1,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
MOV %EAX,%EDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVD %XMM4,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	5	0.50	scal (6.3%)
CLTD																				scal (6.3%)
IDIV %R10D	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VPEXTRD $0x2,%XMM4,%EDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VMOVD %EAX,%XMM8	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	5	1	scal (6.3%)
MOV %EDX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
CLTD																				scal (6.3%)
IDIV %ESI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VPINSRD $0x1,%EDI,%XMM8,%XMM8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
VPEXTRD $0x3,%XMM2,%EDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
MOV %EAX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPEXTRD $0x3,%XMM4,%EAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (6.3%)
VPINSRD $0x2,%ESI,%XMM8,%XMM8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
CLTD																				scal (6.3%)
IDIV %EDI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-14	6	scal (6.3%)
VMOVDQA 0x120(%RSP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPADDD 0x100(%RSP),%XMM1,%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
VPADDD %XMM3,%XMM11,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM3,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPINSRD $0x3,%EAX,%XMM8,%XMM8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	1	scal (6.3%)
VPMULLD %XMM2,%XMM8,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (25.0%)
VPADDD %XMM8,%XMM11,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM8,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBD %XMM10,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVDQA 0x130(%RSP),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPMULLQ %YMM24,%YMM6,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDD %XMM9,%XMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM4,%XMM10,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMULLQ %YMM24,%YMM5,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM27,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXDQ %XMM9,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMULLQ %YMM27,%YMM5,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXDQ %XMM3,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPADDQ %YMM25,%YMM10,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM25,%YMM16,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSUBQ %YMM14,%YMM25,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPSUBQ %YMM14,%YMM26,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM26,%YMM9,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM8,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,0x18(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM17,0x38(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM17,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPADDQ %YMM16,%YMM29,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM3,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM8,0x28(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM3,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R14,%RDX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%R15	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%R10,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDI,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x20(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R14,%R15,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM17,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM8,0x20(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%R15,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM3,%YMM11,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPADDQ %YMM26,%YMM4,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM4,%YMM30,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM11,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM11,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R12,%R13,8),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM11,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%RDI,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM8,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMULPD %YMM3,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
MOV 0x28(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R12,%RAX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R12,%R10,8),%XMM28,%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPEXTRQ $0x1,%XMM16,0x18(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R12,%RDX,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R14,%RAX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM8,%YMM28,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R12,%RSI,8),%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213PD %YMM3,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPADDQ %YMM9,%YMM30,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM10,%YMM29,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVSD (%R12,%RDI,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R15	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R12,%RDI,8),%XMM28,%XMM28	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM3,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVHPD (%R14,%R13,8),%XMM17,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R14,%RAX,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM3,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,0x28(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%RDI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDX,8),%XMM17,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM4,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RSI,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R14,%R13,8),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R14,%RAX,8),%XMM31,%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R12,%RSI,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM16,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM9,%YMM11,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R12,%RDI,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM3,%YMM17,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R14,%R10,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMULPD %YMM11,%YMM11,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVHPD (%R14,%R15,8),%XMM17,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM4,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM16,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVHPD (%R12,%R10,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R12,%RAX,8),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R12,%R15,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VFMADD213PD %YMM8,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPSUBQ %YMM14,%YMM27,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVHPD (%R12,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPMULLQ %YMM5,%YMM8,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM6,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM31,%YMM17,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R12,%RDX,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R12,%RSI,8),%XMM17,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VINSERTF32X4 $0x1,%XMM10,%YMM28,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPSUBQ %YMM14,%YMM24,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMULLQ %YMM5,%YMM28,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM6,%YMM28,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM9,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPADDQ %YMM26,%YMM15,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VFMADD213PD %YMM11,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVHPD (%R12,%RDX,8),%XMM16,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM9,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPADDQ %YMM25,%YMM10,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM10,%YMM29,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM9,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,0x28(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R14,%R13,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM10,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,0x20(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R14,%R10,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x18(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD213PD %YMM4,%YMM31,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM17,%YMM16,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R14,%RAX,8),%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDI,8),%XMM16,%XMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VFMADD231PD %YMM9,%YMM9,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM14,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPADDQ %YMM26,%YMM8,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM8,%YMM30,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM14,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM14,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM14,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM14,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPADDQ %YMM25,%YMM18,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VFMADD213PD %YMM3,%YMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%R14,%R15,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM10,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM10,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM14,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM14,0x50(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM10,0x18(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM14,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM14,0xd0(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R12,%RAX,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R12,%RDX,8),%XMM14,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R12,%RSI,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R12,%RDI,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R14,%RSI,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM11,%YMM14,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPADDQ %YMM15,%YMM30,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM11,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM11,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM11,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM11,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%R10,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x28(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD231PD %YMM17,%YMM17,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%R14,%RSI,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x18(%RSP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R14,%R10,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM10,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R14,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R14,%RDX,8),%XMM10,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R14,%R10,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM8,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM4,%YMM10,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R12,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VFMADD213PD %YMM16,%YMM28,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%R12,%RAX,8),%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R12,%RAX,8),%XMM10,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPADDQ %YMM18,%YMM29,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VINSERTF32X4 $0x1,%XMM3,%YMM11,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVDQA64 0x180(%RSP),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VEXTRACTI128 $0x1,%YMM10,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM10,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM10,0x20(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R14,%RDI,8),%XMM15,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R12,%RSI,8),%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM9,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,0x18(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R12,%R10,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R12,%RDX,8),%XMM15,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VFMADD213PD %YMM31,%YMM29,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVHPD (%R12,%RAX,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%R15,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R12,%RAX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R14,%R13,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM4,%YMM14,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVDQA 0x1a0(%RSP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM9,%YMM3,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVDQA 0x1c0(%RSP),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM10,%YMM8,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VFMADD231PD %YMM17,%YMM17,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM30,%YMM30,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM29,%YMM31,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM27,%YMM14,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM24,%YMM14,%YMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM27,%YMM9,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM24,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM26,%YMM11,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM26,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM25,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPEXTRQ $0x1,%XMM11,0x50(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM3,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM9,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM3,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RBX,%R15,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RBX,%R10,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RDX,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM11,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RSI,8),%XMM9,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%RBX,%RDI,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%R13,8),%XMM9,%XMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPADDQ %YMM25,%YMM14,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVSD (%R8,%RDX,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x50(%RSP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %XMM9,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVHPD (%R8,%RDX,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM3,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%RBX,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x38(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%RBX,%R10,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM9,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VADDPD %YMM0,%YMM3,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVSD (%R12,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R8,%RSI,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x18(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R8,%RDI,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM4,%YMM15,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R8,%R15,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDQA 0x160(%RSP),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVHPD (%R8,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R12,%RSI,8),%XMM11,%XMM10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VADDPD %YMM7,%YMM16,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM9,%YMM14,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R8,%R10,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R8,%RAX,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPMULLQ %YMM27,%YMM15,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM26,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPEXTRQ $0x1,%XMM8,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM14,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R12,%RAX,8),%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x20(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULPD %YMM16,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVHPD (%R12,%RAX,8),%XMM14,%XMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VADDPD %YMM4,%YMM13,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVQ %XMM8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R9,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R9,%RSI,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9,%RDX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R9,%RDI,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM10,%YMM14,%YMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD 0x140(%RSP),%YMM14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM10,%YMM10,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM8,%YMM11,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VFMADD231PD %YMM8,%YMM3,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM3,%YMM9,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM27,%YMM18,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM26,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VADDPD %YMM12,%YMM8,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM3,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R11,%RAX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%RSI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM3,%YMM9,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VFMADD231PD %YMM3,%YMM8,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM14,%YMM28,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM3,%YMM8,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM24,%YMM18,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM25,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM3,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM3,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R11,%RDX,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%RSI,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RAX,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R11,%RDI,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM3,%YMM8,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPMULLQ %YMM24,%YMM15,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM25,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM8,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM8,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R9,%RAX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM8,%RDI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
MOV 0x94(%RSP),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R9,%RSI,8),%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9,%RDX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R9,%RDI,8),%XMM8,%XMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
ADD $-0x8,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VINSERTF128 $0x1,%XMM8,%YMM9,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMULPD %YMM14,%YMM31,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM8,%YMM16,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x1e0(%RSP),%YMM8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM9,%YMM4,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD231PD %YMM3,%YMM4,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
JNE 23d330 <_Z13field_summaryR16global_variablesR9parallel_.omp_outlined+0x290>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code