OV - exec - Loop 160

	Loop Id: 160	Module: exec	Source: advec_mom.cpp:109-139 [...]	Coverage: 4.33%

0x2360e0 VSUBPD	%YMM19,%YMM13,%YMM4

0x2360e6 VMOVAPD	%YMM24,%YMM3{%K1}{z}

0x2360ec ADD	$-0x4,%RSI

0x2360f0 VPADDQ	%YMM0,%YMM14,%YMM0

0x2360f4 VFMADD213PD	%YMM21,%YMM3,%YMM4

0x2360fa VPMULLQ	%YMM16,%YMM7,%YMM3

0x236100 VPADDQ	%YMM3,%YMM15,%YMM3

0x236104 VMULPD	%YMM2,%YMM4,%YMM2

0x236108 VMOVQ	%XMM3,%RDX

0x23610d VPEXTRQ	$0x1,%XMM3,%RAX

0x236113 VEXTRACTI128	$0x1,%YMM3,%XMM3

0x236119 VMOVQ	%XMM3,%RBX

0x23611e VPEXTRQ	$0x1,%XMM3,%R14

0x236124 VMOVLPD	%XMM2,(%R8,%RDX,8)    [1]

0x23612a VMOVHPD	%XMM2,(%R8,%RAX,8)    [1]

0x236130 VEXTRACTF128	$0x1,%YMM2,%XMM2

0x236136 VMOVLPD	%XMM2,(%R8,%RBX,8)    [1]

0x23613c VMOVHPD	%XMM2,(%R8,%R14,8)    [1]

0x236142 JE	23647f

0x236148 VEXTRACTI128	$0x1,%YMM0,%XMM2

0x23614e VPEXTRQ	$0x1,%XMM8,%RBX

0x236154 VPEXTRQ	$0x1,%XMM2,%RAX

0x23615a CQTO

0x23615c IDIV	%RBX

0x23615f VMOVQ	%XMM8,%RBX

0x236164 VMOVQ	%RAX,%XMM15

0x236169 VMOVQ	%XMM2,%RAX

0x23616e CQTO

0x236170 IDIV	%RBX

0x236173 VPEXTRQ	$0x1,%XMM1,%RBX

0x236179 VMOVQ	%RAX,%XMM2

0x23617e VPEXTRQ	$0x1,%XMM0,%RAX

0x236184 CQTO

0x236186 VPUNPCKLQDQ	%XMM15,%XMM2,%XMM2

0x23618b IDIV	%RBX

0x23618e VMOVQ	%XMM1,%RBX

0x236193 VMOVQ	%RAX,%XMM15

0x236198 VMOVQ	%XMM0,%RAX

0x23619d CQTO

0x23619f IDIV	%RBX

0x2361a2 VMOVQ	%RAX,%XMM16

0x2361a8 VPUNPCKLQDQ	%XMM15,%XMM16,%XMM15

0x2361ae VINSERTI128	$0x1,%XMM2,%YMM15,%YMM2

0x2361b4 VPMOVQD	%YMM2,%XMM15

0x2361ba VPMULLQ	%YMM1,%YMM2,%YMM2

0x2361c0 VPSUBQ	%YMM2,%YMM0,%YMM2

0x2361c4 VPMOVQD	%YMM2,%XMM2

0x2361ca VPADDD	%XMM15,%XMM17,%XMM16

0x2361d0 VPMOVSXDQ	%XMM16,%YMM16

0x2361d6 VPMULLQ	%YMM16,%YMM5,%YMM24

0x2361dc VPADDD	%XMM2,%XMM26,%XMM19

0x2361e2 VPMULLQ	%YMM16,%YMM27,%YMM2

0x2361e8 VPMOVSXDQ	%XMM19,%YMM15

0x2361ee VPSUBD	%XMM10,%XMM19,%XMM20

0x2361f4 VPMOVSXDQ	%XMM20,%YMM23

0x2361fa VPADDQ	%YMM2,%YMM15,%YMM2

0x2361fe VMOVQ	%XMM2,%RAX

0x236203 VPEXTRQ	$0x1,%XMM2,%RDX

0x236209 VEXTRACTI128	$0x1,%YMM2,%XMM2

0x23620f VMOVQ	%XMM2,%RBX

0x236214 VMOVSD	(%RDI,%RAX,8),%XMM18    [3]

0x23621b VPEXTRQ	$0x1,%XMM2,%R14

0x236221 VMOVSD	(%RDI,%RBX,8),%XMM2    [3]

0x236226 VMOVHPD	(%RDI,%RDX,8),%XMM18,%XMM18    [3]

0x23622d VMOVHPD	(%RDI,%R14,8),%XMM2,%XMM2    [3]

0x236233 VINSERTF32X4	$0x1,%XMM2,%YMM18,%YMM2

0x23623a VPADDD	%XMM10,%XMM19,%XMM18

0x236240 VMOVDQA64	%XMM18,%XMM22

0x236246 VCMPPD	$0x1,%YMM9,%YMM2,%K1

0x23624d VPBLENDMQ	%YMM23,%YMM15,%YMM21{%K1}

0x236253 VPADDD	-0x33659(%RIP){1to4},%XMM19,%XMM22{%K1}    [7]

0x23625d VANDPD	%YMM11,%YMM2,%YMM19

0x236263 VMOVDQA64	%YMM15,%YMM23{%K1}

0x236269 VPADDQ	%YMM24,%YMM21,%YMM24

0x23626f VMOVQ	%XMM24,%RDX

0x236275 VPEXTRQ	$0x1,%XMM24,%RAX

0x23627c VEXTRACTI32X4	$0x1,%YMM24,%XMM24

0x236283 VMOVQ	%XMM24,%RBX

0x236289 VMOVSD	(%R9,%RDX,8),%XMM25    [2]

0x236290 VPEXTRQ	$0x1,%XMM24,%R14

0x236297 VMOVSD	(%R9,%RBX,8),%XMM24    [2]

0x23629e VMOVHPD	(%R9,%RAX,8),%XMM25,%XMM25    [2]

0x2362a5 VMOVHPD	(%R9,%R14,8),%XMM24,%XMM24    [2]

0x2362ac VPMOVSXDQ	%XMM22,%YMM22

0x2362b2 VINSERTF32X4	$0x1,%XMM24,%YMM25,%YMM24

0x2362b9 VDIVPD	%YMM24,%YMM19,%YMM19

0x2362bf VPMULLQ	%YMM16,%YMM6,%YMM24

0x2362c5 VPADDQ	%YMM24,%YMM21,%YMM21

0x2362cb VPADDQ	%YMM22,%YMM24,%YMM22

0x2362d1 VPADDQ	%YMM24,%YMM23,%YMM23

0x2362d7 VMOVQ	%XMM21,%RAX

0x2362dd VPEXTRQ	$0x1,%XMM21,%RDX

0x2362e4 VEXTRACTI32X4	$0x1,%YMM21,%XMM21

0x2362eb VMOVQ	%XMM21,%RBX

0x2362f1 VMOVSD	(%R11,%RAX,8),%XMM25    [5]

0x2362f8 VPEXTRQ	$0x1,%XMM21,%R14

0x2362ff VMOVQ	%XMM22,%RAX

0x236305 VMOVSD	(%R11,%RBX,8),%XMM21    [5]

0x23630c VMOVHPD	(%R11,%RDX,8),%XMM25,%XMM25    [5]

0x236313 VPEXTRQ	$0x1,%XMM22,%RDX

0x23631a VEXTRACTI32X4	$0x1,%YMM22,%XMM22

0x236321 VMOVHPD	(%R11,%R14,8),%XMM21,%XMM21    [5]

0x236328 VMOVQ	%XMM22,%RBX

0x23632e VPEXTRQ	$0x1,%XMM22,%R14

0x236335 VMOVSD	(%R11,%RBX,8),%XMM22    [5]

0x23633c VMOVHPD	(%R11,%R14,8),%XMM22,%XMM22    [5]

0x236343 VINSERTF32X4	$0x1,%XMM21,%YMM25,%YMM21

0x23634a VMOVSD	(%R11,%RAX,8),%XMM25    [5]

0x236351 VMOVQ	%XMM23,%RAX

0x236357 VMOVHPD	(%R11,%RDX,8),%XMM25,%XMM25    [5]

0x23635e VPEXTRQ	$0x1,%XMM23,%RDX

0x236365 VEXTRACTI32X4	$0x1,%YMM23,%XMM23

0x23636c VMOVSD	(%R11,%RAX,8),%XMM24    [5]

0x236373 VMOVQ	%XMM23,%RBX

0x236379 VPEXTRQ	$0x1,%XMM23,%R14

0x236380 VMOVHPD	(%R11,%RDX,8),%XMM24,%XMM24    [5]

0x236387 VMOVSD	(%R11,%RBX,8),%XMM23    [5]

0x23638e VMOVHPD	(%R11,%R14,8),%XMM23,%XMM23    [5]

0x236395 VINSERTF32X4	$0x1,%XMM22,%YMM25,%YMM22

0x23639c VSUBPD	%YMM22,%YMM21,%YMM22

0x2363a2 VINSERTF32X4	$0x1,%XMM23,%YMM24,%YMM23

0x2363a9 VSUBPD	%YMM21,%YMM23,%YMM23

0x2363af VMULPD	%YMM22,%YMM23,%YMM3

0x2363b5 VCMPPD	$0x1,%YMM3,%YMM9,%K0

0x2363bc VCMPPD	$0x1,%YMM3,%YMM9,%YMM3

0x2363c1 VANDPD	%YMM3,%YMM12,%YMM3

0x2363c5 KORTESTB	%K0,%K0

0x2363c9 VPCMPEQQ	%YMM12,%YMM3,%K1

0x2363cf JE	2360e0

0x2363d5 VCMPPD	$0x1,%YMM9,%YMM2,%YMM3

0x2363db MOV	-0x50(%RBP),%RAX    [6]

0x2363df VXORPD	%XMM4,%XMM4,%XMM4

0x2363e3 KMOVQ	%K1,%K3

0x2363e8 VANDPD	%YMM3,%YMM12,%YMM3

0x2363ec VPCMPEQQ	%YMM12,%YMM3,%K2

0x2363f2 VXORPD	%XMM3,%XMM3,%XMM3

0x2363f6 VMOVDQA32	%XMM20,%XMM18{%K2}

0x2363fc KMOVQ	%K1,%K2

0x236401 VANDPD	%YMM11,%YMM22,%YMM20

0x236407 VANDPD	%YMM11,%YMM23,%YMM22

0x23640d VGATHERQPD	(%RAX,%YMM15,8),%YMM3{%K2}    [4]

0x236414 VCMPPD	$0x1,%YMM23,%YMM9,%K2

0x23641b VBROADCASTSD	-0x2531d(%RIP),%YMM23    [7]

0x236425 VGATHERDPD	(%RAX,%XMM18,8),%YMM4{%K3}    [4]

0x23642c VSUBPD	%YMM19,%YMM23,%YMM23

0x236432 VMULPD	%YMM23,%YMM22,%YMM23

0x236438 VMINPD	%YMM22,%YMM20,%YMM22

0x23643e VFMADD213PD	%YMM20,%YMM19,%YMM20

0x236444 VDIVPD	%YMM3,%YMM23,%YMM23

0x23644a VMULPD	-0x2526c(%RIP){1to4},%YMM3,%YMM3    [7]

0x236454 VDIVPD	%YMM4,%YMM20,%YMM4

0x23645a VADDPD	%YMM23,%YMM4,%YMM4

0x236460 VMULPD	%YMM4,%YMM3,%YMM3

0x236464 VMINPD	%YMM22,%YMM3,%YMM3

0x23646a VXORPD	-0x252fc(%RIP){1to4},%YMM3,%YMM24    [7]

0x236474 VMOVAPD	%YMM3,%YMM24{%K2}

0x23647a JMP	2360e0

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp: 109 - 139

--------------------------------------------------------------------------------

109:     for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

110:       for (int i = (x_min - 1 + 1); i < (x_max + 1 + 2); i++)

111:         ({

112:           int upwind, donor, downwind, dif;

113:           double sigma, width, limiter, vdiffuw, vdiffdw, auw, adw, wind, advec_vel_s;

114:           if (node_flux(i, j) < 0.0) {

[...]

125:           sigma = std::fabs(node_flux(i, j)) / (node_mass_pre(donor, j));

126:           width = celldx[i];

127:           vdiffuw = vel1(donor, j) - vel1(upwind, j);

128:           vdiffdw = vel1(downwind, j) - vel1(donor, j);

129:           limiter = 0.0;

130:           if (vdiffuw * vdiffdw > 0.0) {

131:             auw = std::fabs(vdiffuw);

132:             adw = std::fabs(vdiffdw);

133:             wind = 1.0;

134:             if (vdiffdw <= 0.0) wind = -1.0;

135:             limiter =

136:                 wind * std::fmin(std::fmin(width * ((2.0 - sigma) * adw / width + (1.0 + sigma) * auw / celldx[dif]) / 6.0, auw), adw);

137:           }

138:           advec_vel_s = vel1(donor, j) + (1.0 - sigma) * limiter;

139:           mom_flux(i, j) = advec_vel_s * node_flux(i, j);

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.51 - 2.35
CQA speedup if FP arith vectorized	1.08
CQA speedup if fully vectorized	4.79 - 5.60
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.48 - 2.30
Bottlenecks
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.12]
Source	context.h:69-69,advec_mom.cpp:109-114,advec_mom.cpp:125-139
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	36.00 - 56.00
CQA cycles if no scalar integer	23.88
CQA cycles if FP arith vectorized	32.00 - 52.00
CQA cycles if fully vectorized	7.52 - 10.00
Front-end cycles	23.13
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.00
P3 cycles	8.00
P4 cycles	1.33
P5 cycles	1.17
P6 cycles	7.75
P7 cycles	7.75
P8 cycles	7.75
P9 cycles	7.75
P10 cycles	24.38
P11 cycles	24.38
P12 cycles	24.38
P13 cycles	24.38
P14 cycles	21.50
P15 cycles	21.50
DIV/SQRT cycles	36.00 - 56.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	143.00
Nb uops	185.00
Nb loads	28.00
Nb stores	4.00
Nb stack references	0.50
FLOP/cycle	1.39 - 0.89
Nb FLOP add-sub	16.00
Nb FLOP mul	14.00
Nb FLOP fma	6.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.32 - 6.71
Bytes prefetched	0.00
Bytes loaded	212.00
Bytes stored	32.00
Stride 0	1.50
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.50
Vectorization ratio all	48.17
Vectorization ratio load	12.00
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	31.43
Vectorization ratio other	46.40
Vector-efficiency ratio all	25.90
Vector-efficiency ratio load	15.92
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	42.62
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	24.29
Vector-efficiency ratio other	23.48

Metric	Value
CQA speedup if no scalar integer	1.47 - 2.20
CQA speedup if FP arith vectorized	1.11
CQA speedup if fully vectorized	4.21 - 5.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.43 - 2.14
Bottlenecks	P10, P11,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.12]
Source	context.h:69-69,advec_mom.cpp:109-114,advec_mom.cpp:125-139
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	40.00 - 60.00
CQA cycles if no scalar integer	27.25
CQA cycles if FP arith vectorized	34.00 - 54.00
CQA cycles if fully vectorized	9.50 - 12.00
Front-end cycles	27.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.00
P3 cycles	8.00
P4 cycles	1.67
P5 cycles	1.33
P6 cycles	9.25
P7 cycles	9.25
P8 cycles	9.25
P9 cycles	9.25
P10 cycles	28.00
P11 cycles	28.00
P12 cycles	28.00
P13 cycles	28.00
P14 cycles	24.50
P15 cycles	24.50
DIV/SQRT cycles	40.00 - 60.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	157.00
Nb uops	222.00
Nb loads	31.00
Nb stores	4.00
Nb stack references	1.00
FLOP/cycle	1.70 - 1.13
Nb FLOP add-sub	20.00
Nb FLOP mul	20.00
Nb FLOP fma	8.00
Nb FLOP div	12.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.87 - 7.30
Bytes prefetched	0.00
Bytes loaded	260.00
Bytes stored	32.00
Stride 0	2.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	5.00
Vectorization ratio all	52.35
Vectorization ratio load	19.23
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	42.86
Vectorization ratio other	51.14
Vector-efficiency ratio all	27.60
Vector-efficiency ratio load	18.75
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	43.06
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	28.57
Vector-efficiency ratio other	25.43

Metric	Value
CQA speedup if no scalar integer	1.56 - 2.54
CQA speedup if FP arith vectorized	1.04
CQA speedup if fully vectorized	5.79 - 6.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.54 - 2.51
Bottlenecks	P10, P11,
Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.12]
Source	context.h:69-69,advec_mom.cpp:109-114,advec_mom.cpp:125-139
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	4
CQA cycles	32.00 - 52.00
CQA cycles if no scalar integer	20.50
CQA cycles if FP arith vectorized	30.00 - 50.00
CQA cycles if fully vectorized	5.53 - 8.00
Front-end cycles	18.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	4.00
P3 cycles	8.00
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	6.25
P7 cycles	6.25
P8 cycles	6.25
P9 cycles	6.25
P10 cycles	20.75
P11 cycles	20.75
P12 cycles	20.75
P13 cycles	20.75
P14 cycles	18.50
P15 cycles	18.50
DIV/SQRT cycles	32.00 - 52.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	129.00
Nb uops	148.00
Nb loads	25.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	1.00 - 0.62
Nb FLOP add-sub	12.00
Nb FLOP mul	8.00
Nb FLOP fma	4.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.77 - 6.13
Bytes prefetched	0.00
Bytes loaded	164.00
Bytes stored	32.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	4.00
Vectorization ratio all	44.00
Vectorization ratio load	4.76
Vectorization ratio store	0.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	20.00
Vectorization ratio other	41.67
Vector-efficiency ratio all	24.20
Vector-efficiency ratio load	13.10
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	42.19
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	20.00
Vector-efficiency ratio other	21.53

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.12]
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-114,125-139

It is main loop of related source loop which is unrolled by 4 (including vectorization).
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is poorly vectorized. Only 25% of vector register length is used (average across all SSE/AVX instructions).

Details

48% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

11% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
31% of SSE/AVX divide and square root instructions are used in vector version.
46% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 56.00 to 25.38 cycles (2.21x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 0 occurrences
KORTESTB: 0 occurrences
VGATHERDPD: 0 occurrences
VGATHERQPD: 0 occurrences
VMOVHPD: 0 occurrences
VPEXTRQ: 0 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 0 occurrences
VGATHERQPD: 0 occurrences

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 0 occurrences
VPMOVQD: 0 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

16 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 50 FP arithmetical operations:

22: addition or subtraction (6 inside FMA instructions)
20: multiply (6 inside FMA instructions)
8: divide

The binary loop is loading 212 bytes (26 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.20 FP operations per loaded or stored byte.

General properties

nb instructions	143
nb uops	185
loop length	842
used x86 registers	9.50
used mmx registers	0
used xmm registers	18.50
used ymm registers	23.50
used zmm registers	0
nb stack references	0.50
ADD-SUB / MUL ratio	1.25

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	23.13 cycles
front end	23.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	4.00	8.00	1.33	1.17	7.75	7.75	7.75	7.75	24.38	24.38	24.38	24.38	21.50	21.50
cycles	0.50	0.50	4.00	8.00	1.33	1.17	7.75	7.75	7.75	7.75	24.38	24.38	24.38	24.38	21.50	21.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	36.00-56.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	23.13
Dispatch	24.38
DIV/SQRT	36.00-56.00
Data deps.	1.00
Overall L1	36.00-56.00

Vectorization ratios

INT

all	44%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	29%

all	52%
load	8%
store	0%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	98%

INT+FP

all	48%
load	11%
store	0%
mul	100%
add-sub	100%
fma	100%
div/sqrt	31%
other	46%

Vector efficiency ratios

INT

all	23%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	29%
load	15%
store	12%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	39%

INT+FP

all	25%
load	15%
store	12%
mul	50%
add-sub	42%
fma	50%
div/sqrt	24%
other	23%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 56.00 cycles. At this rate:

1% of peak load performance is reached (3.74 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.57 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.12]
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-114,125-139

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 60.00 to 27.25 cycles (2.20x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 27% of vector register length is used (average across all SSE/AVX instructions).

Details

52% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

19% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
42% of SSE/AVX divide and square root instructions are used in vector version.
51% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 60.00 to 28.00 cycles (2.14x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 60.00 to 29.00 cycles (2.07x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
KORTESTB: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:130
VGATHERDPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:136
VGATHERQPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:126
VMOVHPD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:139
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:139
VPEXTRQ: 16 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:139
VINSERTF32X4: 5 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VGATHERDPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:136
VGATHERQPD: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:126

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
VPMOVQD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

22 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 68 FP arithmetical operations:

28: addition or subtraction (8 inside FMA instructions)
28: multiply (8 inside FMA instructions)
12: divide

The binary loop is loading 260 bytes (32 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.23 FP operations per loaded or stored byte.

General properties

nb instructions	157
nb uops	222
loop length	927
used x86 registers	10
used mmx registers	0
used xmm registers	19
used ymm registers	24
used zmm registers	0
nb stack references	1
ADD-SUB / MUL ratio	1.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	27.75 cycles
front end	27.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	4.00	8.00	1.67	1.33	9.25	9.25	9.25	9.25	28.00	28.00	28.00	28.00	24.50	24.50
cycles	0.50	0.50	4.00	8.00	1.67	1.33	9.25	9.25	9.25	9.25	28.00	28.00	28.00	28.00	24.50	24.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	40.00-60.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	27.75
Dispatch	28.00
DIV/SQRT	40.00-60.00
Data deps.	1.00
Overall L1	40.00-60.00

Vectorization ratios

INT

all	45%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	61%
load	16%
store	0%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	96%

INT+FP

all	52%
load	19%
store	0%
mul	100%
add-sub	100%
fma	100%
div/sqrt	42%
other	51%

Vector efficiency ratios

INT

all	23%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	32%
load	18%
store	12%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	40%

INT+FP

all	27%
load	18%
store	12%
mul	50%
add-sub	43%
fma	50%
div/sqrt	28%
other	25%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 60.00 cycles. At this rate:

1% of peak load performance is reached (4.33 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 236148

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VSUBPD %YMM19,%YMM13,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVAPD %YMM24,%YMM3{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
ADD $-0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPADDQ %YMM0,%YMM14,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VFMADD213PD %YMM21,%YMM3,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM16,%YMM7,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM3,%YMM15,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM2,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVQ %XMM3,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM3,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVLPD %XMM2,(%R8,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R8,%RAX,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVLPD %XMM2,(%R8,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R8,%R14,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
JE 23647f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x52f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VEXTRACTI128 $0x1,%YMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM8,%RBX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %XMM8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %RAX,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM2,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VPEXTRQ $0x1,%XMM1,%RBX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %RAX,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPEXTRQ $0x1,%XMM0,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
CQTO																				scal (12.5%)
VPUNPCKLQDQ %XMM15,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
IDIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %XMM1,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %RAX,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM0,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %RAX,%XMM16	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPUNPCKLQDQ %XMM15,%XMM16,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VINSERTI128 $0x1,%XMM2,%YMM15,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPMOVQD %YMM2,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM1,%YMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPSUBQ %YMM2,%YMM0,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMOVQD %YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPADDD %XMM15,%XMM17,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMULLQ %YMM16,%YMM5,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDD %XMM2,%XMM26,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMULLQ %YMM16,%YMM27,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXDQ %XMM19,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBD %XMM10,%XMM19,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM20,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPADDQ %YMM2,%YMM15,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM2,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM2,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RDI,%RBX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RDI,%RDX,8),%XMM18,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RDI,%R14,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM2,%YMM18,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPADDD %XMM10,%XMM19,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVDQA64 %XMM18,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPPD $0x1,%YMM9,%YMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPBLENDMQ %YMM23,%YMM15,%YMM21{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDD -0x33659(%RIP){1to4},%XMM19,%XMM22{%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
VANDPD %YMM11,%YMM2,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQA64 %YMM15,%YMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPADDQ %YMM24,%YMM21,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM24,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM24,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM24,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R9,%RDX,8),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM24,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R9,%RBX,8),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9,%RAX,8),%XMM25,%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R9,%R14,8),%XMM24,%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPMOVSXDQ %XMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VDIVPD %YMM24,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VPMULLQ %YMM16,%YMM6,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM24,%YMM21,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM22,%YMM24,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM24,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM21,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM21,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM21,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R11,%RAX,8),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM21,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM22,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R11,%RBX,8),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM22,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM22,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVHPD (%R11,%R14,8),%XMM21,%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM22,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM22,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%RBX,8),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R14,8),%XMM22,%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM21,%YMM25,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%RAX,8),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM23,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM23,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R11,%RAX,8),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM23,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM23,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R11,%RDX,8),%XMM24,%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R11,%RBX,8),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R14,8),%XMM23,%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM22,%YMM25,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM22,%YMM21,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM23,%YMM24,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM21,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM22,%YMM23,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM3,%YMM9,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM3,%YMM9,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VANDPD %YMM3,%YMM12,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
VPCMPEQQ %YMM12,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
JE 2360e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x190>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VCMPPD $0x1,%YMM9,%YMM2,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV -0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD %XMM4,%XMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K3	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VANDPD %YMM3,%YMM12,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPEQQ %YMM12,%YMM3,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA32 %XMM20,%XMM18{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
KMOVQ %K1,%K2	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
VANDPD %YMM11,%YMM22,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM11,%YMM23,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VGATHERQPD (%RAX,%YMM15,8),%YMM3{%K2}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VCMPPD $0x1,%YMM23,%YMM9,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD -0x2531d(%RIP),%YMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VGATHERDPD (%RAX,%XMM18,8),%YMM4{%K3}	24	0	0	0	0	0	0	1	1	1	1	1.25	1.25	1.25	1.25	3	3	0-16	4	vect (50.0%)
VSUBPD %YMM19,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM23,%YMM22,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM22,%YMM20,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VFMADD213PD %YMM20,%YMM19,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VDIVPD %YMM3,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMULPD -0x2526c(%RIP){1to4},%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM4,%YMM20,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VADDPD %YMM23,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM4,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM22,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VXORPD -0x252fc(%RIP){1to4},%YMM3,%YMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VMOVAPD %YMM3,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
JMP 2360e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x190>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	advec_mom_kernel(int, int, int, int, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer1D&, clover::Buffer1D&, int, int, int) [clone .omp_outlined.12]
Source file and lines	advec_mom.cpp:109-139
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109-114,125-139

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 52.00 to 20.50 cycles (2.54x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 24% of vector register length is used (average across all SSE/AVX instructions).

Details

44% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

4% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
20% of SSE/AVX divide and square root instructions are used in vector version.
41% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 52.00 to 21.75 cycles (2.39x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 4 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
KORTESTB: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:130
VMOVHPD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:139
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:139
VPEXTRQ: 16 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 4 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 6 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:139
VINSERTF32X4: 5 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
VPMOVQD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:109
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_mom.cpp:110

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

10 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 32 FP arithmetical operations:

16: addition or subtraction (4 inside FMA instructions)
12: multiply (4 inside FMA instructions)
4: divide

The binary loop is loading 164 bytes (20 double precision FP elements). The binary loop is storing 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.16 FP operations per loaded or stored byte.

General properties

nb instructions	129
nb uops	148
loop length	757
used x86 registers	9
used mmx registers	0
used xmm registers	18
used ymm registers	23
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	1.50

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	18.50 cycles
front end	18.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	4.00	8.00	1.00	1.00	6.25	6.25	6.25	6.25	20.75	20.75	20.75	20.75	18.50	18.50
cycles	0.50	0.50	4.00	8.00	1.00	1.00	6.25	6.25	6.25	6.25	20.75	20.75	20.75	20.75	18.50	18.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions	32.00-52.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	18.50
Dispatch	20.75
DIV/SQRT	32.00-52.00
Data deps.	1.00
Overall L1	32.00-52.00

Vectorization ratios

INT

all	43%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	28%

all	44%
load	0%
store	0%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	44%
load	4%
store	0%
mul	100%
add-sub	100%
fma	100%
div/sqrt	20%
other	41%

Vector efficiency ratios

INT

all	23%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	40%
fma	NA (no fma vectorizable/vectorized instructions)
other	17%

all	25%
load	12%
store	12%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	37%

INT+FP

all	24%
load	13%
store	12%
mul	50%
add-sub	42%
fma	50%
div/sqrt	20%
other	21%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 52.00 cycles. At this rate:

1% of peak load performance is reached (3.15 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.62 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 236148

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VSUBPD %YMM19,%YMM13,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVAPD %YMM24,%YMM3{%K1}{z}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
ADD $-0x4,%RSI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPADDQ %YMM0,%YMM14,%YMM0	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VFMADD213PD %YMM21,%YMM3,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM16,%YMM7,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM3,%YMM15,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMULPD %YMM2,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVQ %XMM3,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM3,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVLPD %XMM2,(%R8,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R8,%RAX,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVLPD %XMM2,(%R8,%RBX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R8,%R14,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
JE 23647f <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x52f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VEXTRACTI128 $0x1,%YMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM8,%RBX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %XMM8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %RAX,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM2,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VPEXTRQ $0x1,%XMM1,%RBX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %RAX,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPEXTRQ $0x1,%XMM0,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
CQTO																				scal (12.5%)
VPUNPCKLQDQ %XMM15,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
IDIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %XMM1,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %RAX,%XMM15	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM0,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RBX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %RAX,%XMM16	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPUNPCKLQDQ %XMM15,%XMM16,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VINSERTI128 $0x1,%XMM2,%YMM15,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPMOVQD %YMM2,%XMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM1,%YMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPSUBQ %YMM2,%YMM0,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMOVQD %YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPADDD %XMM15,%XMM17,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM16,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMULLQ %YMM16,%YMM5,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDD %XMM2,%XMM26,%XMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMULLQ %YMM16,%YMM27,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXDQ %XMM19,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBD %XMM10,%XMM19,%XMM20	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM20,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPADDQ %YMM2,%YMM15,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM2,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM2,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RDI,%RBX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RDI,%RDX,8),%XMM18,%XMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RDI,%R14,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM2,%YMM18,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPADDD %XMM10,%XMM19,%XMM18	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVDQA64 %XMM18,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VCMPPD $0x1,%YMM9,%YMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPBLENDMQ %YMM23,%YMM15,%YMM21{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDD -0x33659(%RIP){1to4},%XMM19,%XMM22{%K1}	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (25.0%)
VANDPD %YMM11,%YMM2,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQA64 %YMM15,%YMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPADDQ %YMM24,%YMM21,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM24,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM24,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM24,%XMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM24,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R9,%RDX,8),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM24,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R9,%RBX,8),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R9,%RAX,8),%XMM25,%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R9,%R14,8),%XMM24,%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPMOVSXDQ %XMM22,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VINSERTF32X4 $0x1,%XMM24,%YMM25,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VDIVPD %YMM24,%YMM19,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VPMULLQ %YMM16,%YMM6,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM24,%YMM21,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM22,%YMM24,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM24,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM21,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM21,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM21,%XMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM21,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R11,%RAX,8),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM21,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM22,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R11,%RBX,8),%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM22,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM22,%XMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVHPD (%R11,%R14,8),%XMM21,%XMM21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM22,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM22,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R11,%RBX,8),%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R14,8),%XMM22,%XMM22	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM21,%YMM25,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%RAX,8),%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM23,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RDX,8),%XMM25,%XMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM23,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM23,%XMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R11,%RAX,8),%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM23,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM23,%R14	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R11,%RDX,8),%XMM24,%XMM24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R11,%RBX,8),%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R14,8),%XMM23,%XMM23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM22,%YMM25,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM22,%YMM21,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM23,%YMM24,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM21,%YMM23,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM22,%YMM23,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM3,%YMM9,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM3,%YMM9,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VANDPD %YMM3,%YMM12,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
VPCMPEQQ %YMM12,%YMM3,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
JE 2360e0 <_Z16advec_mom_kerneliiiiRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_S2_RNS_8Buffer1DIdEES5_iii.omp_outlined.12+0x190>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A

Report Configuration

Vectorization

Details

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks