OV - exec - Loop 144

	Loop Id: 144	Module: exec	Source: advec_cell.cpp:158-202 [...]	Coverage: 3.50%

0x232350 VCMPPD	$0x1,%YMM4,%YMM14,%YMM4

0x232355 VCMPPD	$0x1,%YMM6,%YMM14,%YMM6

0x23235a VPADDQ	0x1c0(%RSP),%YMM0,%YMM0    [8]

0x232363 VANDPD	%YMM4,%YMM15,%YMM4

0x232367 VANDPD	%YMM6,%YMM15,%YMM6

0x23236b VPCMPEQQ	%YMM15,%YMM4,%K2

0x232371 VPCMPEQQ	%YMM15,%YMM6,%K1

0x232377 VADDPD	%YMM9,%YMM3,%YMM3{%K2}

0x23237d VADDPD	%YMM7,%YMM2,%YMM2{%K1}

0x232383 VMULPD	%YMM5,%YMM3,%YMM3

0x232387 VMOVDQA	0x220(%RSP),%YMM5    [8]

0x232390 VMULPD	%YMM2,%YMM12,%YMM2

0x232394 VPMULLQ	%YMM21,%YMM5,%YMM4

0x23239a VPMULLQ	%YMM22,%YMM5,%YMM5

0x2323a0 VPADDQ	%YMM19,%YMM4,%YMM4

0x2323a6 VPADDQ	%YMM20,%YMM5,%YMM5

0x2323ac VMOVQ	%XMM4,%RCX

0x2323b1 VPEXTRQ	$0x1,%XMM4,%RAX

0x2323b7 VEXTRACTI128	$0x1,%YMM4,%XMM4

0x2323bd VMOVQ	%XMM5,%R8

0x2323c2 VPEXTRQ	$0x1,%XMM5,%R9

0x2323c8 VMOVLPD	%XMM2,(%R12,%RCX,8)    [3]

0x2323ce MOV	0x120(%RSP),%RCX    [8]

0x2323d6 VMOVHPD	%XMM2,(%R12,%RAX,8)    [3]

0x2323dc VEXTRACTF128	$0x1,%YMM2,%XMM2

0x2323e2 VMOVQ	%XMM4,%RDX

0x2323e7 VPEXTRQ	$0x1,%XMM4,%RSI

0x2323ed VEXTRACTI128	$0x1,%YMM5,%XMM4

0x2323f3 VMOVQ	%XMM4,%R10

0x2323f8 VPEXTRQ	$0x1,%XMM4,%R13

0x2323fe VMOVLPD	%XMM2,(%R12,%RDX,8)    [3]

0x232404 VMOVHPD	%XMM2,(%R12,%RSI,8)    [3]

0x23240a VEXTRACTF128	$0x1,%YMM3,%XMM2

0x232410 VMOVLPD	%XMM3,(%R12,%R8,8)    [3]

0x232416 VMOVHPD	%XMM3,(%R12,%R9,8)    [3]

0x23241c VMOVLPD	%XMM2,(%R12,%R10,8)    [3]

0x232422 VMOVHPD	%XMM2,(%R12,%R13,8)    [3]

0x232428 ADD	$-0x8,%RCX

0x23242c JE	23309a

0x232432 VMOVDQA	0x140(%RSP),%XMM5    [8]

0x23243b VEXTRACTI128	$0x1,%YMM0,%XMM2

0x232441 MOV	%RCX,0x120(%RSP)    [8]

0x232449 VPADDQ	0x200(%RSP),%YMM0,%YMM3    [8]

0x232452 VPEXTRQ	$0x1,%XMM1,%R9

0x232458 VPEXTRQ	$0x1,%XMM2,%RAX

0x23245e CQTO

0x232460 VPEXTRQ	$0x1,%XMM5,%RCX

0x232466 VMOVQ	%XMM5,%RSI

0x23246b IDIV	%RCX

0x23246e VMOVQ	%RAX,%XMM4

0x232473 VMOVQ	%XMM2,%RAX

0x232478 CQTO

0x23247a IDIV	%RSI

0x23247d VMOVQ	%RAX,%XMM2

0x232482 VPEXTRQ	$0x1,%XMM0,%RAX

0x232488 CQTO

0x23248a VPUNPCKLQDQ	%XMM4,%XMM2,%XMM2

0x23248e IDIV	%R9

0x232491 VMOVQ	%XMM1,%R9

0x232496 VMOVQ	%RAX,%XMM4

0x23249b VMOVQ	%XMM0,%RAX

0x2324a0 CQTO

0x2324a2 IDIV	%R9

0x2324a5 VMOVQ	%RAX,%XMM5

0x2324aa VPUNPCKLQDQ	%XMM4,%XMM5,%XMM4

0x2324ae VEXTRACTI128	$0x1,%YMM3,%XMM5

0x2324b4 VPEXTRQ	$0x1,%XMM5,%RAX

0x2324ba VINSERTI128	$0x1,%XMM2,%YMM4,%YMM4

0x2324c0 CQTO

0x2324c2 IDIV	%RCX

0x2324c5 VPEXTRQ	$0x1,%XMM1,%RCX

0x2324cb VMOVQ	%RAX,%XMM2

0x2324d0 VMOVQ	%XMM5,%RAX

0x2324d5 CQTO

0x2324d7 IDIV	%RSI

0x2324da VMOVQ	%RAX,%XMM5

0x2324df VPEXTRQ	$0x1,%XMM3,%RAX

0x2324e5 CQTO

0x2324e7 VPUNPCKLQDQ	%XMM2,%XMM5,%XMM2

0x2324eb IDIV	%RCX

0x2324ee VMOVQ	%XMM1,%RCX

0x2324f3 MOV	%RAX,%RSI

0x2324f6 VMOVQ	%XMM3,%RAX

0x2324fb VMOVQ	%RSI,%XMM5

0x232500 CQTO

0x232502 IDIV	%RCX

0x232505 VMOVDQA	0x170(%RSP),%XMM9    [8]

0x23250e MOV	0x68(%RSP),%R15    [8]

0x232513 VMOVQ	%RAX,%XMM6

0x232518 VPUNPCKLQDQ	%XMM5,%XMM6,%XMM5

0x23251c VPMOVQD	%YMM4,%XMM6

0x232522 VPMULLQ	%YMM1,%YMM4,%YMM4

0x232528 VINSERTI128	$0x1,%XMM2,%YMM5,%YMM5

0x23252e VPMOVQD	%YMM5,%XMM7

0x232534 VPMULLQ	%YMM1,%YMM5,%YMM5

0x23253a VPSUBQ	%YMM4,%YMM0,%YMM4

0x23253e VPADDD	%XMM6,%XMM9,%XMM2

0x232542 VPMOVQD	%YMM4,%XMM4

0x232548 VPSUBQ	%YMM5,%YMM3,%YMM3

0x23254c VPMOVSXDQ	%XMM2,%YMM21

0x232552 VPMOVQD	%YMM3,%XMM5

0x232558 VPADDD	%XMM7,%XMM9,%XMM3

0x23255c VMOVDQA	0x160(%RSP),%XMM9    [8]

0x232565 VPMOVSXDQ	%XMM3,%YMM22

0x23256b VPADDD	%XMM5,%XMM9,%XMM5

0x23256f VPADDD	%XMM4,%XMM9,%XMM4

0x232573 VMOVDQA	0x150(%RSP),%XMM9    [8]

0x23257c VPMOVSXDQ	%XMM5,%YMM20

0x232582 VMOVDQA	0x280(%RSP),%YMM5    [8]

0x23258b VPMOVSXDQ	%XMM4,%YMM19

0x232591 VPMULLQ	%YMM21,%YMM5,%YMM4

0x232597 VPMULLQ	%YMM22,%YMM5,%YMM5

0x23259d VPADDQ	%YMM19,%YMM4,%YMM4

0x2325a3 VPADDQ	%YMM20,%YMM5,%YMM5

0x2325a9 VMOVQ	%XMM4,%RAX

0x2325ae VPEXTRQ	$0x1,%XMM4,%RCX

0x2325b4 VEXTRACTI128	$0x1,%YMM4,%XMM4

0x2325ba VMOVQ	%XMM5,%R9

0x2325bf VPEXTRQ	$0x1,%XMM5,%R10

0x2325c5 VMOVQ	%XMM4,%RDX

0x2325ca VPEXTRQ	$0x1,%XMM4,%RSI

0x2325d0 VEXTRACTI128	$0x1,%YMM5,%XMM4

0x2325d6 VMOVSD	(%R15,%RAX,8),%XMM5    [7]

0x2325dc VPEXTRQ	$0x1,%XMM4,%R13

0x2325e2 VMOVQ	%XMM4,%R8

0x2325e7 VMOVSD	(%R15,%RDX,8),%XMM4    [7]

0x2325ed VMOVHPD	(%R15,%RCX,8),%XMM5,%XMM5    [7]

0x2325f3 VMOVHPD	(%R15,%RSI,8),%XMM4,%XMM4    [7]

0x2325f9 VINSERTF128	$0x1,%XMM4,%YMM5,%YMM12

0x2325ff VMOVSD	(%R15,%R8,8),%XMM4    [7]

0x232605 VMOVSD	(%R15,%R9,8),%XMM5    [7]

0x23260b VMOVHPD	(%R15,%R13,8),%XMM4,%XMM4    [7]

0x232611 VMOVHPD	(%R15,%R10,8),%XMM5,%XMM5    [7]

0x232617 VCMPPD	$0x1,%YMM12,%YMM14,%K0

0x23261e VINSERTF128	$0x1,%XMM4,%YMM5,%YMM5

0x232624 VPADDD	%XMM6,%XMM9,%XMM4

0x232628 VPADDD	%XMM7,%XMM9,%XMM6

0x23262c VCMPPD	$0x1,%YMM5,%YMM14,%K1

0x232633 KSHIFTLB	$0x4,%K1,%K1

0x232639 KORB	%K1,%K0,%K0

0x23263d KORTESTB	%K0,%K0

0x232641 JB	23267d

0x232643 VMOVDQA	0x130(%RSP),%XMM11    [8]

0x23264c VPCMPEQD	%XMM9,%XMM9,%XMM9

0x232651 VPMOVSXDQ	%XMM4,%YMM23

0x232657 VPMOVSXDQ	%XMM6,%YMM24

0x23265d VPSUBD	%XMM9,%XMM2,%XMM7

0x232662 VPSUBD	%XMM9,%XMM3,%XMM9

0x232667 VPMINSD	%XMM7,%XMM11,%XMM7

0x23266c VPMINSD	%XMM9,%XMM11,%XMM9

0x232671 VPMOVSXDQ	%XMM7,%YMM26

0x232677 VPMOVSXDQ	%XMM9,%YMM25

0x23267d VCMPPD	$0x1,%YMM5,%YMM14,%YMM9

0x232682 VCMPPD	$0x1,%YMM12,%YMM14,%YMM7

0x232688 VANDPD	%YMM15,%YMM9,%YMM9

0x23268d VANDPD	%YMM7,%YMM15,%YMM7

0x232691 VPCMPEQQ	%YMM15,%YMM9,%K2

0x232697 VPCMPEQQ	%YMM15,%YMM7,%K1

0x23269d KSHIFTLB	$0x4,%K2,%K0

0x2326a3 KORB	%K0,%K1,%K0

0x2326a7 KORTESTB	%K0,%K0

0x2326ab JE	2326d2

0x2326ad VPBROADCASTD	-0x2faa2(%RIP),%XMM7    [5]

0x2326b6 VPMOVSXDQ	%XMM6,%YMM9

0x2326bb VPADDD	%XMM7,%XMM2,%XMM2

0x2326bf VPADDD	%XMM7,%XMM3,%XMM3

0x2326c3 VPMOVSXDQ	%XMM4,%YMM7

0x2326c8 VPMOVSXDQ	%XMM2,%YMM11

0x2326cd VPMOVSXDQ	%XMM3,%YMM13

0x2326d2 VMOVDQA	0x260(%RSP),%YMM6    [8]

0x2326db VPBLENDMQ	%YMM7,%YMM21,%YMM28{%K1}

0x2326e1 VPBLENDMQ	%YMM9,%YMM22,%YMM18{%K2}

0x2326e7 VANDPD	%YMM16,%YMM12,%YMM2

0x2326ed VANDPD	%YMM16,%YMM5,%YMM3

0x2326f3 VPBLENDMQ	%YMM11,%YMM26,%YMM17{%K1}

0x2326f9 VMOVDQA64	%YMM7,%YMM26{%K1}

0x2326ff VPBLENDMQ	%YMM13,%YMM25,%YMM13{%K2}

0x232705 VMOVDQA64	%YMM9,%YMM25{%K2}

0x23270b VEXTRACTI32X4	$0x1,%YMM25,%XMM9

0x232712 VMOVDQA64	%YMM21,%YMM23{%K1}

0x232718 VMOVDQA64	%YMM22,%YMM24{%K2}

0x23271e VMOVDQA64	%YMM17,0x2e0(%RSP)    [8]

0x232726 VMOVDQA	%YMM13,0x2c0(%RSP)    [8]

0x23272f VPMULLQ	%YMM6,%YMM28,%YMM4

0x232735 VPMULLQ	%YMM6,%YMM18,%YMM6

0x23273b VPADDQ	%YMM19,%YMM4,%YMM4

0x232741 VPADDQ	%YMM20,%YMM6,%YMM6

0x232747 VMOVQ	%XMM4,%RDX

0x23274c VPEXTRQ	$0x1,%XMM4,%RSI

0x232752 VEXTRACTI128	$0x1,%YMM4,%XMM4

0x232758 VMOVQ	%XMM6,%RAX

0x23275d VPEXTRQ	$0x1,%XMM6,%RCX

0x232763 VMOVQ	%XMM4,%R10

0x232768 VPEXTRQ	$0x1,%XMM4,%R15

0x23276e VEXTRACTI128	$0x1,%YMM6,%XMM4

0x232774 VMOVSD	(%R11,%RDX,8),%XMM6    [2]

0x23277a MOV	%RDX,0x108(%RSP)    [8]

0x232782 MOV	%RAX,0x118(%RSP)    [8]

0x23278a MOV	%RSI,0x100(%RSP)    [8]

0x232792 MOV	%RCX,0x110(%RSP)    [8]

0x23279a VPEXTRQ	$0x1,%XMM4,%R8

0x2327a0 VMOVQ	%XMM4,%R9

0x2327a5 VMOVSD	(%R11,%R10,8),%XMM4    [2]

0x2327ab VMOVHPD	(%R11,%RSI,8),%XMM6,%XMM6    [2]

0x2327b1 MOV	%R10,0xe8(%RSP)    [8]

0x2327b9 MOV	%R15,0xe0(%RSP)    [8]

0x2327c1 VMOVHPD	(%R11,%R15,8),%XMM4,%XMM4    [2]

0x2327c7 MOV	%R8,0xf8(%RSP)    [8]

0x2327cf MOV	%R9,0xf0(%RSP)    [8]

0x2327d7 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

0x2327dd VMOVSD	(%R11,%RAX,8),%XMM6    [2]

0x2327e3 VMOVQ	%XMM21,%RAX

0x2327e9 VMOVHPD	(%R11,%RCX,8),%XMM6,%XMM6    [2]

0x2327ef VPEXTRQ	$0x1,%XMM21,%RCX

0x2327f6 VMOVSD	(%R14,%RAX,8),%XMM7    [4]

0x2327fc VDIVPD	%YMM4,%YMM2,%YMM2

0x232800 VMOVSD	(%R11,%R9,8),%XMM4    [2]

0x232806 VMOVHPD	(%R11,%R8,8),%XMM4,%XMM4    [2]

0x23280c VMOVQ	%XMM22,%R8

0x232812 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

0x232818 VEXTRACTI32X4	$0x1,%YMM22,%XMM6

0x23281f VPEXTRQ	$0x1,%XMM6,%RAX

0x232825 VDIVPD	%YMM4,%YMM3,%YMM3

0x232829 VEXTRACTI32X4	$0x1,%YMM21,%XMM4

0x232830 VMOVQ	%XMM4,%RDX

0x232835 VPEXTRQ	$0x1,%XMM4,%RSI

0x23283b VMOVSD	(%R14,%RDX,8),%XMM4    [4]

0x232841 VPEXTRQ	$0x1,%XMM22,%RDX

0x232848 VMOVHPD	(%R14,%RSI,8),%XMM4,%XMM4    [4]

0x23284e VMOVQ	%XMM6,%RSI

0x232853 VMOVHPD	(%R14,%RCX,8),%XMM7,%XMM6    [4]

0x232859 VMOVSD	(%R14,%R8,8),%XMM7    [4]

0x23285f VPEXTRQ	$0x1,%XMM26,%RCX

0x232866 VMOVQ	%XMM25,%R8

0x23286c VMOVHPD	(%R14,%RDX,8),%XMM7,%XMM7    [4]

0x232872 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

0x232878 VMOVSD	(%R14,%RSI,8),%XMM6    [4]

0x23287e VMOVHPD	(%R14,%RAX,8),%XMM6,%XMM6    [4]

0x232884 VMOVQ	%XMM26,%RAX

0x23288a VMOVSD	(%R14,%RAX,8),%XMM11    [4]

0x232890 VPEXTRQ	$0x1,%XMM9,%RAX

0x232896 VFMADD213PD	%YMM4,%YMM2,%YMM4

0x23289b VINSERTF128	$0x1,%XMM6,%YMM7,%YMM6

0x2328a1 VEXTRACTI32X4	$0x1,%YMM26,%XMM7

0x2328a8 VMOVQ	%XMM7,%RDX

0x2328ad VPEXTRQ	$0x1,%XMM7,%RSI

0x2328b3 VMOVSD	(%R14,%RDX,8),%XMM7    [4]

0x2328b9 VPEXTRQ	$0x1,%XMM25,%RDX

0x2328c0 VFMADD213PD	%YMM6,%YMM3,%YMM6

0x2328c5 VMOVAPD	0x1e0(%RSP),%YMM25    [8]

0x2328cd VMOVHPD	(%R14,%RSI,8),%XMM7,%XMM7    [4]

0x2328d3 VMOVQ	%XMM9,%RSI

0x2328d8 VMOVHPD	(%R14,%RCX,8),%XMM11,%XMM9    [4]

0x2328de VMOVSD	(%R14,%R8,8),%XMM11    [4]

0x2328e4 VMOVHPD	(%R14,%RDX,8),%XMM11,%XMM11    [4]

0x2328ea VINSERTF128	$0x1,%XMM7,%YMM9,%YMM7

0x2328f0 VMOVSD	(%R14,%RSI,8),%XMM9    [4]

0x2328f6 VMOVHPD	(%R14,%RAX,8),%XMM9,%XMM9    [4]

0x2328fc VDIVPD	%YMM7,%YMM4,%YMM4

0x232900 VPMULLQ	%YMM8,%YMM13,%YMM7

0x232906 VPADDQ	%YMM20,%YMM7,%YMM7

0x23290c VINSERTF128	$0x1,%XMM9,%YMM11,%YMM9

0x232912 VMOVAPD	%YMM4,0x1a0(%RSP)    [8]

0x23291b VDIVPD	%YMM9,%YMM6,%YMM4

0x232920 VPMULLQ	%YMM8,%YMM18,%YMM6

0x232926 VPADDQ	%YMM20,%YMM6,%YMM29

0x23292c VPMULLQ	%YMM8,%YMM17,%YMM6

0x232932 VPMULLQ	%YMM8,%YMM24,%YMM17

0x232938 VPADDQ	%YMM19,%YMM6,%YMM6

0x23293e VPADDQ	%YMM20,%YMM17,%YMM17

0x232944 VEXTRACTI128	$0x1,%YMM6,%XMM9

0x23294a VMOVQ	%XMM6,%RAX

0x23294f VMOVQ	%XMM9,%RCX

0x232954 VMOVSD	(%RDI,%RCX,8),%XMM11    [1]

0x232959 VPEXTRQ	$0x1,%XMM9,%RCX

0x23295f VMOVHPD	(%RDI,%RCX,8),%XMM11,%XMM9    [1]

0x232964 VPEXTRQ	$0x1,%XMM6,%RCX

0x23296a VEXTRACTI128	$0x1,%YMM7,%XMM6

0x232970 VMOVSD	(%RDI,%RAX,8),%XMM11    [1]

0x232975 VMOVQ	%XMM6,%RAX

0x23297a VMOVHPD	(%RDI,%RCX,8),%XMM11,%XMM11    [1]

0x23297f VPEXTRQ	$0x1,%XMM6,%RCX

0x232985 VMOVSD	(%RDI,%RAX,8),%XMM6    [1]

0x23298a VMOVQ	%XMM7,%RAX

0x23298f VMOVAPD	%YMM4,0x180(%RSP)    [8]

0x232998 VSUBPD	%YMM2,%YMM25,%YMM4

0x23299e VMOVHPD	(%RDI,%RCX,8),%XMM6,%XMM13    [1]

0x2329a3 VEXTRACTI32X4	$0x1,%YMM29,%XMM6

0x2329aa VPEXTRQ	$0x1,%XMM6,%RCX

0x2329b0 MOV	%RCX,0xb0(%RSP)    [8]

0x2329b8 VMOVAPD	%YMM4,0x2a0(%RSP)    [8]

0x2329c1 VPMULLQ	%YMM8,%YMM28,%YMM4

0x2329c7 VPADDQ	%YMM19,%YMM4,%YMM4

0x2329cd VINSERTF128	$0x1,%XMM9,%YMM11,%YMM9

0x2329d3 VMOVQ	%XMM4,%RSI

0x2329d8 VPEXTRQ	$0x1,%XMM4,%RDX

0x2329de VEXTRACTI128	$0x1,%YMM4,%XMM4

0x2329e4 VPEXTRQ	$0x1,%XMM4,%R8

0x2329ea VMOVQ	%XMM4,%R9

0x2329ef VMOVSD	(%RDI,%RAX,8),%XMM4    [1]

0x2329f4 VPEXTRQ	$0x1,%XMM7,%RAX

0x2329fa VMOVSD	(%RDI,%RSI,8),%XMM31    [1]

0x232a01 MOV	%RSI,0xd0(%RSP)    [8]

0x232a09 MOV	%RDX,0xd8(%RSP)    [8]

0x232a11 VMOVHPD	(%RDI,%RAX,8),%XMM4,%XMM7    [1]

0x232a16 VPMULLQ	%YMM8,%YMM23,%YMM4

0x232a1c VMOVHPD	(%RDI,%RDX,8),%XMM31,%XMM31    [1]

0x232a23 MOV	%R9,0xc0(%RSP)    [8]

0x232a2b MOV	%R8,0xc8(%RSP)    [8]

0x232a33 VPADDQ	%YMM19,%YMM4,%YMM4

0x232a39 VEXTRACTI32X4	$0x1,%YMM4,%XMM26

0x232a40 VMOVQ	%XMM26,%RAX

0x232a46 VMOVSD	(%RDI,%RAX,8),%XMM27    [1]

0x232a4d VPEXTRQ	$0x1,%XMM26,%RAX

0x232a54 VMOVHPD	(%RDI,%RAX,8),%XMM27,%XMM26    [1]

0x232a5b VMOVQ	%XMM4,%RAX

0x232a60 VMOVSD	(%RDI,%RAX,8),%XMM27    [1]

0x232a67 VPEXTRQ	$0x1,%XMM4,%RAX

0x232a6d VEXTRACTI32X4	$0x1,%YMM17,%XMM4

0x232a74 VINSERTF128	$0x1,%XMM13,%YMM7,%YMM7

0x232a7a VMOVHPD	(%RDI,%RAX,8),%XMM27,%XMM27    [1]

0x232a81 VMOVQ	%XMM4,%RAX

0x232a86 VMOVSD	(%RDI,%RAX,8),%XMM30    [1]

0x232a8d VPEXTRQ	$0x1,%XMM4,%RAX

0x232a93 VMOVHPD	(%RDI,%RAX,8),%XMM30,%XMM30    [1]

0x232a9a VMOVQ	%XMM17,%RAX

0x232aa0 VMOVSD	(%RDI,%RAX,8),%XMM4    [1]

0x232aa5 VPEXTRQ	$0x1,%XMM17,%RAX

0x232aac VMOVHPD	(%RDI,%RAX,8),%XMM4,%XMM17    [1]

0x232ab3 VMOVSD	(%RDI,%R9,8),%XMM4    [1]

0x232ab9 VMOVQ	%XMM6,%RAX

0x232abe VMOVHPD	(%RDI,%R8,8),%XMM4,%XMM4    [1]

0x232ac4 VMOVSD	(%RDI,%RAX,8),%XMM6    [1]

0x232ac9 MOV	%RAX,0xb8(%RSP)    [8]

0x232ad1 VMOVQ	%XMM29,%RAX

0x232ad7 MOV	%RAX,0xa8(%RSP)    [8]

0x232adf VMOVHPD	(%RDI,%RCX,8),%XMM6,%XMM6    [1]

0x232ae4 VINSERTF32X4	$0x1,%XMM4,%YMM31,%YMM4

0x232aeb VMOVSD	(%RDI,%RAX,8),%XMM31    [1]

0x232af2 VPEXTRQ	$0x1,%XMM29,%RAX

0x232af9 VMOVHPD	(%RDI,%RAX,8),%XMM31,%XMM29    [1]

0x232b00 MOV	%RAX,0xa0(%RSP)    [8]

0x232b08 VSUBPD	%YMM9,%YMM4,%YMM13

0x232b0d VINSERTF32X4	$0x1,%XMM30,%YMM17,%YMM9

0x232b14 VINSERTF32X4	$0x1,%XMM6,%YMM29,%YMM6

0x232b1b VSUBPD	%YMM3,%YMM25,%YMM29

0x232b21 VMOVAPD	0x2a0(%RSP),%YMM25    [8]

0x232b29 VSUBPD	%YMM7,%YMM6,%YMM11

0x232b2d VINSERTF32X4	$0x1,%XMM26,%YMM27,%YMM7

0x232b34 VSUBPD	%YMM6,%YMM9,%YMM17

0x232b3a VSUBPD	%YMM4,%YMM7,%YMM26

0x232b40 VMULPD	%YMM11,%YMM17,%YMM7

0x232b46 VMULPD	%YMM13,%YMM26,%YMM9

0x232b4c VCMPPD	$0x1,%YMM7,%YMM14,%K1

0x232b53 VCMPPD	$0x1,%YMM9,%YMM14,%K0

0x232b5a KSHIFTLB	$0x4,%K1,%K1

0x232b60 KORB	%K1,%K0,%K0

0x232b64 KORTESTB	%K0,%K0

0x232b68 JE	232c1f

0x232b6e VBROADCASTSD	-0x21a28(%RIP),%YMM27    [5]

0x232b78 VCMPPD	$0x1,%YMM26,%YMM14,%K1

0x232b7f VCMPPD	$0x1,%YMM17,%YMM14,%K2

0x232b86 VSUBPD	%YMM2,%YMM27,%YMM2

0x232b8c VSUBPD	%YMM3,%YMM27,%YMM3

0x232b92 VBROADCASTSD	-0x21a24(%RIP),%YMM27    [5]

0x232b9c VXORPD	%YMM27,%YMM2,%YMM30

0x232ba2 VXORPD	%YMM27,%YMM3,%YMM31

0x232ba8 VANDPD	%YMM16,%YMM26,%YMM27

0x232bae VMOVAPD	%YMM2,%YMM30{%K1}

0x232bb4 VMOVAPD	%YMM3,%YMM31{%K2}

0x232bba VANDPD	%YMM16,%YMM13,%YMM2

0x232bc0 VANDPD	%YMM16,%YMM17,%YMM13

0x232bc6 VANDPD	%YMM16,%YMM11,%YMM3

0x232bcc VMINPD	%YMM13,%YMM3,%YMM26

0x232bd2 VMULPD	0x180(%RSP),%YMM3,%YMM3    [8]

0x232bdb VMINPD	%YMM27,%YMM2,%YMM17

0x232be1 VMULPD	0x1a0(%RSP),%YMM2,%YMM2    [8]

0x232bea VFMADD231PD	%YMM13,%YMM29,%YMM3

0x232bf0 VBROADCASTSD	-0x21a11(%RIP),%YMM13    [5]

0x232bf9 VFMADD231PD	%YMM27,%YMM25,%YMM2

0x232bff VMULPD	%YMM2,%YMM13,%YMM2

0x232c03 VMINPD	%YMM2,%YMM17,%YMM2

0x232c09 VMULPD	%YMM30,%YMM2,%YMM27

0x232c0f VMULPD	%YMM3,%YMM13,%YMM2

0x232c13 VMINPD	%YMM2,%YMM26,%YMM2

0x232c19 VMULPD	%YMM31,%YMM2,%YMM30

0x232c1f VCMPPD	$0x1,%YMM7,%YMM14,%YMM3

0x232c24 VCMPPD	$0x1,%YMM9,%YMM14,%YMM2

0x232c2a MOV	0x60(%RSP),%R15    [8]

0x232c2f VMOVAPD	0x1a0(%RSP),%YMM31    [8]

0x232c37 VANDPD	%YMM3,%YMM15,%YMM3

0x232c3b VANDPD	%YMM2,%YMM15,%YMM2

0x232c3f VPCMPEQQ	%YMM15,%YMM3,%K2

0x232c45 VMOVDQA	0x240(%RSP),%YMM3    [8]

0x232c4e VPCMPEQQ	%YMM15,%YMM2,%K1

0x232c54 VADDPD	%YMM27,%YMM4,%YMM4{%K1}

0x232c5a VADDPD	%YMM30,%YMM6,%YMM6{%K2}

0x232c60 VMULPD	%YMM4,%YMM12,%YMM12

0x232c64 VMULPD	%YMM5,%YMM6,%YMM5

0x232c68 VPMULLQ	0x2c0(%RSP),%YMM10,%YMM6    [8]

0x232c70 VPMULLQ	%YMM21,%YMM3,%YMM2

0x232c76 VPMULLQ	%YMM22,%YMM3,%YMM3

0x232c7c VPADDQ	%YMM19,%YMM2,%YMM2

0x232c82 VPADDQ	%YMM20,%YMM3,%YMM3

0x232c88 VMOVQ	%XMM2,%RCX

0x232c8d VPEXTRQ	$0x1,%XMM2,%R8

0x232c93 VEXTRACTI128	$0x1,%YMM2,%XMM2

0x232c99 VMOVQ	%XMM3,%RAX

0x232c9e VPEXTRQ	$0x1,%XMM3,%RDX

0x232ca4 VMOVQ	%XMM2,%R13

0x232ca9 VPEXTRQ	$0x1,%XMM2,%R9

0x232caf VEXTRACTI128	$0x1,%YMM3,%XMM2

0x232cb5 VMOVLPD	%XMM12,(%R15,%RCX,8)    [6]

0x232cbb VMOVHPD	%XMM12,(%R15,%R8,8)    [6]

0x232cc1 VPMULLQ	%YMM10,%YMM18,%YMM3

0x232cc7 VMOVQ	%XMM2,%RSI

0x232ccc VPEXTRQ	$0x1,%XMM2,%R10

0x232cd2 VEXTRACTF128	$0x1,%YMM12,%XMM2

0x232cd8 VPADDQ	%YMM20,%YMM6,%YMM6

0x232cde VMOVLPD	%XMM2,(%R15,%R13,8)    [6]

0x232ce4 VMOVHPD	%XMM2,(%R15,%R9,8)    [6]

0x232cea VEXTRACTF128	$0x1,%YMM5,%XMM2

0x232cf0 VMOVLPD	%XMM5,(%R15,%RAX,8)    [6]

0x232cf6 VMOVHPD	%XMM5,(%R15,%RDX,8)    [6]

0x232cfc VPADDQ	%YMM20,%YMM3,%YMM3

0x232d02 VMOVQ	%XMM3,%R8

0x232d07 VPEXTRQ	$0x1,%XMM3,%R9

0x232d0d VMOVLPD	%XMM2,(%R15,%RSI,8)    [6]

0x232d13 VMOVHPD	%XMM2,(%R15,%R10,8)    [6]

0x232d19 VPMULLQ	%YMM10,%YMM28,%YMM2

0x232d1f VMOVSD	(%RBX,%R8,8),%XMM4    [9]

0x232d25 VPEXTRQ	$0x1,%XMM6,%R8

0x232d2b VMOVHPD	(%RBX,%R9,8),%XMM4,%XMM4    [9]

0x232d31 VMOVQ	%XMM6,%R9

0x232d36 VPADDQ	%YMM19,%YMM2,%YMM2

0x232d3c VMOVSD	(%RBX,%R9,8),%XMM7    [9]

0x232d42 VMOVQ	%XMM2,%RAX

0x232d47 VPEXTRQ	$0x1,%XMM2,%RCX

0x232d4d VEXTRACTI128	$0x1,%YMM2,%XMM2

0x232d53 VMOVHPD	(%RBX,%R8,8),%XMM7,%XMM7    [9]

0x232d59 VMOVQ	%XMM2,%RDX

0x232d5e VPEXTRQ	$0x1,%XMM2,%RSI

0x232d64 VEXTRACTI128	$0x1,%YMM3,%XMM2

0x232d6a VMOVSD	(%RBX,%RAX,8),%XMM3    [9]

0x232d6f VPEXTRQ	$0x1,%XMM2,%R10

0x232d75 VMOVQ	%XMM2,%R13

0x232d7a VMOVSD	(%RBX,%RDX,8),%XMM2    [9]

0x232d7f VMOVHPD	(%RBX,%RCX,8),%XMM3,%XMM3    [9]

0x232d84 VMOVHPD	(%RBX,%RSI,8),%XMM2,%XMM2    [9]

0x232d89 VINSERTF128	$0x1,%XMM2,%YMM3,%YMM2

0x232d8f VMOVSD	(%RBX,%R13,8),%XMM3    [9]

0x232d95 VMOVHPD	(%RBX,%R10,8),%XMM3,%XMM3    [9]

0x232d9b VINSERTF128	$0x1,%XMM3,%YMM4,%YMM3

0x232da1 VPMULLQ	0x2e0(%RSP),%YMM10,%YMM4    [8]

0x232da9 VPADDQ	%YMM19,%YMM4,%YMM4

0x232daf VMOVQ	%XMM4,%RAX

0x232db4 VPEXTRQ	$0x1,%XMM4,%RCX

0x232dba VEXTRACTI128	$0x1,%YMM4,%XMM4

0x232dc0 VMOVQ	%XMM4,%RDX

0x232dc5 VPEXTRQ	$0x1,%XMM4,%RSI

0x232dcb VEXTRACTI128	$0x1,%YMM6,%XMM4

0x232dd1 VMOVSD	(%RBX,%RAX,8),%XMM6    [9]

0x232dd6 VMOVQ	%XMM4,%R10

0x232ddb VPEXTRQ	$0x1,%XMM4,%R13

0x232de1 VMOVSD	(%RBX,%RDX,8),%XMM4    [9]

0x232de6 VMOVHPD	(%RBX,%RCX,8),%XMM6,%XMM6    [9]

0x232deb VMOVHPD	(%RBX,%RSI,8),%XMM4,%XMM4    [9]

0x232df0 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

0x232df6 VMOVSD	(%RBX,%R10,8),%XMM6    [9]

0x232dfc VMOVHPD	(%RBX,%R13,8),%XMM6,%XMM6    [9]

0x232e02 VSUBPD	%YMM4,%YMM2,%YMM18

0x232e08 VPMULLQ	%YMM10,%YMM23,%YMM4

0x232e0e VPADDQ	%YMM19,%YMM4,%YMM4

0x232e14 VMOVQ	%XMM4,%RAX

0x232e19 VPEXTRQ	$0x1,%XMM4,%RCX

0x232e1f VEXTRACTI128	$0x1,%YMM4,%XMM4

0x232e25 VMOVQ	%XMM4,%RDX

0x232e2a VPEXTRQ	$0x1,%XMM4,%RSI

0x232e30 VINSERTF128	$0x1,%XMM6,%YMM7,%YMM6

0x232e36 VSUBPD	%YMM6,%YMM3,%YMM28

0x232e3c VPMULLQ	%YMM10,%YMM24,%YMM6

0x232e42 VPADDQ	%YMM20,%YMM6,%YMM6

0x232e48 VEXTRACTI128	$0x1,%YMM6,%XMM4

0x232e4e VMOVQ	%XMM6,%R9

0x232e53 VPEXTRQ	$0x1,%XMM6,%R8

0x232e59 VMOVSD	(%RBX,%RAX,8),%XMM6    [9]

0x232e5e VMOVQ	%XMM4,%R10

0x232e63 VPEXTRQ	$0x1,%XMM4,%R13

0x232e69 VMOVSD	(%RBX,%RDX,8),%XMM4    [9]

0x232e6e VMOVHPD	(%RBX,%RCX,8),%XMM6,%XMM6    [9]

0x232e73 VMOVSD	(%RBX,%R9,8),%XMM7    [9]

0x232e79 VMOVHPD	(%RBX,%RSI,8),%XMM4,%XMM4    [9]

0x232e7e VMOVHPD	(%RBX,%R8,8),%XMM7,%XMM7    [9]

0x232e84 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

0x232e8a VMOVSD	(%RBX,%R10,8),%XMM6    [9]

0x232e90 VMOVHPD	(%RBX,%R13,8),%XMM6,%XMM6    [9]

0x232e96 VSUBPD	%YMM2,%YMM4,%YMM23

0x232e9c VINSERTF128	$0x1,%XMM6,%YMM7,%YMM6

0x232ea2 VSUBPD	%YMM3,%YMM6,%YMM24

0x232ea8 VMULPD	%YMM18,%YMM23,%YMM6

0x232eae VMULPD	%YMM28,%YMM24,%YMM4

0x232eb4 VCMPPD	$0x1,%YMM6,%YMM14,%K0

0x232ebb VCMPPD	$0x1,%YMM4,%YMM14,%K1

0x232ec2 KSHIFTLB	$0x4,%K1,%K1

0x232ec8 KORB	%K1,%K0,%K0

0x232ecc KORTESTB	%K0,%K0

0x232ed0 JE	232350

0x232ed6 MOV	0xc0(%RSP),%RAX    [8]

0x232ede VCMPPD	$0x1,%YMM24,%YMM14,%K2

0x232ee5 VCMPPD	$0x1,%YMM23,%YMM14,%K1

0x232eec VMOVSD	(%RDI,%RAX,8),%XMM7    [1]

0x232ef1 MOV	0xc8(%RSP),%RAX    [8]

0x232ef9 VMOVHPD	(%RDI,%RAX,8),%XMM7,%XMM7    [1]

0x232efe MOV	0xd0(%RSP),%RAX    [8]

0x232f06 VMOVSD	(%RDI,%RAX,8),%XMM9    [1]

0x232f0b MOV	0xd8(%RSP),%RAX    [8]

0x232f13 VMOVHPD	(%RDI,%RAX,8),%XMM9,%XMM9    [1]

0x232f18 MOV	0xb8(%RSP),%RAX    [8]

0x232f20 VMOVSD	(%RDI,%RAX,8),%XMM11    [1]

0x232f25 MOV	0xb0(%RSP),%RAX    [8]

0x232f2d VINSERTF128	$0x1,%XMM7,%YMM9,%YMM7

0x232f33 VMOVHPD	(%RDI,%RAX,8),%XMM11,%XMM11    [1]

0x232f38 MOV	0xa8(%RSP),%RAX    [8]

0x232f40 VMOVSD	(%RDI,%RAX,8),%XMM13    [1]

0x232f45 MOV	0xa0(%RSP),%RAX    [8]

0x232f4d VMOVHPD	(%RDI,%RAX,8),%XMM13,%XMM13    [1]

0x232f52 MOV	0xe8(%RSP),%RAX    [8]

0x232f5a VMOVSD	(%R11,%RAX,8),%XMM17    [2]

0x232f61 MOV	0xe0(%RSP),%RAX    [8]

0x232f69 VINSERTF128	$0x1,%XMM11,%YMM13,%YMM9

0x232f6f VANDPD	%YMM16,%YMM12,%YMM13

0x232f75 VMOVHPD	(%R11,%RAX,8),%XMM17,%XMM17    [2]

0x232f7c MOV	0x108(%RSP),%RAX    [8]

0x232f84 VMOVSD	(%R11,%RAX,8),%XMM26    [2]

0x232f8b MOV	0x100(%RSP),%RAX    [8]

0x232f93 VMOVHPD	(%R11,%RAX,8),%XMM26,%XMM26    [2]

0x232f9a MOV	0xf0(%RSP),%RAX    [8]

0x232fa2 VMOVSD	(%R11,%RAX,8),%XMM27    [2]

0x232fa9 MOV	0xf8(%RSP),%RAX    [8]

0x232fb1 VINSERTF32X4	$0x1,%XMM17,%YMM26,%YMM11

0x232fb8 VANDPD	%YMM16,%YMM24,%YMM26

0x232fbe VANDPD	%YMM16,%YMM23,%YMM17

0x232fc4 VMOVHPD	(%R11,%RAX,8),%XMM27,%XMM27    [2]

0x232fcb MOV	0x118(%RSP),%RAX    [8]

0x232fd3 VMULPD	%YMM7,%YMM11,%YMM7

0x232fd7 VANDPD	%YMM16,%YMM5,%YMM11

0x232fdd VDIVPD	%YMM7,%YMM13,%YMM7

0x232fe1 VMOVSD	(%R11,%RAX,8),%XMM30    [2]

0x232fe8 MOV	0x110(%RSP),%RAX    [8]

0x232ff0 VMOVHPD	(%R11,%RAX,8),%XMM30,%XMM30    [2]

0x232ff7 VINSERTF32X4	$0x1,%XMM27,%YMM30,%YMM13

0x232ffe VMULPD	%YMM9,%YMM13,%YMM9

0x233003 VDIVPD	%YMM9,%YMM11,%YMM9

0x233008 VBROADCASTSD	-0x21ec1(%RIP),%YMM11    [5]

0x233011 VSUBPD	%YMM7,%YMM11,%YMM7

0x233015 VSUBPD	%YMM9,%YMM11,%YMM9

0x23301a VBROADCASTSD	-0x21eab(%RIP),%YMM11    [5]

0x233023 VXORPD	%YMM7,%YMM11,%YMM13

0x233027 VXORPD	%YMM11,%YMM9,%YMM11

0x23302c VMOVAPD	%YMM9,%YMM11{%K2}

0x233032 VANDPD	%YMM16,%YMM28,%YMM9

0x233038 VMOVAPD	%YMM7,%YMM13{%K1}

0x23303e VANDPD	%YMM16,%YMM18,%YMM7

0x233044 VMINPD	%YMM26,%YMM9,%YMM24

0x23304a VMULPD	0x180(%RSP),%YMM9,%YMM9    [8]

0x233053 VMINPD	%YMM17,%YMM7,%YMM23

0x233059 VMULPD	%YMM31,%YMM7,%YMM7

0x23305f VFMADD213PD	%YMM7,%YMM17,%YMM25

0x233065 VFMADD213PD	%YMM9,%YMM26,%YMM29

0x23306b VBROADCASTSD	-0x21e8c(%RIP),%YMM9    [5]

0x233074 VMULPD	%YMM9,%YMM25,%YMM7

0x23307a VMULPD	%YMM9,%YMM29,%YMM9

0x233080 VMINPD	%YMM7,%YMM23,%YMM7

0x233086 VMINPD	%YMM9,%YMM24,%YMM9

0x23308c VMULPD	%YMM7,%YMM13,%YMM7

0x233090 VMULPD	%YMM9,%YMM11,%YMM9

0x233095 JMP	232350

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 158 - 202

--------------------------------------------------------------------------------

158:     for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) {

159:       for (int i = (x_min + 1); i < (x_max + 2); i++)

160:         ({

161:           int upwind, donor, downwind, dif;

162:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

163:           if (vol_flux_y(i, j) > 0.0) {

164:             upwind = j - 2;

165:             donor = j - 1;

166:             downwind = j;

167:             dif = donor;

168:           } else {

169:             upwind = std::min(j + 1, y_max + 2);

170:             donor = j;

171:             downwind = j - 1;

172:             dif = upwind;

173:           }

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.03 - 1.35
CQA speedup if FP arith vectorized	1.11
CQA speedup if fully vectorized	3.64 - 4.76
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14 - 1.31
Bottlenecks	P10, P11,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.12]
Source	advec_cell.cpp:158-202,context.h:46-46,context.h:69-69
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	91.75 - 120.00
CQA cycles if no scalar integer	88.75
CQA cycles if FP arith vectorized	79.00 - 108.00
CQA cycles if fully vectorized	25.20
Front-end cycles	80.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	8.00
P3 cycles	16.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	44.75
P7 cycles	44.75
P8 cycles	44.75
P9 cycles	44.75
P10 cycles	91.75
P11 cycles	91.75
P12 cycles	91.75
P13 cycles	91.75
P14 cycles	67.50
P15 cycles	67.50
DIV/SQRT cycles	80.00 - 120.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	577.00
Nb uops	644.00
Nb loads	149.00
Nb stores	38.00
Nb stack references	36.00
FLOP/cycle	2.53 - 1.93
Nb FLOP add-sub	72.00
Nb FLOP mul	88.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.03 - 20.97
Bytes prefetched	0.00
Bytes loaded	1500.00
Bytes stored	424.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	49.07
Vectorization ratio load	15.57
Vectorization ratio store	13.16
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	42.86
Vectorization ratio other	50.36
Vector-efficiency ratio all	26.89
Vector-efficiency ratio load	17.26
Vector-efficiency ratio store	17.43
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	45.19
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	28.57
Vector-efficiency ratio other	24.93

Metric	Value
CQA speedup if no scalar integer	1.03 - 1.35
CQA speedup if FP arith vectorized	1.11
CQA speedup if fully vectorized	3.64 - 4.76
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.14 - 1.31
Bottlenecks	P10, P11,
Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.12]
Source	advec_cell.cpp:158-202,context.h:46-46,context.h:69-69
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	91.75 - 120.00
CQA cycles if no scalar integer	88.75
CQA cycles if FP arith vectorized	79.00 - 108.00
CQA cycles if fully vectorized	25.20
Front-end cycles	80.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	8.00
P3 cycles	16.00
P4 cycles	3.00
P5 cycles	3.00
P6 cycles	44.75
P7 cycles	44.75
P8 cycles	44.75
P9 cycles	44.75
P10 cycles	91.75
P11 cycles	91.75
P12 cycles	91.75
P13 cycles	91.75
P14 cycles	67.50
P15 cycles	67.50
DIV/SQRT cycles	80.00 - 120.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	577.00
Nb uops	644.00
Nb loads	149.00
Nb stores	38.00
Nb stack references	36.00
FLOP/cycle	2.53 - 1.93
Nb FLOP add-sub	72.00
Nb FLOP mul	88.00
Nb FLOP fma	24.00
Nb FLOP div	24.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	16.03 - 20.97
Bytes prefetched	0.00
Bytes loaded	1500.00
Bytes stored	424.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	49.07
Vectorization ratio load	15.57
Vectorization ratio store	13.16
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	42.86
Vectorization ratio other	50.36
Vector-efficiency ratio all	26.89
Vector-efficiency ratio load	17.26
Vector-efficiency ratio store	17.43
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	45.19
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	28.57
Vector-efficiency ratio other	24.93

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.12]
Source file and lines	advec_cell.cpp:158-202
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158-202
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

It is main loop of related source loop which is unrolled by 8 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 16 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 120.00 to 88.75 cycles (1.35x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions).

Details

49% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

15% of SSE/AVX loads are used in vector version.
13% of SSE/AVX stores are used in vector version.
42% of SSE/AVX divide and square root instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by execution of divide and square root operations (the divide/square root unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 120.00 to 91.75 cycles (1.31x speedup).

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 120.00 to 93.75 cycles (1.28x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
KORTESTB: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:169
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:182
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:195
VMOVHPD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
VPEXTRQ: 55 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Vector unaligned load/store instructions

Detected 28 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
VINSERTF128: 18 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
VINSERTF32X4: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
VPMOVQD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:159
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:159

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

76 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 232 FP arithmetical operations:

96: addition or subtraction (24 inside FMA instructions)
112: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1500 bytes (187 double precision FP elements). The binary loop is storing 424 bytes (53 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	577
nb uops	644
loop length	3402
used x86 registers	15
used mmx registers	0
used xmm registers	21
used ymm registers	32
used zmm registers	0
nb stack references	36
ADD-SUB / MUL ratio	0.82

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	80.50 cycles
front end	80.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	8.00	16.00	3.00	3.00	44.75	44.75	44.75	44.75	91.75	91.75	91.75	91.75	67.50	67.50
cycles	0.50	0.50	8.00	16.00	3.00	3.00	44.75	44.75	44.75	44.75	91.75	91.75	91.75	91.75	67.50	67.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

80.00-120.00

Cycles summary

Front-end	80.50
Dispatch	91.75
DIV/SQRT	80.00-120.00
Overall L1	91.75-120.00

Vectorization ratios

INT

all	45%
load	92%
store	10%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	53%
load	5%
store	15%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	92%

INT+FP

all	49%
load	15%
store	13%
mul	100%
add-sub	100%
fma	100%
div/sqrt	42%
other	50%

Vector efficiency ratios

INT

all	24%
load	37%
store	16%
mul	50%
add-sub	42%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	29%
load	14%
store	18%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	38%

INT+FP

all	26%
load	17%
store	17%
mul	50%
add-sub	45%
fma	50%
div/sqrt	28%
other	24%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 120.00 cycles. At this rate:

4% of peak load performance is reached (12.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 232432

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VCMPPD $0x1,%YMM4,%YMM14,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VCMPPD $0x1,%YMM6,%YMM14,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VPADDQ 0x1c0(%RSP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VANDPD %YMM4,%YMM15,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM6,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPEQQ %YMM15,%YMM4,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPCMPEQQ %YMM15,%YMM6,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM9,%YMM3,%YMM3{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM7,%YMM2,%YMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM5,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA 0x220(%RSP),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM2,%YMM12,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM21,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM22,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM20,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM5,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM5,%R9	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVLPD %XMM2,(%R12,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x120(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD %XMM2,(%R12,%RAX,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVLPD %XMM2,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R12,%RSI,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVLPD %XMM3,(%R12,%R8,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM3,(%R12,%R9,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VMOVLPD %XMM2,(%R12,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R12,%R13,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
ADD $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 23309a <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0xffa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA 0x140(%RSP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
MOV %RCX,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPADDQ 0x200(%RSP),%YMM0,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VPEXTRQ $0x1,%XMM1,%R9	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
CQTO																				scal (12.5%)
VPEXTRQ $0x1,%XMM5,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM5,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %RAX,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM2,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %RAX,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPEXTRQ $0x1,%XMM0,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
CQTO																				scal (12.5%)
VPUNPCKLQDQ %XMM4,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
IDIV %R9	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %XMM1,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %RAX,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM0,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %R9	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %RAX,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPUNPCKLQDQ %XMM4,%XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM5,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VINSERTI128 $0x1,%XMM2,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
CQTO																				scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VPEXTRQ $0x1,%XMM1,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %RAX,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM5,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %RAX,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
CQTO																				scal (12.5%)
VPUNPCKLQDQ %XMM2,%XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %XMM1,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %RSI,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVDQA 0x170(%RSP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x68(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %RAX,%XMM6	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPUNPCKLQDQ %XMM5,%XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VPMOVQD %YMM4,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM1,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VINSERTI128 $0x1,%XMM2,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPMOVQD %YMM5,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM1,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPSUBQ %YMM4,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDD %XMM6,%XMM9,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVQD %YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPSUBQ %YMM5,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMOVSXDQ %XMM2,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVQD %YMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPADDD %XMM7,%XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVDQA 0x160(%RSP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPMOVSXDQ %XMM3,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPADDD %XMM5,%XMM9,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM4,%XMM9,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVDQA 0x150(%RSP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPMOVSXDQ %XMM5,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVDQA 0x280(%RSP),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXDQ %XMM4,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMULLQ %YMM21,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM22,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM20,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM5,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM5,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R15,%RAX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15,%RDX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R15,%RCX,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R15,%RSI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM5,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R15,%R8,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R15,%R9,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R15,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R15,%R10,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VCMPPD $0x1,%YMM12,%YMM14,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM4,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPADDD %XMM6,%XMM9,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM7,%XMM9,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCMPPD $0x1,%YMM5,%YMM14,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORB %K1,%K0,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JB 23267d <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x5dd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA 0x130(%RSP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPCMPEQD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM4,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM6,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBD %XMM9,%XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSUBD %XMM9,%XMM3,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMINSD %XMM7,%XMM11,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMINSD %XMM9,%XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM7,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM9,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VCMPPD $0x1,%YMM5,%YMM14,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VCMPPD $0x1,%YMM12,%YMM14,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VANDPD %YMM15,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM7,%YMM15,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPEQQ %YMM15,%YMM9,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPCMPEQQ %YMM15,%YMM7,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KSHIFTLB $0x4,%K2,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORB %K0,%K1,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 2326d2 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x632>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTD -0x2faa2(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (6.3%)
VPMOVSXDQ %XMM6,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPADDD %XMM7,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM7,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM4,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM2,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM3,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVDQA 0x260(%RSP),%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPBLENDMQ %YMM7,%YMM21,%YMM28{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPBLENDMQ %YMM9,%YMM22,%YMM18{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM12,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM5,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPBLENDMQ %YMM11,%YMM26,%YMM17{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQA64 %YMM7,%YMM26{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM13,%YMM25,%YMM13{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQA64 %YMM9,%YMM25{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VEXTRACTI32X4 $0x1,%YMM25,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQA64 %YMM21,%YMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA64 %YMM22,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA64 %YMM17,0x2e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQA %YMM13,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPMULLQ %YMM6,%YMM28,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM6,%YMM18,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM20,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM6,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R15	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R11,%RDX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R11,%R10,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RSI,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV %R10,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVHPD (%R11,%R15,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV %R8,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM21,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RCX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM21,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%RAX,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VDIVPD %YMM4,%YMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMOVSD (%R11,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R8,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM22,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VEXTRACTI32X4 $0x1,%YMM22,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM6,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VDIVPD %YMM4,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VEXTRACTI32X4 $0x1,%YMM21,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%RDX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM22,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R14,%RSI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM6,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RCX,8),%XMM7,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R14,%R8,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM26,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM25,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDX,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R14,%RSI,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RAX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM26,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R14,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VFMADD213PD %YMM4,%YMM2,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM6,%YMM7,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VEXTRACTI32X4 $0x1,%YMM26,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM7,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM7,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%RDX,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM25,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VFMADD213PD %YMM6,%YMM3,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x1e0(%RSP),%YMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVHPD (%R14,%RSI,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RCX,8),%XMM11,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R14,%R8,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM7,%YMM9,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R14,%RSI,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RAX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VDIVPD %YMM7,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VPMULLQ %YMM8,%YMM13,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM20,%YMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VINSERTF128 $0x1,%XMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM4,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VDIVPD %YMM9,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VPMULLQ %YMM8,%YMM18,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM20,%YMM6,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMULLQ %YMM8,%YMM17,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM8,%YMM24,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM20,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VEXTRACTI128 $0x1,%YMM6,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM9,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RCX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RDI,%RCX,8),%XMM11,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM6,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM7,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RDI,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%RDI,%RCX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM6,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM7,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %YMM4,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM25,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVHPD (%RDI,%RCX,8),%XMM6,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM29,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM6,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
MOV %RCX,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %YMM4,0x2a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPMULLQ %YMM8,%YMM28,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VINSERTF128 $0x1,%XMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM4,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM7,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RDI,%RSI,8),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVHPD (%RDI,%RAX,8),%XMM4,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPMULLQ %YMM8,%YMM23,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVHPD (%RDI,%RDX,8),%XMM31,%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV %R9,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VEXTRACTI32X4 $0x1,%YMM4,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM26,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM26,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RDI,%RAX,8),%XMM27,%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM17,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VINSERTF128 $0x1,%XMM13,%YMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVHPD (%RDI,%RAX,8),%XMM27,%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RDI,%RAX,8),%XMM30,%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM17,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM17,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RDI,%RAX,8),%XMM4,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%RDI,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%RDI,%R8,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RAX,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM29,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVHPD (%RDI,%RCX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM4,%YMM31,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%RDI,%RAX,8),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM29,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RDI,%RAX,8),%XMM31,%XMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBPD %YMM9,%YMM4,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM30,%YMM17,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VINSERTF32X4 $0x1,%XMM6,%YMM29,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM3,%YMM25,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVAPD 0x2a0(%RSP),%YMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM7,%YMM6,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM26,%YMM27,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM6,%YMM9,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM7,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM11,%YMM17,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM13,%YMM26,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM7,%YMM14,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM9,%YMM14,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORB %K1,%K0,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 232c1f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0xb7f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD -0x21a28(%RIP),%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPPD $0x1,%YMM26,%YMM14,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM17,%YMM14,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM27,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM27,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VBROADCASTSD -0x21a24(%RIP),%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %YMM27,%YMM2,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VXORPD %YMM27,%YMM3,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM26,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM2,%YMM30{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM31{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VANDPD %YMM16,%YMM13,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM17,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM11,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMINPD %YMM13,%YMM3,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD 0x180(%RSP),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM27,%YMM2,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD 0x1a0(%RSP),%YMM2,%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM29,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD -0x21a11(%RIP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %YMM27,%YMM25,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM2,%YMM13,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM2,%YMM17,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM30,%YMM2,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM3,%YMM13,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM2,%YMM26,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM31,%YMM2,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM7,%YMM14,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VCMPPD $0x1,%YMM9,%YMM14,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV 0x60(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD 0x1a0(%RSP),%YMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM3,%YMM15,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM2,%YMM15,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPEQQ %YMM15,%YMM3,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVDQA 0x240(%RSP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPCMPEQQ %YMM15,%YMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM27,%YMM4,%YMM4{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM30,%YMM6,%YMM6{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM4,%YMM12,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM5,%YMM6,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ 0x2c0(%RSP),%YMM10,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM21,%YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM22,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM20,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM2,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM2,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R9	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVLPD %XMM12,(%R15,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM12,(%R15,%R8,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VPMULLQ %YMM10,%YMM18,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVQ %XMM2,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM12,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %YMM20,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVLPD %XMM2,(%R15,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R15,%R9,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVLPD %XMM5,(%R15,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM5,(%R15,%RDX,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VPADDQ %YMM20,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM3,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%R9	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVLPD %XMM2,(%R15,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R15,%R10,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VPMULLQ %YMM10,%YMM28,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD (%RBX,%R8,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM6,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RBX,%R9,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM6,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPADDQ %YMM19,%YMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVSD (%RBX,%R9,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM2,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVHPD (%RBX,%R8,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM2,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RBX,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM2,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RBX,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RCX,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RBX,%RSI,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM2,%YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%RBX,%R13,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%R10,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM3,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPMULLQ 0x2e0(%RSP),%YMM10,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RBX,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RBX,%RDX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RCX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RBX,%RSI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%RBX,%R10,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%R13,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VSUBPD %YMM4,%YMM2,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VPMULLQ %YMM10,%YMM23,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM6,%YMM7,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM6,%YMM3,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VPMULLQ %YMM10,%YMM24,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM20,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VEXTRACTI128 $0x1,%YMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM6,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM6,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RBX,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RBX,%RDX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RCX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%RBX,%R9,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RSI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RBX,%R8,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%RBX,%R10,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%R13,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VSUBPD %YMM2,%YMM4,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM6,%YMM7,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM3,%YMM6,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM18,%YMM23,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM28,%YMM24,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM6,%YMM14,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM4,%YMM14,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORB %K1,%K0,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 232350 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xc0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCMPPD $0x1,%YMM24,%YMM14,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM23,%YMM14,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%RDI,%RAX,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%RDI,%RAX,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI,%RAX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%RDI,%RAX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xb8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VINSERTF128 $0x1,%XMM7,%YMM9,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVHPD (%RDI,%RAX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xa8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI,%RAX,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%RDI,%RAX,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xe8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R11,%RAX,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VINSERTF128 $0x1,%XMM11,%YMM13,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VANDPD %YMM16,%YMM12,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVHPD (%R11,%RAX,8),%XMM17,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x108(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R11,%RAX,8),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x100(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R11,%RAX,8),%XMM26,%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xf0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R11,%RAX,8),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xf8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VINSERTF32X4 $0x1,%XMM17,%YMM26,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VANDPD %YMM16,%YMM24,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM23,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVHPD (%R11,%RAX,8),%XMM27,%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x118(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULPD %YMM7,%YMM11,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM16,%YMM5,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VDIVPD %YMM7,%YMM13,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMOVSD (%R11,%RAX,8),%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R11,%RAX,8),%XMM30,%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM27,%YMM30,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMULPD %YMM9,%YMM13,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VBROADCASTSD -0x21ec1(%RIP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBPD %YMM7,%YMM11,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VBROADCASTSD -0x21eab(%RIP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %YMM7,%YMM11,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VXORPD %YMM11,%YMM9,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM9,%YMM11{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VANDPD %YMM16,%YMM28,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM7,%YMM13{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VANDPD %YMM16,%YMM18,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMINPD %YMM26,%YMM9,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD 0x180(%RSP),%YMM9,%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM17,%YMM7,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM31,%YMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM7,%YMM17,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM9,%YMM26,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD -0x21e8c(%RIP),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %YMM9,%YMM25,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM9,%YMM29,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM7,%YMM23,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMINPD %YMM9,%YMM24,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM7,%YMM13,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
JMP 232350 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Function	advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&) [clone .omp_outlined.12]
Source file and lines	advec_cell.cpp:158-202
Module	exec

The loop is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158-202
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

It is main loop of related source loop which is unrolled by 8 (including vectorization).
Warnings:

Ignoring paths for analysis
Too many paths. Rerun with max-paths=16
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is poorly vectorized. Only 26% of vector register length is used (average across all SSE/AVX instructions).

Details

49% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

15% of SSE/AVX loads are used in vector version.
13% of SSE/AVX stores are used in vector version.
42% of SSE/AVX divide and square root instructions are used in vector version.
50% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Workaround

Reduce the number of division or square root instructions:
- If denominator is constant over iterations, use reciprocal (replace x/y with x*(1/y)). Check precision impact. This will be done by your compiler with ffast-math or Ofast
Check whether you really need double precision. If not, switch to single precision to speedup execution

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 120.00 to 93.75 cycles (1.28x speedup).

Masked instructions

Detected masked instructions.

Details

Vector registers are partially exploited, which is expected if your loop is irregular or mixes elements of different sizes.

Workaround

If your loop is irregular, try to remove or hoist conditional structures out of your loop. If it mixes elements of different sizes, try to uniformize them.

FMA

Detected 24 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

IDIV: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
KORTESTB: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:169
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:182
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:195
VMOVHPD: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
VPEXTRQ: 55 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Vector unaligned load/store instructions

Detected 28 suboptimal vector unaligned load/store instructions.

Details

VEXTRACTF128: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:202
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:189
VINSERTF128: 18 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:163
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:174
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:175
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:191
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:192
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
VINSERTF32X4: 6 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:178
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:179
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:190

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

CQTO: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
VPMOVQD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:159
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:159

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

76 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 232 FP arithmetical operations:

96: addition or subtraction (24 inside FMA instructions)
112: multiply (24 inside FMA instructions)
24: divide

The binary loop is loading 1500 bytes (187 double precision FP elements). The binary loop is storing 424 bytes (53 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	577
nb uops	644
loop length	3402
used x86 registers	15
used mmx registers	0
used xmm registers	21
used ymm registers	32
used zmm registers	0
nb stack references	36
ADD-SUB / MUL ratio	0.82

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	80.50 cycles
front end	80.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	0.50	0.50	8.00	16.00	3.00	3.00	44.75	44.75	44.75	44.75	91.75	91.75	91.75	91.75	67.50	67.50
cycles	0.50	0.50	8.00	16.00	3.00	3.00	44.75	44.75	44.75	44.75	91.75	91.75	91.75	91.75	67.50	67.50

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

80.00-120.00

Cycles summary

Front-end	80.50
Dispatch	91.75
DIV/SQRT	80.00-120.00
Overall L1	91.75-120.00

Vectorization ratios

INT

all	45%
load	92%
store	10%
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	30%

all	53%
load	5%
store	15%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	92%

INT+FP

all	49%
load	15%
store	13%
mul	100%
add-sub	100%
fma	100%
div/sqrt	42%
other	50%

Vector efficiency ratios

INT

all	24%
load	37%
store	16%
mul	50%
add-sub	42%
fma	NA (no fma vectorizable/vectorized instructions)
other	18%

all	29%
load	14%
store	18%
mul	50%
add-sub	50%
fma	50%
div/sqrt	50%
other	38%

INT+FP

all	26%
load	17%
store	17%
mul	50%
add-sub	45%
fma	50%
div/sqrt	28%
other	24%

Cycles and memory resources usage

Detected masked instructions: assuming all mask elements are active. Assuming all data fit into the L1 cache, each iteration of the binary loop takes 120.00 cycles. At this rate:

4% of peak load performance is reached (12.50 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (3.53 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 232432

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
VCMPPD $0x1,%YMM4,%YMM14,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VCMPPD $0x1,%YMM6,%YMM14,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VPADDQ 0x1c0(%RSP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VANDPD %YMM4,%YMM15,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM6,%YMM15,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPEQQ %YMM15,%YMM4,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPCMPEQQ %YMM15,%YMM6,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM9,%YMM3,%YMM3{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM7,%YMM2,%YMM2{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM5,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVDQA 0x220(%RSP),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM2,%YMM12,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM21,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM22,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM20,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM4,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM5,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM5,%R9	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVLPD %XMM2,(%R12,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV 0x120(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD %XMM2,(%R12,%RAX,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVLPD %XMM2,(%R12,%RDX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R12,%RSI,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVLPD %XMM3,(%R12,%R8,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM3,(%R12,%R9,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VMOVLPD %XMM2,(%R12,%R10,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R12,%R13,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
ADD $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
JE 23309a <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0xffa>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA 0x140(%RSP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VEXTRACTI128 $0x1,%YMM0,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
MOV %RCX,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPADDQ 0x200(%RSP),%YMM0,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VPEXTRQ $0x1,%XMM1,%R9	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
CQTO																				scal (12.5%)
VPEXTRQ $0x1,%XMM5,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM5,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %RAX,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM2,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %RAX,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPEXTRQ $0x1,%XMM0,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
CQTO																				scal (12.5%)
VPUNPCKLQDQ %XMM4,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
IDIV %R9	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %XMM1,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %RAX,%XMM4	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM0,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %R9	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %RAX,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPUNPCKLQDQ %XMM4,%XMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM5,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VINSERTI128 $0x1,%XMM2,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
CQTO																				scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VPEXTRQ $0x1,%XMM1,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %RAX,%XMM2	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VMOVQ %XMM5,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RSI	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %RAX,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
CQTO																				scal (12.5%)
VPUNPCKLQDQ %XMM2,%XMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVQ %XMM1,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VMOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %RSI,%XMM5	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
CQTO																				scal (12.5%)
IDIV %RCX	2	0	0	0	2	0	0	0	0	0	0	0	0	0	0	0	0	9-19	7-12	scal (12.5%)
VMOVDQA 0x170(%RSP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
MOV 0x68(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVQ %RAX,%XMM6	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	2	1	scal (12.5%)
VPUNPCKLQDQ %XMM5,%XMM6,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	scal (12.5%)
VPMOVQD %YMM4,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM1,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VINSERTI128 $0x1,%XMM2,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPMOVQD %YMM5,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPMULLQ %YMM1,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPSUBQ %YMM4,%YMM0,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDD %XMM6,%XMM9,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVQD %YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPSUBQ %YMM5,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMOVSXDQ %XMM2,%YMM21	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVQD %YMM3,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPADDD %XMM7,%XMM9,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVDQA 0x160(%RSP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPMOVSXDQ %XMM3,%YMM22	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPADDD %XMM5,%XMM9,%XMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM4,%XMM9,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VMOVDQA 0x150(%RSP),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPMOVSXDQ %XMM5,%YMM20	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVDQA 0x280(%RSP),%YMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPMOVSXDQ %XMM4,%YMM19	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMULLQ %YMM21,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM22,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM20,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM5,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM5,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM5,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R15,%RAX,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R15,%RDX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R15,%RCX,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R15,%RSI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM5,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R15,%R8,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD (%R15,%R9,8),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R15,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%R15,%R10,8),%XMM5,%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VCMPPD $0x1,%YMM12,%YMM14,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM4,%YMM5,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPADDD %XMM6,%XMM9,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM7,%XMM9,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VCMPPD $0x1,%YMM5,%YMM14,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORB %K1,%K0,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JB 23267d <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x5dd>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVDQA 0x130(%RSP),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (25.0%)
VPCMPEQD %XMM9,%XMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM4,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM6,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPSUBD %XMM9,%XMM2,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPSUBD %XMM9,%XMM3,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMINSD %XMM7,%XMM11,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMINSD %XMM9,%XMM11,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM7,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM9,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VCMPPD $0x1,%YMM5,%YMM14,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VCMPPD $0x1,%YMM12,%YMM14,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VANDPD %YMM15,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM7,%YMM15,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPEQQ %YMM15,%YMM9,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VPCMPEQQ %YMM15,%YMM7,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KSHIFTLB $0x4,%K2,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORB %K0,%K1,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 2326d2 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x632>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTD -0x2faa2(%RIP),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (6.3%)
VPMOVSXDQ %XMM6,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPADDD %XMM7,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPADDD %XMM7,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (25.0%)
VPMOVSXDQ %XMM4,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM2,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VPMOVSXDQ %XMM3,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50	vect (25.0%)
VMOVDQA 0x260(%RSP),%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPBLENDMQ %YMM7,%YMM21,%YMM28{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPBLENDMQ %YMM9,%YMM22,%YMM18{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM12,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM5,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPBLENDMQ %YMM11,%YMM26,%YMM17{%K1}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQA64 %YMM7,%YMM26{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VPBLENDMQ %YMM13,%YMM25,%YMM13{%K2}	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVDQA64 %YMM9,%YMM25{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VEXTRACTI32X4 $0x1,%YMM25,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVDQA64 %YMM21,%YMM23{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA64 %YMM22,%YMM24{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVDQA64 %YMM17,0x2e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQA %YMM13,0x2c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPMULLQ %YMM6,%YMM28,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM6,%YMM18,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM20,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM6,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R15	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%R11,%RDX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RDX,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R11,%R10,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RSI,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV %R10,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R15,0xe0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVHPD (%R11,%R15,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV %R8,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R11,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM21,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R11,%RCX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM21,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%RAX,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VDIVPD %YMM4,%YMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMOVSD (%R11,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R11,%R8,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM22,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VEXTRACTI32X4 $0x1,%YMM22,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM6,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VDIVPD %YMM4,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VEXTRACTI32X4 $0x1,%YMM21,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%RDX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM22,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%R14,%RSI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM6,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RCX,8),%XMM7,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R14,%R8,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM26,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM25,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDX,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R14,%RSI,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RAX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM26,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%R14,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VFMADD213PD %YMM4,%YMM2,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM6,%YMM7,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VEXTRACTI32X4 $0x1,%YMM26,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM7,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM7,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%R14,%RDX,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM25,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VFMADD213PD %YMM6,%YMM3,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMOVAPD 0x1e0(%RSP),%YMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VMOVHPD (%R14,%RSI,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM9,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RCX,8),%XMM11,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%R14,%R8,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RDX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM7,%YMM9,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%R14,%RSI,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%R14,%RAX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VDIVPD %YMM7,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VPMULLQ %YMM8,%YMM13,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM20,%YMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VINSERTF128 $0x1,%XMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVAPD %YMM4,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VDIVPD %YMM9,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VPMULLQ %YMM8,%YMM18,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM20,%YMM6,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPMULLQ %YMM8,%YMM17,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM8,%YMM24,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM20,%YMM17,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VEXTRACTI128 $0x1,%YMM6,%XMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVQ %XMM9,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RCX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM9,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RDI,%RCX,8),%XMM11,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM6,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM7,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RDI,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%RDI,%RCX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM6,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM7,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVAPD %YMM4,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM25,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVHPD (%RDI,%RCX,8),%XMM6,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM29,%XMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM6,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
MOV %RCX,0xb0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVAPD %YMM4,0x2a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPMULLQ %YMM8,%YMM28,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VINSERTF128 $0x1,%XMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVQ %XMM4,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPEXTRQ $0x1,%XMM4,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM4,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM7,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RDI,%RSI,8),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RSI,0xd0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVHPD (%RDI,%RAX,8),%XMM4,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VPMULLQ %YMM8,%YMM23,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVHPD (%RDI,%RDX,8),%XMM31,%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV %R9,0xc0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0xc8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VEXTRACTI32X4 $0x1,%YMM4,%XMM26	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM26,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM26,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RDI,%RAX,8),%XMM27,%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI32X4 $0x1,%YMM17,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VINSERTF128 $0x1,%XMM13,%YMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVHPD (%RDI,%RAX,8),%XMM27,%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RDI,%RAX,8),%XMM30,%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM17,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM17,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RDI,%RAX,8),%XMM4,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%RDI,%R9,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM6,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD (%RDI,%R8,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%RDI,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RAX,0xb8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVQ %XMM29,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
MOV %RAX,0xa8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVHPD (%RDI,%RCX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM4,%YMM31,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%RDI,%RAX,8),%XMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM29,%RAX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RDI,%RAX,8),%XMM31,%XMM29	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV %RAX,0xa0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBPD %YMM9,%YMM4,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM30,%YMM17,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VINSERTF32X4 $0x1,%XMM6,%YMM29,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM3,%YMM25,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMOVAPD 0x2a0(%RSP),%YMM25	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VSUBPD %YMM7,%YMM6,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VINSERTF32X4 $0x1,%XMM26,%YMM27,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM6,%YMM9,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM4,%YMM7,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM11,%YMM17,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM13,%YMM26,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM7,%YMM14,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM9,%YMM14,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORB %K1,%K0,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 232c1f <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0xb7f>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VBROADCASTSD -0x21a28(%RIP),%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VCMPPD $0x1,%YMM26,%YMM14,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM17,%YMM14,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VSUBPD %YMM2,%YMM27,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM3,%YMM27,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VBROADCASTSD -0x21a24(%RIP),%YMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %YMM27,%YMM2,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VXORPD %YMM27,%YMM3,%YMM31	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM26,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM2,%YMM30{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VMOVAPD %YMM3,%YMM31{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VANDPD %YMM16,%YMM13,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM17,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM11,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMINPD %YMM13,%YMM3,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD 0x180(%RSP),%YMM3,%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM27,%YMM2,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD 0x1a0(%RSP),%YMM2,%YMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD231PD %YMM13,%YMM29,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD -0x21a11(%RIP),%YMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VFMADD231PD %YMM27,%YMM25,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VMULPD %YMM2,%YMM13,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM2,%YMM17,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM30,%YMM2,%YMM27	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM3,%YMM13,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM2,%YMM26,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM31,%YMM2,%YMM30	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM7,%YMM14,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VCMPPD $0x1,%YMM9,%YMM14,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
MOV 0x60(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVAPD 0x1a0(%RSP),%YMM31	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM3,%YMM15,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM2,%YMM15,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPCMPEQQ %YMM15,%YMM3,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVDQA 0x240(%RSP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.50	vect (50.0%)
VPCMPEQQ %YMM15,%YMM2,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VADDPD %YMM27,%YMM4,%YMM4{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VADDPD %YMM30,%YMM6,%YMM6{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM4,%YMM12,%YMM12	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM5,%YMM6,%YMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ 0x2c0(%RSP),%YMM10,%YMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM21,%YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPMULLQ %YMM22,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VPADDQ %YMM20,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM2,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM3,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%RDX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM2,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R9	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVLPD %XMM12,(%R15,%RCX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM12,(%R15,%R8,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VPMULLQ %YMM10,%YMM18,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVQ %XMM2,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM12,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPADDQ %YMM20,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVLPD %XMM2,(%R15,%R13,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R15,%R9,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VEXTRACTF128 $0x1,%YMM5,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVLPD %XMM5,(%R15,%RAX,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM5,(%R15,%RDX,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VPADDQ %YMM20,%YMM3,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM3,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM3,%R9	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVLPD %XMM2,(%R15,%RSI,8)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVHPD %XMM2,(%R15,%R10,8)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.50	0.50	9-11	0.50	scal (12.5%)
VPMULLQ %YMM10,%YMM28,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMOVSD (%RBX,%R8,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM6,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVHPD (%RBX,%R9,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM6,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPADDQ %YMM19,%YMM2,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVSD (%RBX,%R9,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM2,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVHPD (%RBX,%R8,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVQ %XMM2,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM3,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RBX,%RAX,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM2,%R10	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVQ %XMM2,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VMOVSD (%RBX,%RDX,8),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RCX,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RBX,%RSI,8),%XMM2,%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM2,%YMM3,%YMM2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%RBX,%R13,8),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%R10,8),%XMM3,%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM3,%YMM4,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VPMULLQ 0x2e0(%RSP),%YMM10,%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVSD (%RBX,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RBX,%RDX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RCX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RBX,%RSI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%RBX,%R10,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%R13,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VSUBPD %YMM4,%YMM2,%YMM18	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VPMULLQ %YMM10,%YMM23,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM19,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVQ %XMM4,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RCX	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VEXTRACTI128 $0x1,%YMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM4,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%RSI	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM6,%YMM7,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM6,%YMM3,%YMM28	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VPMULLQ %YMM10,%YMM24,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VPADDQ %YMM20,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VEXTRACTI128 $0x1,%YMM6,%XMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VMOVQ %XMM6,%R9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM6,%R8	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RBX,%RAX,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVQ %XMM4,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	0.50	scal (12.5%)
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	6	0.50	scal (12.5%)
VMOVSD (%RBX,%RDX,8),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RCX,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVSD (%RBX,%R9,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%RSI,8),%XMM4,%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VMOVHPD (%RBX,%R8,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF128 $0x1,%XMM4,%YMM6,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVSD (%RBX,%R10,8),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVHPD (%RBX,%R13,8),%XMM6,%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VSUBPD %YMM2,%YMM4,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VINSERTF128 $0x1,%XMM6,%YMM7,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VSUBPD %YMM3,%YMM6,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM18,%YMM23,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM28,%YMM24,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VCMPPD $0x1,%YMM6,%YMM14,%K0	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM4,%YMM14,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
KSHIFTLB $0x4,%K1,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORB %K1,%K0,%K0	1	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0	0	1	0.50	N/A
KORTESTB %K0,%K0	2	0	0	0	0	0	0	0	0	0	0	0.50	0	0	0.50	0.50	0.50	4	0.50	N/A
JE 232350 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0xc0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VCMPPD $0x1,%YMM24,%YMM14,%K2	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VCMPPD $0x1,%YMM23,%YMM14,%K1	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	0.50	vect (50.0%)
VMOVSD (%RDI,%RAX,8),%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xc8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%RDI,%RAX,8),%XMM7,%XMM7	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xd0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI,%RAX,8),%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xd8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%RDI,%RAX,8),%XMM9,%XMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xb8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI,%RAX,8),%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xb0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VINSERTF128 $0x1,%XMM7,%YMM9,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMOVHPD (%RDI,%RAX,8),%XMM11,%XMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xa8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%RDI,%RAX,8),%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xa0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%RDI,%RAX,8),%XMM13,%XMM13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xe8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R11,%RAX,8),%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xe0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VINSERTF128 $0x1,%XMM11,%YMM13,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VANDPD %YMM16,%YMM12,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVHPD (%R11,%RAX,8),%XMM17,%XMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x108(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R11,%RAX,8),%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x100(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R11,%RAX,8),%XMM26,%XMM26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0xf0(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVSD (%R11,%RAX,8),%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0xf8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VINSERTF32X4 $0x1,%XMM17,%YMM26,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VANDPD %YMM16,%YMM24,%YMM26	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VANDPD %YMM16,%YMM23,%YMM17	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVHPD (%R11,%RAX,8),%XMM27,%XMM27	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
MOV 0x118(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMULPD %YMM7,%YMM11,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VANDPD %YMM16,%YMM5,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VDIVPD %YMM7,%YMM13,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VMOVSD (%R11,%RAX,8),%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV 0x110(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVHPD (%R11,%RAX,8),%XMM30,%XMM30	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	9	0.50	scal (12.5%)
VINSERTF32X4 $0x1,%XMM27,%YMM30,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50	vect (25.0%)
VMULPD %YMM9,%YMM13,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VDIVPD %YMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	4	vect (50.0%)
VBROADCASTSD -0x21ec1(%RIP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VSUBPD %YMM7,%YMM11,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VSUBPD %YMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VBROADCASTSD -0x21eab(%RIP),%YMM11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VXORPD %YMM7,%YMM11,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VXORPD %YMM11,%YMM9,%YMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM9,%YMM11{%K2}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VANDPD %YMM16,%YMM28,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMOVAPD %YMM7,%YMM13{%K1}	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (50.0%)
VANDPD %YMM16,%YMM18,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25	vect (50.0%)
VMINPD %YMM26,%YMM9,%YMM24	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD 0x180(%RSP),%YMM9,%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM17,%YMM7,%YMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM31,%YMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VFMADD213PD %YMM7,%YMM17,%YMM25	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VFMADD213PD %YMM9,%YMM26,%YMM29	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50	vect (50.0%)
VBROADCASTSD -0x21e8c(%RIP),%YMM9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMULPD %YMM9,%YMM25,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM9,%YMM29,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMINPD %YMM7,%YMM23,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMINPD %YMM9,%YMM24,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	2	0.50	vect (50.0%)
VMULPD %YMM7,%YMM13,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
VMULPD %YMM9,%YMM11,%YMM9	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50	vect (50.0%)
JMP 232350 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x2b0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

512-bits vectorization

Workaround

Expensive FP math instructions/calls

Masked instructions

Details

Workaround

FMA

Workaround

Complex instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code