OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:208-216 [...]	Coverage (incl. loops): 3.49% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 208 - 216

--------------------------------------------------------------------------------

208: #pragma omp parallel for simd collapse(2)

209:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

210:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

211:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

212:         double post_mass_s = pre_mass_s + mass_flux_y(i, j) - mass_flux_y(i + 0, j + 1);

213:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 0, j + 1)) / post_mass_s;

214:         double advec_vol_s = pre_vol(i, j) + vol_flux_y(i, j) - vol_flux_y(i + 0, j + 1);

215:         density1(i, j) = post_mass_s / advec_vol_s;

216:         energy1(i, j) = post_ener_s;

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x233340 PUSH	%RBP

0x233341 MOV	%RSP,%RBP

0x233344 PUSH	%R15

0x233346 PUSH	%R14

0x233348 PUSH	%R13

0x23334a PUSH	%R12

0x23334c PUSH	%RBX

0x23334d SUB	$0xb8,%RSP

0x233354 MOV	(%RDX),%R12D

0x233357 MOV	(%RCX),%R15D

0x23335a INC	%R12D

0x23335d ADD	$0x2,%R15D

0x233361 SUB	%R12D,%R15D

0x233364 JLE	233a66

0x23336a MOV	(%R9),%R14D

0x23336d MOV	(%R8),%R13D

0x233370 INC	%R13D

0x233373 ADD	$0x2,%R14D

0x233377 CMP	%R13D,%R14D

0x23337a JLE	233a66

0x233380 SUB	%R13D,%R14D

0x233383 MOV	(%RDI),%ESI

0x233385 MOVQ	$0,-0x78(%RBP)

0x23338d MOVQ	$0x1,-0xd8(%RBP)

0x233398 MOVL	$0,-0x40(%RBP)

0x23339f IMUL	%R14,%R15

0x2333a3 DEC	%R15

0x2333a6 MOV	%R15,-0x38(%RBP)

0x2333aa SUB	$0x8,%RSP

0x2333ae LEA	-0x40(%RBP),%RCX

0x2333b2 LEA	-0xd8(%RBP),%RAX

0x2333b9 LEA	0x27738(%RIP),%RDI

0x2333c0 LEA	-0x78(%RBP),%R8

0x2333c4 LEA	-0x38(%RBP),%R9

0x2333c8 MOV	%ESI,-0x3c(%RBP)

0x2333cb MOV	$0x22,%EDX

0x2333d0 PUSH	$0x1

0x2333d2 PUSH	$0x1

0x2333d4 PUSH	%RAX

0x2333d5 CALL	259680 <@plt_start@+0x530>

0x2333da ADD	$0x20,%RSP

0x2333de MOV	-0x38(%RBP),%RAX

0x2333e2 MOV	-0x78(%RBP),%RCX

0x2333e6 CMP	%R15,%RAX

0x2333e9 CMOVL	%RAX,%R15

0x2333ed MOV	%R15,-0x38(%RBP)

0x2333f1 CMP	%R15,%RCX

0x2333f4 JG	233a54

0x2333fa MOV	0x10(%RBP),%RDI

0x2333fe MOV	0x18(%RBP),%R9

0x233402 MOV	0x20(%RBP),%R8

0x233406 MOV	0x30(%RBP),%RDX

0x23340a MOV	0x38(%RBP),%RAX

0x23340e MOV	0x28(%RBP),%RSI

0x233412 MOV	%R12,-0x70(%RBP)

0x233416 MOV	%R13D,-0x2c(%RBP)

0x23341a MOV	%R14,-0x68(%RBP)

0x23341e MOV	(%RDI),%R10

0x233421 MOV	(%R9),%R11

0x233424 MOV	0x10(%R9),%R9

0x233428 MOV	0x10(%RDI),%RDI

0x23342c MOV	0x10(%RDX),%RBX

0x233430 MOV	%R10,-0x60(%RBP)

0x233434 MOV	(%R8),%R10

0x233437 MOV	%R11,-0x58(%RBP)

0x23343b MOV	%R9,-0x48(%RBP)

0x23343f MOV	0x10(%R8),%R11

0x233443 MOV	(%RSI),%R8

0x233446 MOV	(%RDX),%R9

0x233449 MOV	(%RAX),%RDX

0x23344c MOV	0x10(%RSI),%RSI

0x233450 MOV	%R10,-0x50(%RBP)

0x233454 MOV	0x10(%RAX),%R10

0x233458 MOV	%R15,%RAX

0x23345b SUB	%RCX,%RAX

0x23345e MOV	%R8,-0xb0(%RBP)

0x233465 MOV	%RDX,-0xa8(%RBP)

0x23346c INC	%RAX

0x23346f CMP	$0x4,%RAX

0x233473 JB	233934

0x233479 VPBROADCASTD	%R12D,%XMM2

0x23347f MOV	-0x58(%RBP),%R12

0x233483 VPBROADCASTD	%R13D,%XMM3

0x233489 MOV	-0x60(%RBP),%R13

0x23348d VPBROADCASTQ	%RCX,%YMM0

0x233493 VPADDQ	-0x221bb(%RIP),%YMM0,%YMM0

0x23349b VPBROADCASTQ	-0x222d4(%RIP),%YMM12

0x2334a4 MOV	%RAX,-0x88(%RBP)

0x2334ab AND	$-0x4,%RAX

0x2334af VPBROADCASTQ	%R14,%YMM1

0x2334b5 VPBROADCASTQ	%R8,%YMM7

0x2334bb VPBROADCASTQ	%RDX,%YMM9

0x2334c1 VPCMPEQD	%XMM11,%XMM11,%XMM11

0x2334c6 ADD	%RAX,%RCX

0x2334c9 VEXTRACTI128	$0x1,%YMM1,%XMM10

0x2334cf MOV	%RAX,-0x80(%RBP)

0x2334d3 MOV	%RAX,%R8

0x2334d6 VPBROADCASTQ	%R12,%YMM5

0x2334dc MOV	-0x50(%RBP),%R12

0x2334e0 VPBROADCASTQ	%R13,%YMM4

0x2334e6 MOV	%R9,%R13

0x2334e9 MOV	-0x48(%RBP),%R9

0x2334ed VPBROADCASTQ	%R13,%YMM8

0x2334f3 MOV	%R13,-0x90(%RBP)

0x2334fa VPBROADCASTQ	%R12,%YMM6

(146) 0x233500 VEXTRACTI128	$0x1,%YMM0,%XMM13

(146) 0x233506 VPEXTRQ	$0x1,%XMM10,%R12

(146) 0x23350c VPEXTRQ	$0x1,%XMM13,%RAX

(146) 0x233512 CQTO

(146) 0x233514 IDIV	%R12

(146) 0x233517 VMOVQ	%XMM10,%R12

(146) 0x23351c VMOVQ	%RAX,%XMM14

(146) 0x233521 VMOVQ	%XMM13,%RAX

(146) 0x233526 CQTO

(146) 0x233528 IDIV	%R12

(146) 0x23352b VPEXTRQ	$0x1,%XMM1,%R12

(146) 0x233531 VMOVQ	%RAX,%XMM13

(146) 0x233536 VPEXTRQ	$0x1,%XMM0,%RAX

(146) 0x23353c CQTO

(146) 0x23353e VPUNPCKLQDQ	%XMM14,%XMM13,%XMM13

(146) 0x233543 IDIV	%R12

(146) 0x233546 VMOVQ	%XMM1,%R12

(146) 0x23354b VMOVQ	%RAX,%XMM14

(146) 0x233550 VMOVQ	%XMM0,%RAX

(146) 0x233555 CQTO

(146) 0x233557 IDIV	%R12

(146) 0x23355a ADD	$-0x4,%R8

(146) 0x23355e VMOVQ	%RAX,%XMM15

(146) 0x233563 VPUNPCKLQDQ	%XMM14,%XMM15,%XMM14

(146) 0x233568 VINSERTI128	$0x1,%XMM13,%YMM14,%YMM13

(146) 0x23356e VPMOVQD	%YMM13,%XMM14

(146) 0x233574 VPMULLQ	%YMM1,%YMM13,%YMM13

(146) 0x23357a VPSUBQ	%YMM13,%YMM0,%YMM13

(146) 0x23357f VPADDQ	%YMM0,%YMM12,%YMM0

(146) 0x233583 VPMOVQD	%YMM13,%XMM13

(146) 0x233589 VPADDD	%XMM14,%XMM2,%XMM17

(146) 0x23358f VPMOVSXDQ	%XMM17,%YMM15

(146) 0x233595 VPSUBD	%XMM11,%XMM17,%XMM17

(146) 0x23359b VPMULLQ	%YMM15,%YMM4,%YMM14

(146) 0x2335a1 VPADDD	%XMM3,%XMM13,%XMM13

(146) 0x2335a5 VPMOVSXDQ	%XMM13,%YMM13

(146) 0x2335aa VPADDQ	%YMM13,%YMM14,%YMM14

(146) 0x2335af VMOVQ	%XMM14,%RAX

(146) 0x2335b4 VPEXTRQ	$0x1,%XMM14,%RDX

(146) 0x2335ba VEXTRACTI128	$0x1,%YMM14,%XMM14

(146) 0x2335c0 VMOVQ	%XMM14,%R14

(146) 0x2335c5 VPEXTRQ	$0x1,%XMM14,%R12

(146) 0x2335cb VMOVSD	(%RDI,%RAX,8),%XMM16

(146) 0x2335d2 MOV	%RAX,-0xc0(%RBP)

(146) 0x2335d9 MOV	%RDX,-0xb8(%RBP)

(146) 0x2335e0 VMOVSD	(%RDI,%R14,8),%XMM14

(146) 0x2335e6 VMOVHPD	(%RDI,%RDX,8),%XMM16,%XMM16

(146) 0x2335ed MOV	%R12,-0xc8(%RBP)

(146) 0x2335f4 MOV	%R14,-0xd0(%RBP)

(146) 0x2335fb MOV	-0xc0(%RBP),%RDX

(146) 0x233602 VMOVHPD	(%RDI,%R12,8),%XMM14,%XMM14

(146) 0x233608 VINSERTF32X4	$0x1,%XMM14,%YMM16,%YMM14

(146) 0x23360f VPMULLQ	%YMM15,%YMM5,%YMM16

(146) 0x233615 VPADDQ	%YMM13,%YMM16,%YMM16

(146) 0x23361b VMOVQ	%XMM16,%RAX

(146) 0x233621 VPEXTRQ	$0x1,%XMM16,%R12

(146) 0x233628 VEXTRACTI32X4	$0x1,%YMM16,%XMM16

(146) 0x23362f VMOVQ	%XMM16,%R13

(146) 0x233635 VMOVSD	(%R9,%RAX,8),%XMM18

(146) 0x23363c VPEXTRQ	$0x1,%XMM16,%R14

(146) 0x233643 VMOVSD	(%R9,%R13,8),%XMM16

(146) 0x23364a VMOVHPD	(%R9,%R12,8),%XMM18,%XMM18

(146) 0x233651 VMOVHPD	(%R9,%R14,8),%XMM16,%XMM16

(146) 0x233658 VINSERTF32X4	$0x1,%XMM16,%YMM18,%YMM16

(146) 0x23365f VPMULLQ	%YMM15,%YMM6,%YMM18

(146) 0x233665 VMULPD	%YMM14,%YMM16,%YMM14

(146) 0x23366b VPADDQ	%YMM13,%YMM18,%YMM18

(146) 0x233671 VMOVQ	%XMM18,%RAX

(146) 0x233677 VPEXTRQ	$0x1,%XMM18,%R14

(146) 0x23367e VEXTRACTI32X4	$0x1,%YMM18,%XMM18

(146) 0x233685 VMOVQ	%XMM18,%R12

(146) 0x23368b VMOVSD	(%R11,%RAX,8),%XMM19

(146) 0x233692 VPEXTRQ	$0x1,%XMM18,%R13

(146) 0x233699 VMOVSD	(%R11,%R12,8),%XMM18

(146) 0x2336a0 VMOVHPD	(%R11,%R14,8),%XMM19,%XMM19

(146) 0x2336a7 VMOVHPD	(%R11,%R13,8),%XMM18,%XMM18

(146) 0x2336ae VINSERTF32X4	$0x1,%XMM18,%YMM19,%YMM18

(146) 0x2336b5 VADDPD	%YMM14,%YMM18,%YMM19

(146) 0x2336bb VPMOVSXDQ	%XMM17,%YMM18

(146) 0x2336c1 VPMULLQ	%YMM18,%YMM6,%YMM17

(146) 0x2336c7 VPADDQ	%YMM13,%YMM17,%YMM17

(146) 0x2336cd VMOVQ	%XMM17,%RAX

(146) 0x2336d3 VPEXTRQ	$0x1,%XMM17,%R14

(146) 0x2336da VEXTRACTI32X4	$0x1,%YMM17,%XMM17

(146) 0x2336e1 VMOVQ	%XMM17,%R12

(146) 0x2336e7 VMOVSD	(%R11,%RAX,8),%XMM20

(146) 0x2336ee VPEXTRQ	$0x1,%XMM17,%R13

(146) 0x2336f5 VMOVSD	(%R11,%R12,8),%XMM17

(146) 0x2336fc VMOVHPD	(%R11,%R14,8),%XMM20,%XMM20

(146) 0x233703 VMOVHPD	(%R11,%R13,8),%XMM17,%XMM17

(146) 0x23370a VINSERTF32X4	$0x1,%XMM17,%YMM20,%YMM17

(146) 0x233711 VPMULLQ	%YMM15,%YMM8,%YMM20

(146) 0x233717 VSUBPD	%YMM17,%YMM19,%YMM17

(146) 0x23371d VPMULLQ	%YMM15,%YMM7,%YMM19

(146) 0x233723 VPMULLQ	%YMM15,%YMM9,%YMM15

(146) 0x233729 VPADDQ	%YMM13,%YMM20,%YMM20

(146) 0x23372f VEXTRACTI32X4	$0x1,%YMM20,%XMM21

(146) 0x233736 VPEXTRQ	$0x1,%XMM20,%R14

(146) 0x23373d VMOVQ	%XMM21,%R12

(146) 0x233743 VPADDQ	%YMM13,%YMM15,%YMM15

(146) 0x233748 VPADDQ	%YMM13,%YMM19,%YMM19

(146) 0x23374e VMOVSD	(%RBX,%R12,8),%XMM22

(146) 0x233755 VPEXTRQ	$0x1,%XMM21,%R12

(146) 0x23375c VPEXTRQ	$0x1,%XMM19,%RAX

(146) 0x233763 VMOVQ	%XMM19,%R13

(146) 0x233769 VEXTRACTI32X4	$0x1,%YMM19,%XMM19

(146) 0x233770 VMOVHPD	(%RBX,%R12,8),%XMM22,%XMM21

(146) 0x233777 VPMULLQ	%YMM18,%YMM8,%YMM22

(146) 0x23377d VMOVQ	%XMM20,%R12

(146) 0x233783 VPMULLQ	%YMM18,%YMM9,%YMM18

(146) 0x233789 VMOVSD	(%RBX,%R12,8),%XMM20

(146) 0x233790 VMOVHPD	(%RBX,%R14,8),%XMM20,%XMM20

(146) 0x233797 VPADDQ	%YMM13,%YMM22,%YMM22

(146) 0x23379d VPADDQ	%YMM13,%YMM18,%YMM13

(146) 0x2337a3 VEXTRACTI32X4	$0x1,%YMM22,%XMM23

(146) 0x2337aa VMOVQ	%XMM22,%R14

(146) 0x2337b0 VEXTRACTI32X4	$0x1,%YMM13,%XMM18

(146) 0x2337b7 VMOVQ	%XMM23,%R12

(146) 0x2337bd VMOVSD	(%RBX,%R12,8),%XMM24

(146) 0x2337c4 VPEXTRQ	$0x1,%XMM23,%R12

(146) 0x2337cb VMOVHPD	(%RBX,%R12,8),%XMM24,%XMM23

(146) 0x2337d2 VEXTRACTI32X4	$0x1,%YMM15,%XMM24

(146) 0x2337d9 VPEXTRQ	$0x1,%XMM22,%R12

(146) 0x2337e0 VMOVSD	(%RBX,%R14,8),%XMM22

(146) 0x2337e7 VMOVQ	%XMM24,%R14

(146) 0x2337ed VMOVHPD	(%RBX,%R12,8),%XMM22,%XMM22

(146) 0x2337f4 VPEXTRQ	$0x1,%XMM24,%R12

(146) 0x2337fb VMOVSD	(%R10,%R14,8),%XMM24

(146) 0x233802 VMOVQ	%XMM15,%R14

(146) 0x233807 VMOVHPD	(%R10,%R12,8),%XMM24,%XMM24

(146) 0x23380e VPEXTRQ	$0x1,%XMM15,%R12

(146) 0x233814 VMOVSD	(%R10,%R14,8),%XMM15

(146) 0x23381a VMOVQ	%XMM18,%R14

(146) 0x233820 VMOVHPD	(%R10,%R12,8),%XMM15,%XMM15

(146) 0x233826 VPEXTRQ	$0x1,%XMM18,%R12

(146) 0x23382d VMOVSD	(%R10,%R14,8),%XMM18

(146) 0x233834 VMOVQ	%XMM13,%R14

(146) 0x233839 VMOVHPD	(%R10,%R12,8),%XMM18,%XMM18

(146) 0x233840 VPEXTRQ	$0x1,%XMM13,%R12

(146) 0x233846 VMOVSD	(%R10,%R14,8),%XMM13

(146) 0x23384c VMOVQ	%XMM19,%R14

(146) 0x233852 VMOVHPD	(%R10,%R12,8),%XMM13,%XMM13

(146) 0x233858 VPEXTRQ	$0x1,%XMM19,%R12

(146) 0x23385f VINSERTF32X4	$0x1,%XMM24,%YMM15,%YMM15

(146) 0x233866 VADDPD	%YMM16,%YMM15,%YMM15

(146) 0x23386c VINSERTF32X4	$0x1,%XMM18,%YMM13,%YMM13

(146) 0x233873 VMOVSD	(%RSI,%R14,8),%XMM16

(146) 0x23387a VMOVHPD	(%RSI,%R12,8),%XMM16,%XMM16

(146) 0x233881 VSUBPD	%YMM13,%YMM15,%YMM13

(146) 0x233886 VMOVSD	(%RSI,%R13,8),%XMM15

(146) 0x23388c VMOVHPD	(%RSI,%RAX,8),%XMM15,%XMM15

(146) 0x233891 VDIVPD	%YMM13,%YMM17,%YMM13

(146) 0x233897 VMOVLPD	%XMM13,(%RDI,%RDX,8)

(146) 0x23389c MOV	-0xb8(%RBP),%RDX

(146) 0x2338a3 VMOVHPD	%XMM13,(%RDI,%RDX,8)

(146) 0x2338a8 MOV	-0xd0(%RBP),%RDX

(146) 0x2338af VEXTRACTF128	$0x1,%YMM13,%XMM13

(146) 0x2338b5 VMOVLPD	%XMM13,(%RDI,%RDX,8)

(146) 0x2338ba MOV	-0xc8(%RBP),%RDX

(146) 0x2338c1 VMOVHPD	%XMM13,(%RDI,%RDX,8)

(146) 0x2338c6 VINSERTF32X4	$0x1,%XMM16,%YMM15,%YMM13

(146) 0x2338cd VINSERTF32X4	$0x1,%XMM21,%YMM20,%YMM16

(146) 0x2338d4 VFMADD231PD	%YMM13,%YMM14,%YMM16

(146) 0x2338da VINSERTF32X4	$0x1,%XMM23,%YMM22,%YMM13

(146) 0x2338e1 VSUBPD	%YMM13,%YMM16,%YMM13

(146) 0x2338e7 VDIVPD	%YMM17,%YMM13,%YMM13

(146) 0x2338ed VMOVLPD	%XMM13,(%RSI,%R13,8)

(146) 0x2338f3 VMOVHPD	%XMM13,(%RSI,%RAX,8)

(146) 0x2338f8 VEXTRACTF128	$0x1,%YMM13,%XMM13

(146) 0x2338fe VMOVLPD	%XMM13,(%RSI,%R14,8)

(146) 0x233904 VMOVHPD	%XMM13,(%RSI,%R12,8)

(146) 0x23390a JNE	233500

0x233910 MOV	-0x80(%RBP),%RAX

0x233914 MOV	-0x70(%RBP),%R12

0x233918 MOV	-0x2c(%RBP),%R13D

0x23391c MOV	-0x68(%RBP),%R14

0x233920 MOV	-0x90(%RBP),%R9

0x233927 CMP	%RAX,-0x88(%RBP)

0x23392e JE	233a54

0x233934 MOV	%R15,-0xa0(%RBP)

0x23393b MOV	%R11,-0x98(%RBP)

0x233942 NOPW	%CS:(%RAX,%RAX,1)

(145) 0x233950 MOV	%RCX,%RAX

(145) 0x233953 CQTO

(145) 0x233955 IDIV	%R14

(145) 0x233958 MOV	-0x48(%RBP),%R15

(145) 0x23395c ADD	%R13D,%EDX

(145) 0x23395f MOVSXD	%EDX,%R8

(145) 0x233962 MOV	-0x60(%RBP),%RDX

(145) 0x233966 LEA	(%R12,%RAX,1),%R14D

(145) 0x23396a LEA	0x1(%R12,%RAX,1),%EAX

(145) 0x23396f MOV	-0xb0(%RBP),%R12

(145) 0x233976 MOVSXD	%R14D,%R13

(145) 0x233979 MOV	-0x58(%RBP),%R14

(145) 0x23397d IMUL	%R13,%RDX

(145) 0x233981 CLTQ

(145) 0x233983 ADD	%R8,%RDX

(145) 0x233986 IMUL	%R13,%R12

(145) 0x23398a IMUL	%R13,%R14

(145) 0x23398e ADD	%R8,%R12

(145) 0x233991 ADD	%R8,%R14

(145) 0x233994 VMOVSD	(%RSI,%R12,8),%XMM3

(145) 0x23399a VMOVSD	(%R15,%R14,8),%XMM0

(145) 0x2339a0 MOV	%R9,%R15

(145) 0x2339a3 MOV	-0x50(%RBP),%R9

(145) 0x2339a7 VMULSD	(%RDI,%RDX,8),%XMM0,%XMM1

(145) 0x2339ac MOV	%R9,%R14

(145) 0x2339af IMUL	%R13,%R14

(145) 0x2339b3 ADD	%R8,%R14

(145) 0x2339b6 VADDSD	(%R11,%R14,8),%XMM1,%XMM2

(145) 0x2339bc MOV	%R9,%R14

(145) 0x2339bf IMUL	%RAX,%R14

(145) 0x2339c3 MOV	%R15,%R9

(145) 0x2339c6 MOV	-0xa0(%RBP),%R15

(145) 0x2339cd ADD	%R8,%R14

(145) 0x2339d0 VSUBSD	(%R11,%R14,8),%XMM2,%XMM2

(145) 0x2339d6 MOV	%RDI,%R11

(145) 0x2339d9 MOV	%RCX,%RDI

(145) 0x2339dc MOV	-0xa8(%RBP),%RCX

(145) 0x2339e3 MOV	%R9,%R14

(145) 0x2339e6 IMUL	%R13,%R14

(145) 0x2339ea ADD	%R8,%R14

(145) 0x2339ed VFMADD213SD	(%RBX,%R14,8),%XMM1,%XMM3

(145) 0x2339f3 MOV	%R9,%R14

(145) 0x2339f6 IMUL	%RAX,%R14

(145) 0x2339fa IMUL	%RCX,%R13

(145) 0x2339fe IMUL	%RCX,%RAX

(145) 0x233a02 LEA	0x1(%RDI),%RCX

(145) 0x233a06 ADD	%R8,%R14

(145) 0x233a09 ADD	%R8,%R13

(145) 0x233a0c ADD	%R8,%RAX

(145) 0x233a0f VSUBSD	(%RBX,%R14,8),%XMM3,%XMM1

(145) 0x233a15 MOV	-0x68(%RBP),%R14

(145) 0x233a19 VADDSD	(%R10,%R13,8),%XMM0,%XMM0

(145) 0x233a1f MOV	-0x2c(%RBP),%R13D

(145) 0x233a23 VSUBSD	(%R10,%RAX,8),%XMM0,%XMM0

(145) 0x233a29 VDIVSD	%XMM2,%XMM1,%XMM1

(145) 0x233a2d VDIVSD	%XMM0,%XMM2,%XMM0

(145) 0x233a31 VMOVSD	%XMM0,(%R11,%RDX,8)

(145) 0x233a37 VMOVSD	%XMM1,(%RSI,%R12,8)

(145) 0x233a3d MOV	-0x70(%RBP),%R12

(145) 0x233a41 CMP	%R15,%RDI

(145) 0x233a44 MOV	%R11,%RDI

(145) 0x233a47 MOV	-0x98(%RBP),%R11

(145) 0x233a4e JL	233950

0x233a54 MOV	-0x3c(%RBP),%ESI

0x233a57 LEA	0x270b2(%RIP),%RDI

0x233a5e VZEROUPPER

0x233a61 CALL	259690 <@plt_start@+0x540>

0x233a66 ADD	$0xb8,%RSP

0x233a6d POP	%RBX

0x233a6e POP	%R12

0x233a70 POP	%R13

0x233a72 POP	%R14

0x233a74 POP	%R15

0x233a76 POP	%RBP

0x233a77 RET

0x233a78 NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.38 to 6.00 cycles (2.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
12% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
14% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
VPBROADCASTQ: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 300 bytes. The binary function is storing 148 bytes.

General properties

nb instructions	128
nb uops	139
loop length	556
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	9
used zmm registers	0
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.38 cycles
front end	17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.33	6.33	6.33	6.33	6.33	6.33	15.00	15.00	15.00	15.00	1.00	6.00	6.00	1.00	0.00	0.00
cycles	6.33	6.33	6.33	6.33	6.33	6.33	15.00	15.00	15.00	15.00	1.00	6.00	6.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.38
Dispatch	15.00
Overall L1	17.38

Vectorization ratios

all	6%
load	5%
store	0%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	11%
load	12%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.38 cycles. At this rate:

6% of peak load performance is reached (17.27 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.52 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.38 to 15.00 cycles (1.16x speedup).

ASM code

In the binary file, the address of the function is: 233340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R12D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 233a66 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x726>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 233a66 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x726>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R14,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0xd8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x27738(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x78(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 233a54 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x714>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R12,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R9),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R10,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RSI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 233934 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x5f4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTD %R12D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x58(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTD %R13D,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x60(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x221bb(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x222d4(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R14,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R8,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPCMPEQD %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %R12,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x50(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %R13,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x48(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %R13,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R13,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %R12,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x2c(%RBP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV -0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x90(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %RAX,-0x88(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 233a54 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x714>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x270b2(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_cell.cpp:208-216
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208-216
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.38 to 6.00 cycles (2.90x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
12% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
14% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:208

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
VPBROADCASTQ: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:209

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 300 bytes. The binary function is storing 148 bytes.

General properties

nb instructions	128
nb uops	139
loop length	556
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	9
used zmm registers	0
nb stack references	25

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.38 cycles
front end	17.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.33	6.33	6.33	6.33	6.33	6.33	15.00	15.00	15.00	15.00	1.00	6.00	6.00	1.00	0.00	0.00
cycles	6.33	6.33	6.33	6.33	6.33	6.33	15.00	15.00	15.00	15.00	1.00	6.00	6.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.38
Dispatch	15.00
Overall L1	17.38

Vectorization ratios

all	6%
load	5%
store	0%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	11%
load	12%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.38 cycles. At this rate:

6% of peak load performance is reached (17.27 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (8.52 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 233340

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R12D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 233a66 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x726>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 233a66 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x726>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R13D,%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xd8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R14,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0xd8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x27738(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x78(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 233a54 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x714>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R12,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R14,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R9),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R10,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R8),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RSI),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R10,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0xb0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDX,-0xa8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 233934 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x5f4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTD %R12D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x58(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTD %R13D,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x60(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x221bb(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x222d4(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R14,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R8,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPCMPEQD %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %R12,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x50(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %R13,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV -0x48(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %R13,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R13,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %R12,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x2c(%RBP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV -0x68(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x90(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %RAX,-0x88(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 233a54 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.14+0x714>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %R15,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R11,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x270b2(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0xb8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.49	1.30
○Loop 146 - advec_cell.cpp:209-216 - exec	3.49	1.30
○Loop 145 - advec_cell.cpp:209-216 - exec	0.00	0.00

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Execution units bottlenecks

512-bits vectorization

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code