OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:157-202 [...]	Coverage (incl. loops): 3.51% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 157 - 202

--------------------------------------------------------------------------------

157: #pragma omp parallel for simd collapse(2)

158:     for (int j = (y_min + 1); j < (y_max + 2 + 2); j++) {

159:       for (int i = (x_min + 1); i < (x_max + 2); i++)

160:         ({

161:           int upwind, donor, downwind, dif;

162:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

163:           if (vol_flux_y(i, j) > 0.0) {

164:             upwind = j - 2;

165:             donor = j - 1;

166:             downwind = j;

167:             dif = donor;

168:           } else {

169:             upwind = std::min(j + 1, y_max + 2);

170:             donor = j;

171:             downwind = j - 1;

172:             dif = upwind;

173:           }

174:           sigmat = std::fabs(vol_flux_y(i, j)) / pre_vol(i, donor);

175:           sigma3 = (1.0 + sigmat) * (vertexdy[j] / vertexdy[dif]);

176:           sigma4 = 2.0 - sigmat;

177:           sigmav = sigmat;

178:           diffuw = density1(i, donor) - density1(i, upwind);

179:           diffdw = density1(i, downwind) - density1(i, donor);

180:           wind = 1.0;

181:           if (diffdw <= 0.0) wind = -1.0;

182:           if (diffuw * diffdw > 0.0) {

183:             limiter = (1.0 - sigmav) * wind *

184:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

185:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

186:           } else {

187:             limiter = 0.0;

188:           }

189:           mass_flux_y(i, j) = vol_flux_y(i, j) * (density1(i, donor) + limiter);

190:           sigmam = std::fabs(mass_flux_y(i, j)) / (density1(i, donor) * pre_vol(i, donor));

191:           diffuw = energy1(i, donor) - energy1(i, upwind);

192:           diffdw = energy1(i, downwind) - energy1(i, donor);

193:           wind = 1.0;

194:           if (diffdw <= 0.0) wind = -1.0;

195:           if (diffuw * diffdw > 0.0) {

196:             limiter = (1.0 - sigmam) * wind *

197:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

198:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

199:           } else {

200:             limiter = 0.0;

201:           }

202:           ener_flux(i, j) = mass_flux_y(i, j) * (energy1(i, donor) + limiter);

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x2320a0 PUSH	%RBP

0x2320a1 MOV	%RSP,%RBP

0x2320a4 PUSH	%R15

0x2320a6 PUSH	%R14

0x2320a8 PUSH	%R13

0x2320aa PUSH	%R12

0x2320ac PUSH	%RBX

0x2320ad AND	$-0x20,%RSP

0x2320b1 SUB	$0x320,%RSP

0x2320b8 MOV	(%RCX),%EBX

0x2320ba MOV	(%RDX),%EAX

0x2320bc MOV	%RAX,0x8(%RSP)

0x2320c1 INC	%EAX

0x2320c3 ADD	$0x4,%EBX

0x2320c6 SUB	%EAX,%EBX

0x2320c8 MOV	%RAX,0x58(%RSP)

0x2320cd JLE	2330c6

0x2320d3 MOV	(%R9),%EAX

0x2320d6 MOV	(%R8),%R13D

0x2320d9 INC	%R13D

0x2320dc ADD	$0x2,%EAX

0x2320df CMP	%R13D,%EAX

0x2320e2 JLE	2330c6

0x2320e8 SUB	%R13D,%EAX

0x2320eb MOV	(%RDI),%ESI

0x2320ed MOV	%RCX,%R14

0x2320f0 MOVQ	$0,0x70(%RSP)

0x2320f9 MOVQ	$0x1,0x128(%RSP)

0x232105 MOVL	$0,0x2c(%RSP)

0x23210d IMUL	%RAX,%RBX

0x232111 MOV	%RAX,0x48(%RSP)

0x232116 DEC	%RBX

0x232119 MOV	%RBX,0x18(%RSP)

0x23211e SUB	$0x8,%RSP

0x232122 LEA	0x130(%RSP),%RAX

0x23212a LEA	0x2897f(%RIP),%RDI

0x232131 LEA	0x34(%RSP),%RCX

0x232136 LEA	0x78(%RSP),%R8

0x23213b LEA	0x20(%RSP),%R9

0x232140 MOV	%ESI,0x2c(%RSP)

0x232144 MOV	$0x22,%EDX

0x232149 PUSH	$0x1

0x23214b PUSH	$0x1

0x23214d PUSH	%RAX

0x23214e CALL	259680 <@plt_start@+0x530>

0x232153 ADD	$0x20,%RSP

0x232157 MOV	0x18(%RSP),%RAX

0x23215c MOV	0x70(%RSP),%R10

0x232161 CMP	%RBX,%RAX

0x232164 CMOVL	%RAX,%RBX

0x232168 MOV	%RBX,0x18(%RSP)

0x23216d MOV	%RBX,0x50(%RSP)

0x232172 CMP	%RBX,%R10

0x232175 JG	2330b3

0x23217b MOV	0x10(%RBP),%R8

0x23217f MOV	0x18(%RBP),%RCX

0x232183 MOV	0x38(%RBP),%RDX

0x232187 MOV	0x28(%RBP),%RSI

0x23218b MOV	0x20(%RBP),%RDI

0x23218f MOV	0x48(%RBP),%RAX

0x232193 MOV	0x40(%RBP),%RBX

0x232197 MOV	%R13D,0x4(%RSP)

0x23219c MOV	(%R8),%R9

0x23219f MOV	0x10(%R8),%R8

0x2321a3 MOV	0x10(%RCX),%R11

0x2321a7 MOV	(%RAX),%R15

0x2321aa MOV	0x10(%RAX),%R12

0x2321ae MOV	0x50(%RSP),%RAX

0x2321b3 MOV	%R9,0x40(%RSP)

0x2321b8 MOV	(%RCX),%R9

0x2321bb MOV	%R8,0x68(%RSP)

0x2321c0 MOV	(%R14),%R8D

0x2321c3 MOV	0x8(%RDI),%R14

0x2321c7 MOV	(%RSI),%RCX

0x2321ca MOV	0x10(%RSI),%RDI

0x2321ce MOV	(%RDX),%RSI

0x2321d1 MOV	0x10(%RDX),%RDX

0x2321d5 SUB	%R10,%RAX

0x2321d8 MOV	%R15,0x88(%RSP)

0x2321e0 INC	%RAX

0x2321e3 MOV	%RDX,0x60(%RSP)

0x2321e8 MOV	(%RBX),%RDX

0x2321eb MOV	0x10(%RBX),%RBX

0x2321ef ADD	$0x2,%R8D

0x2321f3 MOV	%RCX,0x38(%RSP)

0x2321f8 MOV	%R9,0x30(%RSP)

0x2321fd MOV	%RSI,0x98(%RSP)

0x232205 MOV	%R8D,0x28(%RSP)

0x23220a MOV	%RDX,0x90(%RSP)

0x232212 CMP	$0x8,%RAX

0x232216 JB	2330d5

0x23221c MOV	%RAX,%RCX

0x23221f MOV	%RAX,0x80(%RSP)

0x232227 MOV	0x48(%RSP),%RAX

0x23222c VPBROADCASTQ	%RSI,%YMM3

0x232232 AND	$-0x8,%RCX

0x232236 VPBROADCASTQ	%R10,%YMM0

0x23223c VPBROADCASTQ	%R9,%YMM4

0x232242 VPADDQ	-0x20f6a(%RIP),%YMM0,%YMM0

0x23224a VBROADCASTSD	-0x210f3(%RIP),%YMM15

0x232253 VBROADCASTSD	-0x21105(%RIP),%YMM16

0x23225d VPBROADCASTQ	%RDX,%YMM10

0x232263 VXORPD	%XMM14,%XMM14,%XMM14

0x232268 VMOVDQA	%YMM3,0x240(%RSP)

0x232271 VBROADCASTSD	-0x210aa(%RIP),%YMM3

0x23227a ADD	%RCX,%R10

0x23227d VMOVDQA	%YMM4,0x260(%RSP)

0x232286 VPBROADCASTQ	%R15,%YMM4

0x23228c MOV	%RCX,0x78(%RSP)

0x232291 MOV	%R10,0x10(%RSP)

0x232296 MOV	0x40(%RSP),%R10

0x23229b VMOVDQA	%YMM4,0x220(%RSP)

0x2322a4 VPBROADCASTQ	-0x211a5(%RIP),%YMM4

0x2322ad VPBROADCASTQ	%RAX,%YMM1

0x2322b3 MOV	0x58(%RSP),%RAX

0x2322b8 VEXTRACTI128	$0x1,%YMM1,0x140(%RSP)

0x2322c3 VMOVAPS	%YMM3,0x200(%RSP)

0x2322cc VBROADCASTSD	-0x211ed(%RIP),%YMM3

0x2322d5 VPBROADCASTD	%EAX,%XMM2

0x2322db MOV	0x8(%RSP),%RAX

0x2322e0 VMOVDQA	%XMM2,0x170(%RSP)

0x2322e9 VPBROADCASTD	%R13D,%XMM2

0x2322ef VMOVDQA	%YMM4,0x1e0(%RSP)

0x2322f8 VMOVDQA	%XMM2,0x160(%RSP)

0x232301 VPBROADCASTQ	%R10,%YMM2

0x232307 VMOVDQA	%YMM2,0x280(%RSP)

0x232310 VPBROADCASTD	%R8D,%XMM2

0x232316 VMOVDQA	%XMM2,0x130(%RSP)

0x23231f VPBROADCASTD	%EAX,%XMM2

0x232325 MOV	0x38(%RSP),%RAX

0x23232a VMOVDQA	%XMM2,0x150(%RSP)

0x232333 VMOVAPD	%YMM3,0x1c0(%RSP)

0x23233c VPBROADCASTQ	%RAX,%YMM8

0x232342 JMP	232432

0x232347 NOPW	(%RAX,%RAX,1)

(144) 0x232350 VCMPPD	$0x1,%YMM4,%YMM14,%YMM4

(144) 0x232355 VCMPPD	$0x1,%YMM6,%YMM14,%YMM6

(144) 0x23235a VPADDQ	0x1c0(%RSP),%YMM0,%YMM0

(144) 0x232363 VANDPD	%YMM4,%YMM15,%YMM4

(144) 0x232367 VANDPD	%YMM6,%YMM15,%YMM6

(144) 0x23236b VPCMPEQQ	%YMM15,%YMM4,%K2

(144) 0x232371 VPCMPEQQ	%YMM15,%YMM6,%K1

(144) 0x232377 VADDPD	%YMM9,%YMM3,%YMM3{%K2}

(144) 0x23237d VADDPD	%YMM7,%YMM2,%YMM2{%K1}

(144) 0x232383 VMULPD	%YMM5,%YMM3,%YMM3

(144) 0x232387 VMOVDQA	0x220(%RSP),%YMM5

(144) 0x232390 VMULPD	%YMM2,%YMM12,%YMM2

(144) 0x232394 VPMULLQ	%YMM21,%YMM5,%YMM4

(144) 0x23239a VPMULLQ	%YMM22,%YMM5,%YMM5

(144) 0x2323a0 VPADDQ	%YMM19,%YMM4,%YMM4

(144) 0x2323a6 VPADDQ	%YMM20,%YMM5,%YMM5

(144) 0x2323ac VMOVQ	%XMM4,%RCX

(144) 0x2323b1 VPEXTRQ	$0x1,%XMM4,%RAX

(144) 0x2323b7 VEXTRACTI128	$0x1,%YMM4,%XMM4

(144) 0x2323bd VMOVQ	%XMM5,%R8

(144) 0x2323c2 VPEXTRQ	$0x1,%XMM5,%R9

(144) 0x2323c8 VMOVLPD	%XMM2,(%R12,%RCX,8)

(144) 0x2323ce MOV	0x120(%RSP),%RCX

(144) 0x2323d6 VMOVHPD	%XMM2,(%R12,%RAX,8)

(144) 0x2323dc VEXTRACTF128	$0x1,%YMM2,%XMM2

(144) 0x2323e2 VMOVQ	%XMM4,%RDX

(144) 0x2323e7 VPEXTRQ	$0x1,%XMM4,%RSI

(144) 0x2323ed VEXTRACTI128	$0x1,%YMM5,%XMM4

(144) 0x2323f3 VMOVQ	%XMM4,%R10

(144) 0x2323f8 VPEXTRQ	$0x1,%XMM4,%R13

(144) 0x2323fe VMOVLPD	%XMM2,(%R12,%RDX,8)

(144) 0x232404 VMOVHPD	%XMM2,(%R12,%RSI,8)

(144) 0x23240a VEXTRACTF128	$0x1,%YMM3,%XMM2

(144) 0x232410 VMOVLPD	%XMM3,(%R12,%R8,8)

(144) 0x232416 VMOVHPD	%XMM3,(%R12,%R9,8)

(144) 0x23241c VMOVLPD	%XMM2,(%R12,%R10,8)

(144) 0x232422 VMOVHPD	%XMM2,(%R12,%R13,8)

(144) 0x232428 ADD	$-0x8,%RCX

(144) 0x23242c JE	23309a

(144) 0x232432 VMOVDQA	0x140(%RSP),%XMM5

(144) 0x23243b VEXTRACTI128	$0x1,%YMM0,%XMM2

(144) 0x232441 MOV	%RCX,0x120(%RSP)

(144) 0x232449 VPADDQ	0x200(%RSP),%YMM0,%YMM3

(144) 0x232452 VPEXTRQ	$0x1,%XMM1,%R9

(144) 0x232458 VPEXTRQ	$0x1,%XMM2,%RAX

(144) 0x23245e CQTO

(144) 0x232460 VPEXTRQ	$0x1,%XMM5,%RCX

(144) 0x232466 VMOVQ	%XMM5,%RSI

(144) 0x23246b IDIV	%RCX

(144) 0x23246e VMOVQ	%RAX,%XMM4

(144) 0x232473 VMOVQ	%XMM2,%RAX

(144) 0x232478 CQTO

(144) 0x23247a IDIV	%RSI

(144) 0x23247d VMOVQ	%RAX,%XMM2

(144) 0x232482 VPEXTRQ	$0x1,%XMM0,%RAX

(144) 0x232488 CQTO

(144) 0x23248a VPUNPCKLQDQ	%XMM4,%XMM2,%XMM2

(144) 0x23248e IDIV	%R9

(144) 0x232491 VMOVQ	%XMM1,%R9

(144) 0x232496 VMOVQ	%RAX,%XMM4

(144) 0x23249b VMOVQ	%XMM0,%RAX

(144) 0x2324a0 CQTO

(144) 0x2324a2 IDIV	%R9

(144) 0x2324a5 VMOVQ	%RAX,%XMM5

(144) 0x2324aa VPUNPCKLQDQ	%XMM4,%XMM5,%XMM4

(144) 0x2324ae VEXTRACTI128	$0x1,%YMM3,%XMM5

(144) 0x2324b4 VPEXTRQ	$0x1,%XMM5,%RAX

(144) 0x2324ba VINSERTI128	$0x1,%XMM2,%YMM4,%YMM4

(144) 0x2324c0 CQTO

(144) 0x2324c2 IDIV	%RCX

(144) 0x2324c5 VPEXTRQ	$0x1,%XMM1,%RCX

(144) 0x2324cb VMOVQ	%RAX,%XMM2

(144) 0x2324d0 VMOVQ	%XMM5,%RAX

(144) 0x2324d5 CQTO

(144) 0x2324d7 IDIV	%RSI

(144) 0x2324da VMOVQ	%RAX,%XMM5

(144) 0x2324df VPEXTRQ	$0x1,%XMM3,%RAX

(144) 0x2324e5 CQTO

(144) 0x2324e7 VPUNPCKLQDQ	%XMM2,%XMM5,%XMM2

(144) 0x2324eb IDIV	%RCX

(144) 0x2324ee VMOVQ	%XMM1,%RCX

(144) 0x2324f3 MOV	%RAX,%RSI

(144) 0x2324f6 VMOVQ	%XMM3,%RAX

(144) 0x2324fb VMOVQ	%RSI,%XMM5

(144) 0x232500 CQTO

(144) 0x232502 IDIV	%RCX

(144) 0x232505 VMOVDQA	0x170(%RSP),%XMM9

(144) 0x23250e MOV	0x68(%RSP),%R15

(144) 0x232513 VMOVQ	%RAX,%XMM6

(144) 0x232518 VPUNPCKLQDQ	%XMM5,%XMM6,%XMM5

(144) 0x23251c VPMOVQD	%YMM4,%XMM6

(144) 0x232522 VPMULLQ	%YMM1,%YMM4,%YMM4

(144) 0x232528 VINSERTI128	$0x1,%XMM2,%YMM5,%YMM5

(144) 0x23252e VPMOVQD	%YMM5,%XMM7

(144) 0x232534 VPMULLQ	%YMM1,%YMM5,%YMM5

(144) 0x23253a VPSUBQ	%YMM4,%YMM0,%YMM4

(144) 0x23253e VPADDD	%XMM6,%XMM9,%XMM2

(144) 0x232542 VPMOVQD	%YMM4,%XMM4

(144) 0x232548 VPSUBQ	%YMM5,%YMM3,%YMM3

(144) 0x23254c VPMOVSXDQ	%XMM2,%YMM21

(144) 0x232552 VPMOVQD	%YMM3,%XMM5

(144) 0x232558 VPADDD	%XMM7,%XMM9,%XMM3

(144) 0x23255c VMOVDQA	0x160(%RSP),%XMM9

(144) 0x232565 VPMOVSXDQ	%XMM3,%YMM22

(144) 0x23256b VPADDD	%XMM5,%XMM9,%XMM5

(144) 0x23256f VPADDD	%XMM4,%XMM9,%XMM4

(144) 0x232573 VMOVDQA	0x150(%RSP),%XMM9

(144) 0x23257c VPMOVSXDQ	%XMM5,%YMM20

(144) 0x232582 VMOVDQA	0x280(%RSP),%YMM5

(144) 0x23258b VPMOVSXDQ	%XMM4,%YMM19

(144) 0x232591 VPMULLQ	%YMM21,%YMM5,%YMM4

(144) 0x232597 VPMULLQ	%YMM22,%YMM5,%YMM5

(144) 0x23259d VPADDQ	%YMM19,%YMM4,%YMM4

(144) 0x2325a3 VPADDQ	%YMM20,%YMM5,%YMM5

(144) 0x2325a9 VMOVQ	%XMM4,%RAX

(144) 0x2325ae VPEXTRQ	$0x1,%XMM4,%RCX

(144) 0x2325b4 VEXTRACTI128	$0x1,%YMM4,%XMM4

(144) 0x2325ba VMOVQ	%XMM5,%R9

(144) 0x2325bf VPEXTRQ	$0x1,%XMM5,%R10

(144) 0x2325c5 VMOVQ	%XMM4,%RDX

(144) 0x2325ca VPEXTRQ	$0x1,%XMM4,%RSI

(144) 0x2325d0 VEXTRACTI128	$0x1,%YMM5,%XMM4

(144) 0x2325d6 VMOVSD	(%R15,%RAX,8),%XMM5

(144) 0x2325dc VPEXTRQ	$0x1,%XMM4,%R13

(144) 0x2325e2 VMOVQ	%XMM4,%R8

(144) 0x2325e7 VMOVSD	(%R15,%RDX,8),%XMM4

(144) 0x2325ed VMOVHPD	(%R15,%RCX,8),%XMM5,%XMM5

(144) 0x2325f3 VMOVHPD	(%R15,%RSI,8),%XMM4,%XMM4

(144) 0x2325f9 VINSERTF128	$0x1,%XMM4,%YMM5,%YMM12

(144) 0x2325ff VMOVSD	(%R15,%R8,8),%XMM4

(144) 0x232605 VMOVSD	(%R15,%R9,8),%XMM5

(144) 0x23260b VMOVHPD	(%R15,%R13,8),%XMM4,%XMM4

(144) 0x232611 VMOVHPD	(%R15,%R10,8),%XMM5,%XMM5

(144) 0x232617 VCMPPD	$0x1,%YMM12,%YMM14,%K0

(144) 0x23261e VINSERTF128	$0x1,%XMM4,%YMM5,%YMM5

(144) 0x232624 VPADDD	%XMM6,%XMM9,%XMM4

(144) 0x232628 VPADDD	%XMM7,%XMM9,%XMM6

(144) 0x23262c VCMPPD	$0x1,%YMM5,%YMM14,%K1

(144) 0x232633 KSHIFTLB	$0x4,%K1,%K1

(144) 0x232639 KORB	%K1,%K0,%K0

(144) 0x23263d KORTESTB	%K0,%K0

(144) 0x232641 JB	23267d

(144) 0x232643 VMOVDQA	0x130(%RSP),%XMM11

(144) 0x23264c VPCMPEQD	%XMM9,%XMM9,%XMM9

(144) 0x232651 VPMOVSXDQ	%XMM4,%YMM23

(144) 0x232657 VPMOVSXDQ	%XMM6,%YMM24

(144) 0x23265d VPSUBD	%XMM9,%XMM2,%XMM7

(144) 0x232662 VPSUBD	%XMM9,%XMM3,%XMM9

(144) 0x232667 VPMINSD	%XMM7,%XMM11,%XMM7

(144) 0x23266c VPMINSD	%XMM9,%XMM11,%XMM9

(144) 0x232671 VPMOVSXDQ	%XMM7,%YMM26

(144) 0x232677 VPMOVSXDQ	%XMM9,%YMM25

(144) 0x23267d VCMPPD	$0x1,%YMM5,%YMM14,%YMM9

(144) 0x232682 VCMPPD	$0x1,%YMM12,%YMM14,%YMM7

(144) 0x232688 VANDPD	%YMM15,%YMM9,%YMM9

(144) 0x23268d VANDPD	%YMM7,%YMM15,%YMM7

(144) 0x232691 VPCMPEQQ	%YMM15,%YMM9,%K2

(144) 0x232697 VPCMPEQQ	%YMM15,%YMM7,%K1

(144) 0x23269d KSHIFTLB	$0x4,%K2,%K0

(144) 0x2326a3 KORB	%K0,%K1,%K0

(144) 0x2326a7 KORTESTB	%K0,%K0

(144) 0x2326ab JE	2326d2

(144) 0x2326ad VPBROADCASTD	-0x2faa2(%RIP),%XMM7

(144) 0x2326b6 VPMOVSXDQ	%XMM6,%YMM9

(144) 0x2326bb VPADDD	%XMM7,%XMM2,%XMM2

(144) 0x2326bf VPADDD	%XMM7,%XMM3,%XMM3

(144) 0x2326c3 VPMOVSXDQ	%XMM4,%YMM7

(144) 0x2326c8 VPMOVSXDQ	%XMM2,%YMM11

(144) 0x2326cd VPMOVSXDQ	%XMM3,%YMM13

(144) 0x2326d2 VMOVDQA	0x260(%RSP),%YMM6

(144) 0x2326db VPBLENDMQ	%YMM7,%YMM21,%YMM28{%K1}

(144) 0x2326e1 VPBLENDMQ	%YMM9,%YMM22,%YMM18{%K2}

(144) 0x2326e7 VANDPD	%YMM16,%YMM12,%YMM2

(144) 0x2326ed VANDPD	%YMM16,%YMM5,%YMM3

(144) 0x2326f3 VPBLENDMQ	%YMM11,%YMM26,%YMM17{%K1}

(144) 0x2326f9 VMOVDQA64	%YMM7,%YMM26{%K1}

(144) 0x2326ff VPBLENDMQ	%YMM13,%YMM25,%YMM13{%K2}

(144) 0x232705 VMOVDQA64	%YMM9,%YMM25{%K2}

(144) 0x23270b VEXTRACTI32X4	$0x1,%YMM25,%XMM9

(144) 0x232712 VMOVDQA64	%YMM21,%YMM23{%K1}

(144) 0x232718 VMOVDQA64	%YMM22,%YMM24{%K2}

(144) 0x23271e VMOVDQA64	%YMM17,0x2e0(%RSP)

(144) 0x232726 VMOVDQA	%YMM13,0x2c0(%RSP)

(144) 0x23272f VPMULLQ	%YMM6,%YMM28,%YMM4

(144) 0x232735 VPMULLQ	%YMM6,%YMM18,%YMM6

(144) 0x23273b VPADDQ	%YMM19,%YMM4,%YMM4

(144) 0x232741 VPADDQ	%YMM20,%YMM6,%YMM6

(144) 0x232747 VMOVQ	%XMM4,%RDX

(144) 0x23274c VPEXTRQ	$0x1,%XMM4,%RSI

(144) 0x232752 VEXTRACTI128	$0x1,%YMM4,%XMM4

(144) 0x232758 VMOVQ	%XMM6,%RAX

(144) 0x23275d VPEXTRQ	$0x1,%XMM6,%RCX

(144) 0x232763 VMOVQ	%XMM4,%R10

(144) 0x232768 VPEXTRQ	$0x1,%XMM4,%R15

(144) 0x23276e VEXTRACTI128	$0x1,%YMM6,%XMM4

(144) 0x232774 VMOVSD	(%R11,%RDX,8),%XMM6

(144) 0x23277a MOV	%RDX,0x108(%RSP)

(144) 0x232782 MOV	%RAX,0x118(%RSP)

(144) 0x23278a MOV	%RSI,0x100(%RSP)

(144) 0x232792 MOV	%RCX,0x110(%RSP)

(144) 0x23279a VPEXTRQ	$0x1,%XMM4,%R8

(144) 0x2327a0 VMOVQ	%XMM4,%R9

(144) 0x2327a5 VMOVSD	(%R11,%R10,8),%XMM4

(144) 0x2327ab VMOVHPD	(%R11,%RSI,8),%XMM6,%XMM6

(144) 0x2327b1 MOV	%R10,0xe8(%RSP)

(144) 0x2327b9 MOV	%R15,0xe0(%RSP)

(144) 0x2327c1 VMOVHPD	(%R11,%R15,8),%XMM4,%XMM4

(144) 0x2327c7 MOV	%R8,0xf8(%RSP)

(144) 0x2327cf MOV	%R9,0xf0(%RSP)

(144) 0x2327d7 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

(144) 0x2327dd VMOVSD	(%R11,%RAX,8),%XMM6

(144) 0x2327e3 VMOVQ	%XMM21,%RAX

(144) 0x2327e9 VMOVHPD	(%R11,%RCX,8),%XMM6,%XMM6

(144) 0x2327ef VPEXTRQ	$0x1,%XMM21,%RCX

(144) 0x2327f6 VMOVSD	(%R14,%RAX,8),%XMM7

(144) 0x2327fc VDIVPD	%YMM4,%YMM2,%YMM2

(144) 0x232800 VMOVSD	(%R11,%R9,8),%XMM4

(144) 0x232806 VMOVHPD	(%R11,%R8,8),%XMM4,%XMM4

(144) 0x23280c VMOVQ	%XMM22,%R8

(144) 0x232812 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

(144) 0x232818 VEXTRACTI32X4	$0x1,%YMM22,%XMM6

(144) 0x23281f VPEXTRQ	$0x1,%XMM6,%RAX

(144) 0x232825 VDIVPD	%YMM4,%YMM3,%YMM3

(144) 0x232829 VEXTRACTI32X4	$0x1,%YMM21,%XMM4

(144) 0x232830 VMOVQ	%XMM4,%RDX

(144) 0x232835 VPEXTRQ	$0x1,%XMM4,%RSI

(144) 0x23283b VMOVSD	(%R14,%RDX,8),%XMM4

(144) 0x232841 VPEXTRQ	$0x1,%XMM22,%RDX

(144) 0x232848 VMOVHPD	(%R14,%RSI,8),%XMM4,%XMM4

(144) 0x23284e VMOVQ	%XMM6,%RSI

(144) 0x232853 VMOVHPD	(%R14,%RCX,8),%XMM7,%XMM6

(144) 0x232859 VMOVSD	(%R14,%R8,8),%XMM7

(144) 0x23285f VPEXTRQ	$0x1,%XMM26,%RCX

(144) 0x232866 VMOVQ	%XMM25,%R8

(144) 0x23286c VMOVHPD	(%R14,%RDX,8),%XMM7,%XMM7

(144) 0x232872 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

(144) 0x232878 VMOVSD	(%R14,%RSI,8),%XMM6

(144) 0x23287e VMOVHPD	(%R14,%RAX,8),%XMM6,%XMM6

(144) 0x232884 VMOVQ	%XMM26,%RAX

(144) 0x23288a VMOVSD	(%R14,%RAX,8),%XMM11

(144) 0x232890 VPEXTRQ	$0x1,%XMM9,%RAX

(144) 0x232896 VFMADD213PD	%YMM4,%YMM2,%YMM4

(144) 0x23289b VINSERTF128	$0x1,%XMM6,%YMM7,%YMM6

(144) 0x2328a1 VEXTRACTI32X4	$0x1,%YMM26,%XMM7

(144) 0x2328a8 VMOVQ	%XMM7,%RDX

(144) 0x2328ad VPEXTRQ	$0x1,%XMM7,%RSI

(144) 0x2328b3 VMOVSD	(%R14,%RDX,8),%XMM7

(144) 0x2328b9 VPEXTRQ	$0x1,%XMM25,%RDX

(144) 0x2328c0 VFMADD213PD	%YMM6,%YMM3,%YMM6

(144) 0x2328c5 VMOVAPD	0x1e0(%RSP),%YMM25

(144) 0x2328cd VMOVHPD	(%R14,%RSI,8),%XMM7,%XMM7

(144) 0x2328d3 VMOVQ	%XMM9,%RSI

(144) 0x2328d8 VMOVHPD	(%R14,%RCX,8),%XMM11,%XMM9

(144) 0x2328de VMOVSD	(%R14,%R8,8),%XMM11

(144) 0x2328e4 VMOVHPD	(%R14,%RDX,8),%XMM11,%XMM11

(144) 0x2328ea VINSERTF128	$0x1,%XMM7,%YMM9,%YMM7

(144) 0x2328f0 VMOVSD	(%R14,%RSI,8),%XMM9

(144) 0x2328f6 VMOVHPD	(%R14,%RAX,8),%XMM9,%XMM9

(144) 0x2328fc VDIVPD	%YMM7,%YMM4,%YMM4

(144) 0x232900 VPMULLQ	%YMM8,%YMM13,%YMM7

(144) 0x232906 VPADDQ	%YMM20,%YMM7,%YMM7

(144) 0x23290c VINSERTF128	$0x1,%XMM9,%YMM11,%YMM9

(144) 0x232912 VMOVAPD	%YMM4,0x1a0(%RSP)

(144) 0x23291b VDIVPD	%YMM9,%YMM6,%YMM4

(144) 0x232920 VPMULLQ	%YMM8,%YMM18,%YMM6

(144) 0x232926 VPADDQ	%YMM20,%YMM6,%YMM29

(144) 0x23292c VPMULLQ	%YMM8,%YMM17,%YMM6

(144) 0x232932 VPMULLQ	%YMM8,%YMM24,%YMM17

(144) 0x232938 VPADDQ	%YMM19,%YMM6,%YMM6

(144) 0x23293e VPADDQ	%YMM20,%YMM17,%YMM17

(144) 0x232944 VEXTRACTI128	$0x1,%YMM6,%XMM9

(144) 0x23294a VMOVQ	%XMM6,%RAX

(144) 0x23294f VMOVQ	%XMM9,%RCX

(144) 0x232954 VMOVSD	(%RDI,%RCX,8),%XMM11

(144) 0x232959 VPEXTRQ	$0x1,%XMM9,%RCX

(144) 0x23295f VMOVHPD	(%RDI,%RCX,8),%XMM11,%XMM9

(144) 0x232964 VPEXTRQ	$0x1,%XMM6,%RCX

(144) 0x23296a VEXTRACTI128	$0x1,%YMM7,%XMM6

(144) 0x232970 VMOVSD	(%RDI,%RAX,8),%XMM11

(144) 0x232975 VMOVQ	%XMM6,%RAX

(144) 0x23297a VMOVHPD	(%RDI,%RCX,8),%XMM11,%XMM11

(144) 0x23297f VPEXTRQ	$0x1,%XMM6,%RCX

(144) 0x232985 VMOVSD	(%RDI,%RAX,8),%XMM6

(144) 0x23298a VMOVQ	%XMM7,%RAX

(144) 0x23298f VMOVAPD	%YMM4,0x180(%RSP)

(144) 0x232998 VSUBPD	%YMM2,%YMM25,%YMM4

(144) 0x23299e VMOVHPD	(%RDI,%RCX,8),%XMM6,%XMM13

(144) 0x2329a3 VEXTRACTI32X4	$0x1,%YMM29,%XMM6

(144) 0x2329aa VPEXTRQ	$0x1,%XMM6,%RCX

(144) 0x2329b0 MOV	%RCX,0xb0(%RSP)

(144) 0x2329b8 VMOVAPD	%YMM4,0x2a0(%RSP)

(144) 0x2329c1 VPMULLQ	%YMM8,%YMM28,%YMM4

(144) 0x2329c7 VPADDQ	%YMM19,%YMM4,%YMM4

(144) 0x2329cd VINSERTF128	$0x1,%XMM9,%YMM11,%YMM9

(144) 0x2329d3 VMOVQ	%XMM4,%RSI

(144) 0x2329d8 VPEXTRQ	$0x1,%XMM4,%RDX

(144) 0x2329de VEXTRACTI128	$0x1,%YMM4,%XMM4

(144) 0x2329e4 VPEXTRQ	$0x1,%XMM4,%R8

(144) 0x2329ea VMOVQ	%XMM4,%R9

(144) 0x2329ef VMOVSD	(%RDI,%RAX,8),%XMM4

(144) 0x2329f4 VPEXTRQ	$0x1,%XMM7,%RAX

(144) 0x2329fa VMOVSD	(%RDI,%RSI,8),%XMM31

(144) 0x232a01 MOV	%RSI,0xd0(%RSP)

(144) 0x232a09 MOV	%RDX,0xd8(%RSP)

(144) 0x232a11 VMOVHPD	(%RDI,%RAX,8),%XMM4,%XMM7

(144) 0x232a16 VPMULLQ	%YMM8,%YMM23,%YMM4

(144) 0x232a1c VMOVHPD	(%RDI,%RDX,8),%XMM31,%XMM31

(144) 0x232a23 MOV	%R9,0xc0(%RSP)

(144) 0x232a2b MOV	%R8,0xc8(%RSP)

(144) 0x232a33 VPADDQ	%YMM19,%YMM4,%YMM4

(144) 0x232a39 VEXTRACTI32X4	$0x1,%YMM4,%XMM26

(144) 0x232a40 VMOVQ	%XMM26,%RAX

(144) 0x232a46 VMOVSD	(%RDI,%RAX,8),%XMM27

(144) 0x232a4d VPEXTRQ	$0x1,%XMM26,%RAX

(144) 0x232a54 VMOVHPD	(%RDI,%RAX,8),%XMM27,%XMM26

(144) 0x232a5b VMOVQ	%XMM4,%RAX

(144) 0x232a60 VMOVSD	(%RDI,%RAX,8),%XMM27

(144) 0x232a67 VPEXTRQ	$0x1,%XMM4,%RAX

(144) 0x232a6d VEXTRACTI32X4	$0x1,%YMM17,%XMM4

(144) 0x232a74 VINSERTF128	$0x1,%XMM13,%YMM7,%YMM7

(144) 0x232a7a VMOVHPD	(%RDI,%RAX,8),%XMM27,%XMM27

(144) 0x232a81 VMOVQ	%XMM4,%RAX

(144) 0x232a86 VMOVSD	(%RDI,%RAX,8),%XMM30

(144) 0x232a8d VPEXTRQ	$0x1,%XMM4,%RAX

(144) 0x232a93 VMOVHPD	(%RDI,%RAX,8),%XMM30,%XMM30

(144) 0x232a9a VMOVQ	%XMM17,%RAX

(144) 0x232aa0 VMOVSD	(%RDI,%RAX,8),%XMM4

(144) 0x232aa5 VPEXTRQ	$0x1,%XMM17,%RAX

(144) 0x232aac VMOVHPD	(%RDI,%RAX,8),%XMM4,%XMM17

(144) 0x232ab3 VMOVSD	(%RDI,%R9,8),%XMM4

(144) 0x232ab9 VMOVQ	%XMM6,%RAX

(144) 0x232abe VMOVHPD	(%RDI,%R8,8),%XMM4,%XMM4

(144) 0x232ac4 VMOVSD	(%RDI,%RAX,8),%XMM6

(144) 0x232ac9 MOV	%RAX,0xb8(%RSP)

(144) 0x232ad1 VMOVQ	%XMM29,%RAX

(144) 0x232ad7 MOV	%RAX,0xa8(%RSP)

(144) 0x232adf VMOVHPD	(%RDI,%RCX,8),%XMM6,%XMM6

(144) 0x232ae4 VINSERTF32X4	$0x1,%XMM4,%YMM31,%YMM4

(144) 0x232aeb VMOVSD	(%RDI,%RAX,8),%XMM31

(144) 0x232af2 VPEXTRQ	$0x1,%XMM29,%RAX

(144) 0x232af9 VMOVHPD	(%RDI,%RAX,8),%XMM31,%XMM29

(144) 0x232b00 MOV	%RAX,0xa0(%RSP)

(144) 0x232b08 VSUBPD	%YMM9,%YMM4,%YMM13

(144) 0x232b0d VINSERTF32X4	$0x1,%XMM30,%YMM17,%YMM9

(144) 0x232b14 VINSERTF32X4	$0x1,%XMM6,%YMM29,%YMM6

(144) 0x232b1b VSUBPD	%YMM3,%YMM25,%YMM29

(144) 0x232b21 VMOVAPD	0x2a0(%RSP),%YMM25

(144) 0x232b29 VSUBPD	%YMM7,%YMM6,%YMM11

(144) 0x232b2d VINSERTF32X4	$0x1,%XMM26,%YMM27,%YMM7

(144) 0x232b34 VSUBPD	%YMM6,%YMM9,%YMM17

(144) 0x232b3a VSUBPD	%YMM4,%YMM7,%YMM26

(144) 0x232b40 VMULPD	%YMM11,%YMM17,%YMM7

(144) 0x232b46 VMULPD	%YMM13,%YMM26,%YMM9

(144) 0x232b4c VCMPPD	$0x1,%YMM7,%YMM14,%K1

(144) 0x232b53 VCMPPD	$0x1,%YMM9,%YMM14,%K0

(144) 0x232b5a KSHIFTLB	$0x4,%K1,%K1

(144) 0x232b60 KORB	%K1,%K0,%K0

(144) 0x232b64 KORTESTB	%K0,%K0

(144) 0x232b68 JE	232c1f

(144) 0x232b6e VBROADCASTSD	-0x21a28(%RIP),%YMM27

(144) 0x232b78 VCMPPD	$0x1,%YMM26,%YMM14,%K1

(144) 0x232b7f VCMPPD	$0x1,%YMM17,%YMM14,%K2

(144) 0x232b86 VSUBPD	%YMM2,%YMM27,%YMM2

(144) 0x232b8c VSUBPD	%YMM3,%YMM27,%YMM3

(144) 0x232b92 VBROADCASTSD	-0x21a24(%RIP),%YMM27

(144) 0x232b9c VXORPD	%YMM27,%YMM2,%YMM30

(144) 0x232ba2 VXORPD	%YMM27,%YMM3,%YMM31

(144) 0x232ba8 VANDPD	%YMM16,%YMM26,%YMM27

(144) 0x232bae VMOVAPD	%YMM2,%YMM30{%K1}

(144) 0x232bb4 VMOVAPD	%YMM3,%YMM31{%K2}

(144) 0x232bba VANDPD	%YMM16,%YMM13,%YMM2

(144) 0x232bc0 VANDPD	%YMM16,%YMM17,%YMM13

(144) 0x232bc6 VANDPD	%YMM16,%YMM11,%YMM3

(144) 0x232bcc VMINPD	%YMM13,%YMM3,%YMM26

(144) 0x232bd2 VMULPD	0x180(%RSP),%YMM3,%YMM3

(144) 0x232bdb VMINPD	%YMM27,%YMM2,%YMM17

(144) 0x232be1 VMULPD	0x1a0(%RSP),%YMM2,%YMM2

(144) 0x232bea VFMADD231PD	%YMM13,%YMM29,%YMM3

(144) 0x232bf0 VBROADCASTSD	-0x21a11(%RIP),%YMM13

(144) 0x232bf9 VFMADD231PD	%YMM27,%YMM25,%YMM2

(144) 0x232bff VMULPD	%YMM2,%YMM13,%YMM2

(144) 0x232c03 VMINPD	%YMM2,%YMM17,%YMM2

(144) 0x232c09 VMULPD	%YMM30,%YMM2,%YMM27

(144) 0x232c0f VMULPD	%YMM3,%YMM13,%YMM2

(144) 0x232c13 VMINPD	%YMM2,%YMM26,%YMM2

(144) 0x232c19 VMULPD	%YMM31,%YMM2,%YMM30

(144) 0x232c1f VCMPPD	$0x1,%YMM7,%YMM14,%YMM3

(144) 0x232c24 VCMPPD	$0x1,%YMM9,%YMM14,%YMM2

(144) 0x232c2a MOV	0x60(%RSP),%R15

(144) 0x232c2f VMOVAPD	0x1a0(%RSP),%YMM31

(144) 0x232c37 VANDPD	%YMM3,%YMM15,%YMM3

(144) 0x232c3b VANDPD	%YMM2,%YMM15,%YMM2

(144) 0x232c3f VPCMPEQQ	%YMM15,%YMM3,%K2

(144) 0x232c45 VMOVDQA	0x240(%RSP),%YMM3

(144) 0x232c4e VPCMPEQQ	%YMM15,%YMM2,%K1

(144) 0x232c54 VADDPD	%YMM27,%YMM4,%YMM4{%K1}

(144) 0x232c5a VADDPD	%YMM30,%YMM6,%YMM6{%K2}

(144) 0x232c60 VMULPD	%YMM4,%YMM12,%YMM12

(144) 0x232c64 VMULPD	%YMM5,%YMM6,%YMM5

(144) 0x232c68 VPMULLQ	0x2c0(%RSP),%YMM10,%YMM6

(144) 0x232c70 VPMULLQ	%YMM21,%YMM3,%YMM2

(144) 0x232c76 VPMULLQ	%YMM22,%YMM3,%YMM3

(144) 0x232c7c VPADDQ	%YMM19,%YMM2,%YMM2

(144) 0x232c82 VPADDQ	%YMM20,%YMM3,%YMM3

(144) 0x232c88 VMOVQ	%XMM2,%RCX

(144) 0x232c8d VPEXTRQ	$0x1,%XMM2,%R8

(144) 0x232c93 VEXTRACTI128	$0x1,%YMM2,%XMM2

(144) 0x232c99 VMOVQ	%XMM3,%RAX

(144) 0x232c9e VPEXTRQ	$0x1,%XMM3,%RDX

(144) 0x232ca4 VMOVQ	%XMM2,%R13

(144) 0x232ca9 VPEXTRQ	$0x1,%XMM2,%R9

(144) 0x232caf VEXTRACTI128	$0x1,%YMM3,%XMM2

(144) 0x232cb5 VMOVLPD	%XMM12,(%R15,%RCX,8)

(144) 0x232cbb VMOVHPD	%XMM12,(%R15,%R8,8)

(144) 0x232cc1 VPMULLQ	%YMM10,%YMM18,%YMM3

(144) 0x232cc7 VMOVQ	%XMM2,%RSI

(144) 0x232ccc VPEXTRQ	$0x1,%XMM2,%R10

(144) 0x232cd2 VEXTRACTF128	$0x1,%YMM12,%XMM2

(144) 0x232cd8 VPADDQ	%YMM20,%YMM6,%YMM6

(144) 0x232cde VMOVLPD	%XMM2,(%R15,%R13,8)

(144) 0x232ce4 VMOVHPD	%XMM2,(%R15,%R9,8)

(144) 0x232cea VEXTRACTF128	$0x1,%YMM5,%XMM2

(144) 0x232cf0 VMOVLPD	%XMM5,(%R15,%RAX,8)

(144) 0x232cf6 VMOVHPD	%XMM5,(%R15,%RDX,8)

(144) 0x232cfc VPADDQ	%YMM20,%YMM3,%YMM3

(144) 0x232d02 VMOVQ	%XMM3,%R8

(144) 0x232d07 VPEXTRQ	$0x1,%XMM3,%R9

(144) 0x232d0d VMOVLPD	%XMM2,(%R15,%RSI,8)

(144) 0x232d13 VMOVHPD	%XMM2,(%R15,%R10,8)

(144) 0x232d19 VPMULLQ	%YMM10,%YMM28,%YMM2

(144) 0x232d1f VMOVSD	(%RBX,%R8,8),%XMM4

(144) 0x232d25 VPEXTRQ	$0x1,%XMM6,%R8

(144) 0x232d2b VMOVHPD	(%RBX,%R9,8),%XMM4,%XMM4

(144) 0x232d31 VMOVQ	%XMM6,%R9

(144) 0x232d36 VPADDQ	%YMM19,%YMM2,%YMM2

(144) 0x232d3c VMOVSD	(%RBX,%R9,8),%XMM7

(144) 0x232d42 VMOVQ	%XMM2,%RAX

(144) 0x232d47 VPEXTRQ	$0x1,%XMM2,%RCX

(144) 0x232d4d VEXTRACTI128	$0x1,%YMM2,%XMM2

(144) 0x232d53 VMOVHPD	(%RBX,%R8,8),%XMM7,%XMM7

(144) 0x232d59 VMOVQ	%XMM2,%RDX

(144) 0x232d5e VPEXTRQ	$0x1,%XMM2,%RSI

(144) 0x232d64 VEXTRACTI128	$0x1,%YMM3,%XMM2

(144) 0x232d6a VMOVSD	(%RBX,%RAX,8),%XMM3

(144) 0x232d6f VPEXTRQ	$0x1,%XMM2,%R10

(144) 0x232d75 VMOVQ	%XMM2,%R13

(144) 0x232d7a VMOVSD	(%RBX,%RDX,8),%XMM2

(144) 0x232d7f VMOVHPD	(%RBX,%RCX,8),%XMM3,%XMM3

(144) 0x232d84 VMOVHPD	(%RBX,%RSI,8),%XMM2,%XMM2

(144) 0x232d89 VINSERTF128	$0x1,%XMM2,%YMM3,%YMM2

(144) 0x232d8f VMOVSD	(%RBX,%R13,8),%XMM3

(144) 0x232d95 VMOVHPD	(%RBX,%R10,8),%XMM3,%XMM3

(144) 0x232d9b VINSERTF128	$0x1,%XMM3,%YMM4,%YMM3

(144) 0x232da1 VPMULLQ	0x2e0(%RSP),%YMM10,%YMM4

(144) 0x232da9 VPADDQ	%YMM19,%YMM4,%YMM4

(144) 0x232daf VMOVQ	%XMM4,%RAX

(144) 0x232db4 VPEXTRQ	$0x1,%XMM4,%RCX

(144) 0x232dba VEXTRACTI128	$0x1,%YMM4,%XMM4

(144) 0x232dc0 VMOVQ	%XMM4,%RDX

(144) 0x232dc5 VPEXTRQ	$0x1,%XMM4,%RSI

(144) 0x232dcb VEXTRACTI128	$0x1,%YMM6,%XMM4

(144) 0x232dd1 VMOVSD	(%RBX,%RAX,8),%XMM6

(144) 0x232dd6 VMOVQ	%XMM4,%R10

(144) 0x232ddb VPEXTRQ	$0x1,%XMM4,%R13

(144) 0x232de1 VMOVSD	(%RBX,%RDX,8),%XMM4

(144) 0x232de6 VMOVHPD	(%RBX,%RCX,8),%XMM6,%XMM6

(144) 0x232deb VMOVHPD	(%RBX,%RSI,8),%XMM4,%XMM4

(144) 0x232df0 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

(144) 0x232df6 VMOVSD	(%RBX,%R10,8),%XMM6

(144) 0x232dfc VMOVHPD	(%RBX,%R13,8),%XMM6,%XMM6

(144) 0x232e02 VSUBPD	%YMM4,%YMM2,%YMM18

(144) 0x232e08 VPMULLQ	%YMM10,%YMM23,%YMM4

(144) 0x232e0e VPADDQ	%YMM19,%YMM4,%YMM4

(144) 0x232e14 VMOVQ	%XMM4,%RAX

(144) 0x232e19 VPEXTRQ	$0x1,%XMM4,%RCX

(144) 0x232e1f VEXTRACTI128	$0x1,%YMM4,%XMM4

(144) 0x232e25 VMOVQ	%XMM4,%RDX

(144) 0x232e2a VPEXTRQ	$0x1,%XMM4,%RSI

(144) 0x232e30 VINSERTF128	$0x1,%XMM6,%YMM7,%YMM6

(144) 0x232e36 VSUBPD	%YMM6,%YMM3,%YMM28

(144) 0x232e3c VPMULLQ	%YMM10,%YMM24,%YMM6

(144) 0x232e42 VPADDQ	%YMM20,%YMM6,%YMM6

(144) 0x232e48 VEXTRACTI128	$0x1,%YMM6,%XMM4

(144) 0x232e4e VMOVQ	%XMM6,%R9

(144) 0x232e53 VPEXTRQ	$0x1,%XMM6,%R8

(144) 0x232e59 VMOVSD	(%RBX,%RAX,8),%XMM6

(144) 0x232e5e VMOVQ	%XMM4,%R10

(144) 0x232e63 VPEXTRQ	$0x1,%XMM4,%R13

(144) 0x232e69 VMOVSD	(%RBX,%RDX,8),%XMM4

(144) 0x232e6e VMOVHPD	(%RBX,%RCX,8),%XMM6,%XMM6

(144) 0x232e73 VMOVSD	(%RBX,%R9,8),%XMM7

(144) 0x232e79 VMOVHPD	(%RBX,%RSI,8),%XMM4,%XMM4

(144) 0x232e7e VMOVHPD	(%RBX,%R8,8),%XMM7,%XMM7

(144) 0x232e84 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

(144) 0x232e8a VMOVSD	(%RBX,%R10,8),%XMM6

(144) 0x232e90 VMOVHPD	(%RBX,%R13,8),%XMM6,%XMM6

(144) 0x232e96 VSUBPD	%YMM2,%YMM4,%YMM23

(144) 0x232e9c VINSERTF128	$0x1,%XMM6,%YMM7,%YMM6

(144) 0x232ea2 VSUBPD	%YMM3,%YMM6,%YMM24

(144) 0x232ea8 VMULPD	%YMM18,%YMM23,%YMM6

(144) 0x232eae VMULPD	%YMM28,%YMM24,%YMM4

(144) 0x232eb4 VCMPPD	$0x1,%YMM6,%YMM14,%K0

(144) 0x232ebb VCMPPD	$0x1,%YMM4,%YMM14,%K1

(144) 0x232ec2 KSHIFTLB	$0x4,%K1,%K1

(144) 0x232ec8 KORB	%K1,%K0,%K0

(144) 0x232ecc KORTESTB	%K0,%K0

(144) 0x232ed0 JE	232350

(144) 0x232ed6 MOV	0xc0(%RSP),%RAX

(144) 0x232ede VCMPPD	$0x1,%YMM24,%YMM14,%K2

(144) 0x232ee5 VCMPPD	$0x1,%YMM23,%YMM14,%K1

(144) 0x232eec VMOVSD	(%RDI,%RAX,8),%XMM7

(144) 0x232ef1 MOV	0xc8(%RSP),%RAX

(144) 0x232ef9 VMOVHPD	(%RDI,%RAX,8),%XMM7,%XMM7

(144) 0x232efe MOV	0xd0(%RSP),%RAX

(144) 0x232f06 VMOVSD	(%RDI,%RAX,8),%XMM9

(144) 0x232f0b MOV	0xd8(%RSP),%RAX

(144) 0x232f13 VMOVHPD	(%RDI,%RAX,8),%XMM9,%XMM9

(144) 0x232f18 MOV	0xb8(%RSP),%RAX

(144) 0x232f20 VMOVSD	(%RDI,%RAX,8),%XMM11

(144) 0x232f25 MOV	0xb0(%RSP),%RAX

(144) 0x232f2d VINSERTF128	$0x1,%XMM7,%YMM9,%YMM7

(144) 0x232f33 VMOVHPD	(%RDI,%RAX,8),%XMM11,%XMM11

(144) 0x232f38 MOV	0xa8(%RSP),%RAX

(144) 0x232f40 VMOVSD	(%RDI,%RAX,8),%XMM13

(144) 0x232f45 MOV	0xa0(%RSP),%RAX

(144) 0x232f4d VMOVHPD	(%RDI,%RAX,8),%XMM13,%XMM13

(144) 0x232f52 MOV	0xe8(%RSP),%RAX

(144) 0x232f5a VMOVSD	(%R11,%RAX,8),%XMM17

(144) 0x232f61 MOV	0xe0(%RSP),%RAX

(144) 0x232f69 VINSERTF128	$0x1,%XMM11,%YMM13,%YMM9

(144) 0x232f6f VANDPD	%YMM16,%YMM12,%YMM13

(144) 0x232f75 VMOVHPD	(%R11,%RAX,8),%XMM17,%XMM17

(144) 0x232f7c MOV	0x108(%RSP),%RAX

(144) 0x232f84 VMOVSD	(%R11,%RAX,8),%XMM26

(144) 0x232f8b MOV	0x100(%RSP),%RAX

(144) 0x232f93 VMOVHPD	(%R11,%RAX,8),%XMM26,%XMM26

(144) 0x232f9a MOV	0xf0(%RSP),%RAX

(144) 0x232fa2 VMOVSD	(%R11,%RAX,8),%XMM27

(144) 0x232fa9 MOV	0xf8(%RSP),%RAX

(144) 0x232fb1 VINSERTF32X4	$0x1,%XMM17,%YMM26,%YMM11

(144) 0x232fb8 VANDPD	%YMM16,%YMM24,%YMM26

(144) 0x232fbe VANDPD	%YMM16,%YMM23,%YMM17

(144) 0x232fc4 VMOVHPD	(%R11,%RAX,8),%XMM27,%XMM27

(144) 0x232fcb MOV	0x118(%RSP),%RAX

(144) 0x232fd3 VMULPD	%YMM7,%YMM11,%YMM7

(144) 0x232fd7 VANDPD	%YMM16,%YMM5,%YMM11

(144) 0x232fdd VDIVPD	%YMM7,%YMM13,%YMM7

(144) 0x232fe1 VMOVSD	(%R11,%RAX,8),%XMM30

(144) 0x232fe8 MOV	0x110(%RSP),%RAX

(144) 0x232ff0 VMOVHPD	(%R11,%RAX,8),%XMM30,%XMM30

(144) 0x232ff7 VINSERTF32X4	$0x1,%XMM27,%YMM30,%YMM13

(144) 0x232ffe VMULPD	%YMM9,%YMM13,%YMM9

(144) 0x233003 VDIVPD	%YMM9,%YMM11,%YMM9

(144) 0x233008 VBROADCASTSD	-0x21ec1(%RIP),%YMM11

(144) 0x233011 VSUBPD	%YMM7,%YMM11,%YMM7

(144) 0x233015 VSUBPD	%YMM9,%YMM11,%YMM9

(144) 0x23301a VBROADCASTSD	-0x21eab(%RIP),%YMM11

(144) 0x233023 VXORPD	%YMM7,%YMM11,%YMM13

(144) 0x233027 VXORPD	%YMM11,%YMM9,%YMM11

(144) 0x23302c VMOVAPD	%YMM9,%YMM11{%K2}

(144) 0x233032 VANDPD	%YMM16,%YMM28,%YMM9

(144) 0x233038 VMOVAPD	%YMM7,%YMM13{%K1}

(144) 0x23303e VANDPD	%YMM16,%YMM18,%YMM7

(144) 0x233044 VMINPD	%YMM26,%YMM9,%YMM24

(144) 0x23304a VMULPD	0x180(%RSP),%YMM9,%YMM9

(144) 0x233053 VMINPD	%YMM17,%YMM7,%YMM23

(144) 0x233059 VMULPD	%YMM31,%YMM7,%YMM7

(144) 0x23305f VFMADD213PD	%YMM7,%YMM17,%YMM25

(144) 0x233065 VFMADD213PD	%YMM9,%YMM26,%YMM29

(144) 0x23306b VBROADCASTSD	-0x21e8c(%RIP),%YMM9

(144) 0x233074 VMULPD	%YMM9,%YMM25,%YMM7

(144) 0x23307a VMULPD	%YMM9,%YMM29,%YMM9

(144) 0x233080 VMINPD	%YMM7,%YMM23,%YMM7

(144) 0x233086 VMINPD	%YMM9,%YMM24,%YMM9

(144) 0x23308c VMULPD	%YMM7,%YMM13,%YMM7

(144) 0x233090 VMULPD	%YMM9,%YMM11,%YMM9

(144) 0x233095 JMP	232350

0x23309a MOV	0x78(%RSP),%RAX

0x23309f MOV	0x4(%RSP),%R13D

0x2330a4 MOV	0x10(%RSP),%R10

0x2330a9 CMP	%RAX,0x80(%RSP)

0x2330b1 JNE	2330d5

0x2330b3 MOV	0x24(%RSP),%ESI

0x2330b7 LEA	0x27a0a(%RIP),%RDI

0x2330be VZEROUPPER

0x2330c1 CALL	259690 <@plt_start@+0x540>

0x2330c6 LEA	-0x28(%RBP),%RSP

0x2330ca POP	%RBX

0x2330cb POP	%R12

0x2330cd POP	%R13

0x2330cf POP	%R14

0x2330d1 POP	%R15

0x2330d3 POP	%RBP

0x2330d4 RET

0x2330d5 VMOVDDUP	-0x21f85(%RIP),%XMM1

0x2330dd VMOVSD	-0x21fdd(%RIP),%XMM2

0x2330e5 VMOVSD	-0x21f9d(%RIP),%XMM3

0x2330ed VMOVDDUP	-0x21f7d(%RIP),%XMM4

0x2330f5 VMOVDDUP	-0x21fa5(%RIP),%XMM5

0x2330fd VMOVSD	-0x21f1d(%RIP),%XMM6

0x233105 VPXOR	%XMM0,%XMM0,%XMM0

0x233109 JMP	233144

0x23310b NOPL	(%RAX,%RAX,1)

(143) 0x233110 IMUL	0x88(%RSP),%RSI

(143) 0x233119 VADDSD	%XMM11,%XMM10,%XMM8

(143) 0x23311e MOV	0x10(%RSP),%RCX

(143) 0x233123 MOV	0x4(%RSP),%R13D

(143) 0x233128 VMULSD	%XMM7,%XMM8,%XMM7

(143) 0x23312c LEA	0x1(%RCX),%R10

(143) 0x233130 ADD	%RDX,%RSI

(143) 0x233133 VMOVSD	%XMM7,(%R12,%RSI,8)

(143) 0x233139 CMP	%RCX,0x50(%RSP)

(143) 0x23313e JLE	2330b3

(143) 0x233144 MOV	%R10,%RAX

(143) 0x233147 CQTO

(143) 0x233149 IDIVQ	0x48(%RSP)

(143) 0x23314e MOV	0x58(%RSP),%RCX

(143) 0x233153 MOV	0x40(%RSP),%R8

(143) 0x233158 MOV	0x68(%RSP),%R9

(143) 0x23315d MOV	%R10,0x10(%RSP)

(143) 0x233162 ADD	%R13D,%EDX

(143) 0x233165 MOVSXD	%EDX,%RDX

(143) 0x233168 ADD	%EAX,%ECX

(143) 0x23316a MOVSXD	%ECX,%RSI

(143) 0x23316d IMUL	%RSI,%R8

(143) 0x233171 ADD	%RDX,%R8

(143) 0x233174 VMOVSD	(%R9,%R8,8),%XMM7

(143) 0x23317a VUCOMISD	%XMM7,%XMM0

(143) 0x23317e JAE	2331a0

(143) 0x233180 ADD	0x8(%RSP),%EAX

(143) 0x233184 ADD	$-0x2,%ECX

(143) 0x233187 MOVSXD	%ECX,%R9

(143) 0x23318a MOVSXD	%EAX,%R13

(143) 0x23318d MOV	%RSI,%RAX

(143) 0x233190 MOV	%R13,%R10

(143) 0x233193 JMP	2331bd

0x233195 NOPW	%CS:(%RAX,%RAX,1)

(143) 0x2331a0 MOV	0x28(%RSP),%R8D

(143) 0x2331a5 INC	%ECX

(143) 0x2331a7 MOV	%RSI,%R10

(143) 0x2331aa CMP	%ECX,%R8D

(143) 0x2331ad CMOVL	%R8D,%ECX

(143) 0x2331b1 ADD	0x8(%RSP),%EAX

(143) 0x2331b5 MOVSXD	%ECX,%R9

(143) 0x2331b8 MOV	%R9,%R13

(143) 0x2331bb CLTQ

(143) 0x2331bd MOV	0x30(%RSP),%R8

(143) 0x2331c2 MOV	%R10,%RCX

(143) 0x2331c5 VANDPD	%XMM1,%XMM7,%XMM8

(143) 0x2331c9 MOV	0x38(%RSP),%R15

(143) 0x2331ce IMUL	%R8,%RCX

(143) 0x2331d2 MOV	%R9,%R8

(143) 0x2331d5 IMUL	%R15,%R8

(143) 0x2331d9 ADD	%RDX,%RCX

(143) 0x2331dc ADD	%RDX,%R8

(143) 0x2331df VDIVSD	(%R11,%RCX,8),%XMM8,%XMM12

(143) 0x2331e5 VMOVSD	(%R14,%RSI,8),%XMM8

(143) 0x2331eb VFMADD213SD	%XMM8,%XMM12,%XMM8

(143) 0x2331f0 VDIVSD	(%R14,%R13,8),%XMM8,%XMM9

(143) 0x2331f6 MOV	%R10,%R13

(143) 0x2331f9 IMUL	%R15,%R13

(143) 0x2331fd VSUBSD	%XMM12,%XMM2,%XMM8

(143) 0x233202 ADD	%RDX,%R13

(143) 0x233205 VMOVSD	(%RDI,%R13,8),%XMM11

(143) 0x23320b VSUBSD	(%RDI,%R8,8),%XMM11,%XMM13

(143) 0x233211 MOV	%RAX,%R8

(143) 0x233214 IMUL	%R15,%R8

(143) 0x233218 ADD	%RDX,%R8

(143) 0x23321b VMOVSD	(%RDI,%R8,8),%XMM10

(143) 0x233221 VSUBSD	%XMM11,%XMM10,%XMM14

(143) 0x233226 VXORPD	%XMM10,%XMM10,%XMM10

(143) 0x23322b VMULSD	%XMM13,%XMM14,%XMM15

(143) 0x233230 VUCOMISD	%XMM10,%XMM15

(143) 0x233235 VXORPD	%XMM15,%XMM15,%XMM15

(143) 0x23323a JBE	233277

(143) 0x23323c VSUBSD	%XMM12,%XMM3,%XMM12

(143) 0x233241 VCMPSD	$0x1,%XMM14,%XMM0,%K1

(143) 0x233248 VXORPD	%XMM4,%XMM12,%XMM15

(143) 0x23324c VMOVSD	%XMM12,%XMM15,%XMM15{%K1}

(143) 0x233252 VANDPD	%XMM5,%XMM13,%XMM12

(143) 0x233256 VANDPD	%XMM5,%XMM14,%XMM13

(143) 0x23325a VMINSD	%XMM13,%XMM12,%XMM14

(143) 0x23325f VMULSD	%XMM9,%XMM12,%XMM12

(143) 0x233264 VFMADD231SD	%XMM13,%XMM8,%XMM12

(143) 0x233269 VMULSD	%XMM6,%XMM12,%XMM12

(143) 0x23326d VMINSD	%XMM12,%XMM14,%XMM12

(143) 0x233272 VMULSD	%XMM15,%XMM12,%XMM15

(143) 0x233277 MOV	0x98(%RSP),%R8

(143) 0x23327f VADDSD	%XMM11,%XMM15,%XMM11

(143) 0x233284 MOV	0x60(%RSP),%R15

(143) 0x233289 VMULSD	%XMM7,%XMM11,%XMM7

(143) 0x23328d IMUL	%RSI,%R8

(143) 0x233291 ADD	%RDX,%R8

(143) 0x233294 VMOVSD	%XMM7,(%R15,%R8,8)

(143) 0x23329a MOV	0x90(%RSP),%R15

(143) 0x2332a2 IMUL	%R15,%R10

(143) 0x2332a6 IMUL	%R15,%RAX

(143) 0x2332aa IMUL	%R15,%R9

(143) 0x2332ae ADD	%RDX,%R10

(143) 0x2332b1 ADD	%RDX,%RAX

(143) 0x2332b4 ADD	%RDX,%R9

(143) 0x2332b7 VMOVSD	(%RBX,%R10,8),%XMM11

(143) 0x2332bd VMOVSD	(%RBX,%RAX,8),%XMM13

(143) 0x2332c2 VSUBSD	(%RBX,%R9,8),%XMM11,%XMM12

(143) 0x2332c8 VSUBSD	%XMM11,%XMM13,%XMM13

(143) 0x2332cd VMULSD	%XMM12,%XMM13,%XMM14

(143) 0x2332d2 VUCOMISD	%XMM10,%XMM14

(143) 0x2332d7 JBE	233110

(143) 0x2332dd VMOVSD	(%R11,%RCX,8),%XMM14

(143) 0x2332e3 VANDPD	%XMM5,%XMM7,%XMM10

(143) 0x2332e7 VCMPSD	$0x1,%XMM13,%XMM0,%K1

(143) 0x2332ee VMULSD	(%RDI,%R13,8),%XMM14,%XMM14

(143) 0x2332f4 VDIVSD	%XMM14,%XMM10,%XMM10

(143) 0x2332f9 VSUBSD	%XMM10,%XMM3,%XMM10

(143) 0x2332fe VXORPD	%XMM4,%XMM10,%XMM14

(143) 0x233302 VMOVSD	%XMM10,%XMM14,%XMM14{%K1}

(143) 0x233308 VANDPD	%XMM5,%XMM12,%XMM10

(143) 0x23330c VANDPD	%XMM5,%XMM13,%XMM12

(143) 0x233310 VMULSD	%XMM9,%XMM10,%XMM9

(143) 0x233315 VMINSD	%XMM12,%XMM10,%XMM13

(143) 0x23331a VFMADD213SD	%XMM9,%XMM12,%XMM8

(143) 0x23331f VMULSD	%XMM6,%XMM8,%XMM8

(143) 0x233323 VMINSD	%XMM8,%XMM13,%XMM8

(143) 0x233328 VMULSD	%XMM8,%XMM14,%XMM10

(143) 0x23332d JMP	233110

0x233332 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-202
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.00 to 8.63 cycles (2.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

21% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
34% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
VEXTRACTI128: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
VPBROADCASTD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
VPBROADCASTQ: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 400 bytes. The binary function is storing 472 bytes.

General properties

nb instructions	163
nb uops	175
loop length	831
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	9
used zmm registers	0
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.88 cycles
front end	21.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.00	7.00	7.00	7.00	7.00	7.00	22.00	22.00	22.00	22.00	2.00	7.00	7.00	2.00	6.00	6.00
cycles	7.00	7.00	7.00	7.00	7.00	7.00	22.00	22.00	22.00	22.00	2.00	7.00	7.00	2.00	6.00	6.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.88
Dispatch	22.00
Overall L1	22.00

Vectorization ratios

INT

all	20%
load	10%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	23%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	21%
load	5%
store	34%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	16%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	19%
load	12%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	16%
load	13%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.00 cycles. At this rate:

7% of peak load performance is reached (18.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 2320a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x320,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EAX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JLE 2330c6 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1026>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2330c6 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1026>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %RAX,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RAX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x130(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x2897f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x34(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x78(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x20(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RBX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 2330b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1013>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13D,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RCX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R14),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RDX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2330d5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1035>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
AND $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R10,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %R9,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ -0x20f6a(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VBROADCASTSD -0x210f3(%RIP),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x21105(%RIP),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RDX,%YMM10	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA %YMM3,0x240(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x210aa(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RCX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVDQA %YMM4,0x260(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R15,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %RCX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVDQA %YMM4,0x220(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ -0x211a5(%RIP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x58(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VEXTRACTI128 $0x1,%YMM1,0x140(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0.50	0.50	3	0.50	vect (25.0%)
VMOVAPS %YMM3,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x211ed(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM2,0x170(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %R13D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %YMM4,0x1e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQA %XMM2,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTQ %R10,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM2,0x280(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTD %R8D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %XMM2,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x38(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM2,0x150(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %YMM3,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RAX,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
JMP 232432 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x392>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x4(%RSP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x10(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,0x80(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 2330d5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1035>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x24(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x27a0a(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVDDUP -0x21f85(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x21fdd(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x21f9d(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x21f7d(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x21fa5(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x21f1d(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 233144 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x10a4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_cell.cpp:157-202
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157-202
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.00 to 8.63 cycles (2.55x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 16% of vector register length is used (average across all SSE/AVX instructions).

Details

21% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
34% of SSE/AVX stores are used in vector version.
33% of SSE/AVX addition or subtraction instructions are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:157

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
VEXTRACTI128: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
VPBROADCASTD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
VPBROADCASTQ: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:158

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 400 bytes. The binary function is storing 472 bytes.

General properties

nb instructions	163
nb uops	175
loop length	831
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	9
used zmm registers	0
nb stack references	44

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	21.88 cycles
front end	21.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.00	7.00	7.00	7.00	7.00	7.00	22.00	22.00	22.00	22.00	2.00	7.00	7.00	2.00	6.00	6.00
cycles	7.00	7.00	7.00	7.00	7.00	7.00	22.00	22.00	22.00	22.00	2.00	7.00	7.00	2.00	6.00	6.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	21.88
Dispatch	22.00
Overall L1	22.00

Vectorization ratios

INT

all	20%
load	10%
store	30%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	23%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	21%
load	5%
store	34%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	16%
load	15%
store	18%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	19%
load	12%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	16%
load	13%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	22%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.00 cycles. At this rate:

7% of peak load performance is reached (18.18 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
16% of peak store performance is reached (21.45 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 2320a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x320,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x4,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EAX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RAX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
JLE 2330c6 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1026>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
INC %R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2330c6 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1026>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R13D,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RCX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOVQ $0,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %RAX,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
MOV %RAX,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x130(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x2897f(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x34(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x78(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x20(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x2c(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RBX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RBX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 2330b3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1013>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R13D,0x4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV (%R8),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RCX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RAX),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x50(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RCX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R8,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R14),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%RDI),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %R10,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R15,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RCX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R9,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8D,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RDX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x8,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2330d5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1035>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RAX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x48(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
AND $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R10,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %R9,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ -0x20f6a(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VBROADCASTSD -0x210f3(%RIP),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x21105(%RIP),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %RDX,%YMM10	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
VMOVDQA %YMM3,0x240(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x210aa(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
ADD %RCX,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVDQA %YMM4,0x260(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R15,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %RCX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVDQA %YMM4,0x220(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ -0x211a5(%RIP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %RAX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x58(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VEXTRACTI128 $0x1,%YMM1,0x140(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0.50	0.50	3	0.50	vect (25.0%)
VMOVAPS %YMM3,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x211ed(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM2,0x170(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %R13D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %YMM4,0x1e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VMOVDQA %XMM2,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTQ %R10,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM2,0x280(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTD %R8D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %XMM2,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x38(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM2,0x150(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %YMM3,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RAX,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
JMP 232432 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x392>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x4(%RSP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV 0x10(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,0x80(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 2330d5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x1035>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x24(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x27a0a(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVDDUP -0x21f85(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x21fdd(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x21f9d(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x21f7d(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x21fa5(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x21f1d(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 233144 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.12+0x10a4>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.51	1.31
○Loop 144 - advec_cell.cpp:158-202 - exec	3.50	1.31
○Loop 143 - advec_cell.cpp:158-202 - exec	0.00	0.00

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Execution units bottlenecks

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512-bits vectorization

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CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code