OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:136-140 [...]	Coverage (incl. loops): 1.50% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 136 - 140

--------------------------------------------------------------------------------

136: #pragma omp parallel for simd collapse(2)

137:       for (int j = (y_min - 2 + 1); j < (y_max + 2 + 2); j++) {

138:         for (int i = (x_min - 2 + 1); i < (x_max + 2 + 2); i++) {

139:           pre_vol(i, j) = volume(i, j) + (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j) + vol_flux_x(i + 1, j + 0) - vol_flux_x(i, j));

140:           post_vol(i, j) = pre_vol(i, j) - (vol_flux_y(i + 0, j + 1) - vol_flux_y(i, j));

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x2315e0 PUSH	%RBP

0x2315e1 MOV	%RSP,%RBP

0x2315e4 PUSH	%R15

0x2315e6 PUSH	%R14

0x2315e8 PUSH	%R13

0x2315ea PUSH	%R12

0x2315ec PUSH	%RBX

0x2315ed SUB	$0xa8,%RSP

0x2315f4 MOV	(%RCX),%R15D

0x2315f7 MOV	(%RDX),%R12D

0x2315fa ADD	$0x4,%R15D

0x2315fe CMP	%R15D,%R12D

0x231601 JG	231c07

0x231607 MOV	(%R9),%EBX

0x23160a MOV	(%R8),%EAX

0x23160d ADD	$0x4,%EBX

0x231610 CMP	%EBX,%EAX

0x231612 JG	231c07

0x231618 LEA	-0x1(%RAX),%ECX

0x23161b LEA	-0x1(%R12),%R14D

0x231620 MOV	(%RDI),%ESI

0x231622 MOVQ	$0,-0x78(%RBP)

0x23162a MOVQ	$0x1,-0xc8(%RBP)

0x231635 MOVL	$0,-0x38(%RBP)

0x23163c SUB	%ECX,%EBX

0x23163e SUB	%R14D,%R15D

0x231641 MOV	%RCX,-0x70(%RBP)

0x231645 IMUL	%RBX,%R15

0x231649 DEC	%R15

0x23164c MOV	%R15,-0x30(%RBP)

0x231650 SUB	$0x8,%RSP

0x231654 LEA	-0x38(%RBP),%RCX

0x231658 MOV	%RAX,%R13

0x23165b LEA	-0xc8(%RBP),%RAX

0x231662 LEA	0x293b7(%RIP),%RDI

0x231669 LEA	-0x78(%RBP),%R8

0x23166d LEA	-0x30(%RBP),%R9

0x231671 MOV	%ESI,-0x34(%RBP)

0x231674 MOV	$0x22,%EDX

0x231679 PUSH	$0x1

0x23167b PUSH	$0x1

0x23167d PUSH	%RAX

0x23167e CALL	259680 <@plt_start@+0x530>

0x231683 ADD	$0x20,%RSP

0x231687 MOV	-0x30(%RBP),%RAX

0x23168b MOV	-0x78(%RBP),%RCX

0x23168f CMP	%R15,%RAX

0x231692 CMOVL	%RAX,%R15

0x231696 MOV	%R15,-0x30(%RBP)

0x23169a CMP	%R15,%RCX

0x23169d JG	231bf5

0x2316a3 MOV	0x28(%RBP),%RDX

0x2316a7 MOV	0x18(%RBP),%RDI

0x2316ab MOV	0x30(%RBP),%RAX

0x2316af MOV	0x20(%RBP),%RSI

0x2316b3 MOV	0x10(%RBP),%R8

0x2316b7 MOV	%R13,-0x68(%RBP)

0x2316bb MOV	%RBX,-0x60(%RBP)

0x2316bf MOV	%R14,-0x58(%RBP)

0x2316c3 MOV	(%RDI),%R9

0x2316c6 MOV	(%RDX),%R10

0x2316c9 MOV	0x10(%RDX),%R11

0x2316cd MOV	(%R8),%RDX

0x2316d0 MOV	0x10(%RDI),%RDI

0x2316d4 MOV	(%RSI),%R13

0x2316d7 MOV	%R9,-0x50(%RBP)

0x2316db MOV	0x10(%RSI),%R9

0x2316df MOV	%R10,-0x48(%RBP)

0x2316e3 MOV	0x10(%R8),%R10

0x2316e7 MOV	(%RAX),%R8

0x2316ea MOV	0x10(%RAX),%RSI

0x2316ee MOV	%R15,%RAX

0x2316f1 SUB	%RCX,%RAX

0x2316f4 MOV	%RDX,-0x40(%RBP)

0x2316f8 INC	%RAX

0x2316fb MOV	%R8,-0xa0(%RBP)

0x231702 CMP	$0x4,%RAX

0x231706 JB	231b40

0x23170c MOV	%RAX,%RDX

0x23170f VPBROADCASTQ	%RBX,%YMM1

0x231715 MOV	%RAX,-0x88(%RBP)

0x23171c MOV	-0x70(%RBP),%RAX

0x231720 MOV	-0x50(%RBP),%RBX

0x231724 VPBROADCASTQ	%RCX,%YMM0

0x23172a VPADDQ	-0x20452(%RIP),%YMM0,%YMM0

0x231732 VPBROADCASTQ	-0x2056b(%RIP),%YMM12

0x23173b VPBROADCASTD	%R14D,%XMM2

0x231741 MOV	-0x48(%RBP),%R14

0x231745 AND	$-0x4,%RDX

0x231749 VPBROADCASTD	%R12D,%XMM5

0x23174f VPBROADCASTQ	%R13,%YMM6

0x231755 VPBROADCASTQ	%R8,%YMM10

0x23175b MOV	%R12,-0x98(%RBP)

0x231762 MOV	%R13,-0x90(%RBP)

0x231769 ADD	%RDX,%RCX

0x23176c VEXTRACTI128	$0x1,%YMM1,%XMM11

0x231772 MOV	%RDX,-0x80(%RBP)

0x231776 VPBROADCASTD	%EAX,%XMM3

0x23177c MOV	-0x68(%RBP),%RAX

0x231780 VPBROADCASTQ	%RBX,%YMM4

0x231786 MOV	-0x40(%RBP),%RBX

0x23178a VPBROADCASTQ	%R14,%YMM8

0x231790 VPBROADCASTD	%EAX,%XMM7

0x231796 VPBROADCASTQ	%RBX,%YMM9

0x23179c NOPL	(%RAX)

(140) 0x2317a0 VEXTRACTI128	$0x1,%YMM0,%XMM13

(140) 0x2317a6 MOV	%RDX,-0xc0(%RBP)

(140) 0x2317ad VPEXTRQ	$0x1,%XMM11,%R8

(140) 0x2317b3 VPEXTRQ	$0x1,%XMM13,%RAX

(140) 0x2317b9 CQTO

(140) 0x2317bb IDIV	%R8

(140) 0x2317be VMOVQ	%XMM11,%R8

(140) 0x2317c3 VMOVQ	%RAX,%XMM14

(140) 0x2317c8 VMOVQ	%XMM13,%RAX

(140) 0x2317cd CQTO

(140) 0x2317cf IDIV	%R8

(140) 0x2317d2 VPEXTRQ	$0x1,%XMM1,%R8

(140) 0x2317d8 VMOVQ	%RAX,%XMM13

(140) 0x2317dd VPEXTRQ	$0x1,%XMM0,%RAX

(140) 0x2317e3 CQTO

(140) 0x2317e5 VPUNPCKLQDQ	%XMM14,%XMM13,%XMM13

(140) 0x2317ea IDIV	%R8

(140) 0x2317ed VMOVQ	%XMM1,%R8

(140) 0x2317f2 VMOVQ	%RAX,%XMM14

(140) 0x2317f7 VMOVQ	%XMM0,%RAX

(140) 0x2317fc CQTO

(140) 0x2317fe IDIV	%R8

(140) 0x231801 VMOVQ	%RAX,%XMM15

(140) 0x231806 VPUNPCKLQDQ	%XMM14,%XMM15,%XMM14

(140) 0x23180b VINSERTI128	$0x1,%XMM13,%YMM14,%YMM13

(140) 0x231811 VPMOVQD	%YMM13,%XMM15

(140) 0x231817 VPMULLQ	%YMM1,%YMM13,%YMM13

(140) 0x23181d VPSUBQ	%YMM13,%YMM0,%YMM13

(140) 0x231822 VPADDQ	%YMM0,%YMM12,%YMM0

(140) 0x231826 VPMOVQD	%YMM13,%XMM16

(140) 0x23182c VPADDD	%XMM2,%XMM15,%XMM14

(140) 0x231830 VPADDD	%XMM5,%XMM15,%XMM15

(140) 0x231834 VPMOVSXDQ	%XMM14,%YMM14

(140) 0x231839 VPMOVSXDQ	%XMM15,%YMM15

(140) 0x23183e VPMULLQ	%YMM14,%YMM4,%YMM17

(140) 0x231844 VPMULLQ	%YMM15,%YMM6,%YMM15

(140) 0x23184a VPADDD	%XMM16,%XMM3,%XMM13

(140) 0x231850 VPADDD	%XMM16,%XMM7,%XMM16

(140) 0x231856 VPMOVSXDQ	%XMM13,%YMM13

(140) 0x23185b VPMOVSXDQ	%XMM16,%YMM16

(140) 0x231861 VPADDQ	%YMM13,%YMM17,%YMM17

(140) 0x231867 VPADDQ	%YMM13,%YMM15,%YMM15

(140) 0x23186c VMOVQ	%XMM17,%RAX

(140) 0x231872 VPEXTRQ	$0x1,%XMM17,%RDX

(140) 0x231879 VEXTRACTI32X4	$0x1,%YMM17,%XMM17

(140) 0x231880 VMOVQ	%XMM17,%R8

(140) 0x231886 VMOVSD	(%RDI,%RAX,8),%XMM18

(140) 0x23188d VPEXTRQ	$0x1,%XMM17,%R14

(140) 0x231894 VMOVQ	%XMM15,%RAX

(140) 0x231899 VMOVSD	(%RDI,%R8,8),%XMM17

(140) 0x2318a0 VMOVHPD	(%RDI,%RDX,8),%XMM18,%XMM18

(140) 0x2318a7 VPEXTRQ	$0x1,%XMM15,%RDX

(140) 0x2318ad VEXTRACTI128	$0x1,%YMM15,%XMM15

(140) 0x2318b3 MOV	%RAX,-0xb8(%RBP)

(140) 0x2318ba VMOVHPD	(%RDI,%R14,8),%XMM17,%XMM17

(140) 0x2318c1 VMOVQ	%XMM15,%R12

(140) 0x2318c6 VPEXTRQ	$0x1,%XMM15,%R8

(140) 0x2318cc MOV	%RDX,-0xb0(%RBP)

(140) 0x2318d3 VMOVSD	(%R9,%R12,8),%XMM15

(140) 0x2318d9 MOV	%R8,-0xa8(%RBP)

(140) 0x2318e0 VMOVHPD	(%R9,%R8,8),%XMM15,%XMM15

(140) 0x2318e6 VINSERTF32X4	$0x1,%XMM17,%YMM18,%YMM17

(140) 0x2318ed VMOVSD	(%R9,%RAX,8),%XMM18

(140) 0x2318f4 VMOVHPD	(%R9,%RDX,8),%XMM18,%XMM18

(140) 0x2318fb VINSERTF32X4	$0x1,%XMM15,%YMM18,%YMM15

(140) 0x231902 VADDPD	%YMM17,%YMM15,%YMM15

(140) 0x231908 VPMULLQ	%YMM14,%YMM6,%YMM17

(140) 0x23190e VPADDQ	%YMM13,%YMM17,%YMM17

(140) 0x231914 VMOVQ	%XMM17,%R13

(140) 0x23191a VPEXTRQ	$0x1,%XMM17,%R14

(140) 0x231921 VEXTRACTI32X4	$0x1,%YMM17,%XMM17

(140) 0x231928 VMOVQ	%XMM17,%R8

(140) 0x23192e VMOVSD	(%R9,%R13,8),%XMM18

(140) 0x231935 VPEXTRQ	$0x1,%XMM17,%RDX

(140) 0x23193c VMOVSD	(%R9,%R8,8),%XMM17

(140) 0x231943 VMOVHPD	(%R9,%R14,8),%XMM18,%XMM18

(140) 0x23194a VMOVHPD	(%R9,%RDX,8),%XMM17,%XMM17

(140) 0x231951 VINSERTF32X4	$0x1,%XMM17,%YMM18,%YMM17

(140) 0x231958 VPMULLQ	%YMM14,%YMM8,%YMM18

(140) 0x23195e VPADDQ	%YMM16,%YMM18,%YMM16

(140) 0x231964 VEXTRACTI32X4	$0x1,%YMM16,%XMM19

(140) 0x23196b VMOVQ	%XMM19,%RBX

(140) 0x231971 VPEXTRQ	$0x1,%XMM19,%RAX

(140) 0x231978 VMOVSD	(%R11,%RBX,8),%XMM19

(140) 0x23197f VMOVQ	%XMM16,%RBX

(140) 0x231985 VMOVHPD	(%R11,%RAX,8),%XMM19,%XMM19

(140) 0x23198c VPEXTRQ	$0x1,%XMM16,%RAX

(140) 0x231993 VMOVSD	(%R11,%RBX,8),%XMM16

(140) 0x23199a VMOVHPD	(%R11,%RAX,8),%XMM16,%XMM16

(140) 0x2319a1 VINSERTF32X4	$0x1,%XMM19,%YMM16,%YMM16

(140) 0x2319a8 VADDPD	%YMM16,%YMM15,%YMM15

(140) 0x2319ae VPADDQ	%YMM13,%YMM18,%YMM16

(140) 0x2319b4 VEXTRACTI32X4	$0x1,%YMM16,%XMM18

(140) 0x2319bb VPEXTRQ	$0x1,%XMM16,%RAX

(140) 0x2319c2 VMOVQ	%XMM18,%RBX

(140) 0x2319c8 VMOVSD	(%R11,%RBX,8),%XMM19

(140) 0x2319cf VPEXTRQ	$0x1,%XMM18,%RBX

(140) 0x2319d6 VMOVHPD	(%R11,%RBX,8),%XMM19,%XMM18

(140) 0x2319dd VMOVQ	%XMM16,%RBX

(140) 0x2319e3 VMOVSD	(%R11,%RBX,8),%XMM16

(140) 0x2319ea VMOVHPD	(%R11,%RAX,8),%XMM16,%XMM16

(140) 0x2319f1 VINSERTF32X4	$0x1,%XMM18,%YMM16,%YMM16

(140) 0x2319f8 VADDPD	%YMM16,%YMM17,%YMM16

(140) 0x2319fe VSUBPD	%YMM16,%YMM15,%YMM15

(140) 0x231a04 VPMULLQ	%YMM14,%YMM9,%YMM16

(140) 0x231a0a VPMULLQ	%YMM14,%YMM10,%YMM14

(140) 0x231a10 VPADDQ	%YMM13,%YMM16,%YMM16

(140) 0x231a16 VPADDQ	%YMM13,%YMM14,%YMM13

(140) 0x231a1b VMOVQ	%XMM16,%RAX

(140) 0x231a21 VPEXTRQ	$0x1,%XMM16,%RBX

(140) 0x231a28 VEXTRACTI32X4	$0x1,%YMM16,%XMM16

(140) 0x231a2f VMOVLPD	%XMM15,(%R10,%RAX,8)

(140) 0x231a35 VMOVHPD	%XMM15,(%R10,%RBX,8)

(140) 0x231a3b VMOVQ	%XMM16,%RAX

(140) 0x231a41 VPEXTRQ	$0x1,%XMM16,%RBX

(140) 0x231a48 VEXTRACTF32X4	$0x1,%YMM15,%XMM16

(140) 0x231a4f VMOVLPD	%XMM16,(%R10,%RAX,8)

(140) 0x231a56 MOV	-0xa8(%RBP),%RAX

(140) 0x231a5d VMOVHPD	%XMM16,(%R10,%RBX,8)

(140) 0x231a64 VMOVSD	(%R9,%R12,8),%XMM16

(140) 0x231a6b VMOVSD	(%R9,%R8,8),%XMM18

(140) 0x231a72 VMOVSD	(%R9,%R13,8),%XMM19

(140) 0x231a79 VMOVHPD	(%R9,%RDX,8),%XMM18,%XMM18

(140) 0x231a80 MOV	-0xc0(%RBP),%RDX

(140) 0x231a87 VMOVHPD	(%R9,%RAX,8),%XMM16,%XMM16

(140) 0x231a8e MOV	-0xb8(%RBP),%RAX

(140) 0x231a95 ADD	$-0x4,%RDX

(140) 0x231a99 VMOVSD	(%R9,%RAX,8),%XMM17

(140) 0x231aa0 MOV	-0xb0(%RBP),%RAX

(140) 0x231aa7 VMOVHPD	(%R9,%RAX,8),%XMM17,%XMM17

(140) 0x231aae VMOVQ	%XMM13,%RAX

(140) 0x231ab3 VINSERTF32X4	$0x1,%XMM16,%YMM17,%YMM16

(140) 0x231aba VMOVHPD	(%R9,%R14,8),%XMM19,%XMM17

(140) 0x231ac1 VSUBPD	%YMM16,%YMM15,%YMM15

(140) 0x231ac7 VINSERTF32X4	$0x1,%XMM18,%YMM17,%YMM17

(140) 0x231ace VADDPD	%YMM17,%YMM15,%YMM15

(140) 0x231ad4 VMOVLPD	%XMM15,(%RSI,%RAX,8)

(140) 0x231ad9 VPEXTRQ	$0x1,%XMM13,%RAX

(140) 0x231adf VEXTRACTI128	$0x1,%YMM13,%XMM13

(140) 0x231ae5 VEXTRACTF128	$0x1,%YMM15,%XMM14

(140) 0x231aeb VMOVHPD	%XMM15,(%RSI,%RAX,8)

(140) 0x231af0 VMOVQ	%XMM13,%RAX

(140) 0x231af5 VMOVLPD	%XMM14,(%RSI,%RAX,8)

(140) 0x231afa VPEXTRQ	$0x1,%XMM13,%RAX

(140) 0x231b00 VMOVHPD	%XMM14,(%RSI,%RAX,8)

(140) 0x231b05 JNE	2317a0

0x231b0b MOV	-0x80(%RBP),%RAX

0x231b0f MOV	-0x98(%RBP),%R12

0x231b16 MOV	-0x60(%RBP),%RBX

0x231b1a MOV	-0x58(%RBP),%R14

0x231b1e MOV	-0x90(%RBP),%R13

0x231b25 CMP	%RAX,-0x88(%RBP)

0x231b2c JE	231bf5

0x231b32 NOPW	%CS:(%RAX,%RAX,1)

(139) 0x231b40 MOV	%RCX,%RAX

(139) 0x231b43 CQTO

(139) 0x231b45 IDIV	%RBX

(139) 0x231b48 MOV	-0x70(%RBP),%R8

(139) 0x231b4c ADD	%EDX,%R8D

(139) 0x231b4f ADD	-0x68(%RBP),%EDX

(139) 0x231b52 MOVSXD	%R8D,%R8

(139) 0x231b55 MOVSXD	%EDX,%RDX

(139) 0x231b58 LEA	(%R14,%RAX,1),%EBX

(139) 0x231b5c MOV	-0x50(%RBP),%R14

(139) 0x231b60 ADD	%R12D,%EAX

(139) 0x231b63 CLTQ

(139) 0x231b65 MOVSXD	%EBX,%RBX

(139) 0x231b68 IMUL	%R13,%RAX

(139) 0x231b6c IMUL	%RBX,%R14

(139) 0x231b70 ADD	%R8,%RAX

(139) 0x231b73 VMOVSD	(%R9,%RAX,8),%XMM0

(139) 0x231b79 ADD	%R8,%R14

(139) 0x231b7c VADDSD	(%RDI,%R14,8),%XMM0,%XMM0

(139) 0x231b82 MOV	-0x48(%RBP),%R14

(139) 0x231b86 IMUL	%RBX,%R14

(139) 0x231b8a ADD	%R14,%RDX

(139) 0x231b8d ADD	%R8,%R14

(139) 0x231b90 VADDSD	(%R11,%RDX,8),%XMM0,%XMM0

(139) 0x231b96 MOV	%R13,%RDX

(139) 0x231b99 IMUL	%RBX,%RDX

(139) 0x231b9d ADD	%R8,%RDX

(139) 0x231ba0 VMOVSD	(%R9,%RDX,8),%XMM1

(139) 0x231ba6 VADDSD	(%R11,%R14,8),%XMM1,%XMM1

(139) 0x231bac MOV	-0x40(%RBP),%R14

(139) 0x231bb0 IMUL	%RBX,%R14

(139) 0x231bb4 ADD	%R8,%R14

(139) 0x231bb7 VSUBSD	%XMM1,%XMM0,%XMM0

(139) 0x231bbb VMOVSD	%XMM0,(%R10,%R14,8)

(139) 0x231bc1 MOV	-0x58(%RBP),%R14

(139) 0x231bc5 VSUBSD	(%R9,%RAX,8),%XMM0,%XMM0

(139) 0x231bcb MOV	-0xa0(%RBP),%RAX

(139) 0x231bd2 VADDSD	(%R9,%RDX,8),%XMM0,%XMM0

(139) 0x231bd8 IMUL	%RAX,%RBX

(139) 0x231bdc ADD	%R8,%RBX

(139) 0x231bdf VMOVSD	%XMM0,(%RSI,%RBX,8)

(139) 0x231be4 MOV	-0x60(%RBP),%RBX

(139) 0x231be8 CMP	%R15,%RCX

(139) 0x231beb LEA	0x1(%RCX),%RCX

(139) 0x231bef JL	231b40

0x231bf5 MOV	-0x34(%RBP),%ESI

0x231bf8 LEA	0x28e39(%RIP),%RDI

0x231bff VZEROUPPER

0x231c02 CALL	259690 <@plt_start@+0x540>

0x231c07 ADD	$0xa8,%RSP

0x231c0e POP	%RBX

0x231c0f POP	%R12

0x231c11 POP	%R13

0x231c13 POP	%R14

0x231c15 POP	%R15

0x231c17 POP	%RBP

0x231c18 RET

0x231c19 NOPL	(%RAX)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.13 to 6.50 cycles (2.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

5% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

6% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
VPBROADCASTD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
VPBROADCASTQ: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 288 bytes. The binary function is storing 136 bytes.

General properties

nb instructions	126
nb uops	137
loop length	544
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	8
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.13 cycles
front end	17.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	14.00	14.00	14.00	14.00	0.50	6.50	6.50	0.50	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	14.00	14.00	14.00	14.00	0.50	6.50	6.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.13
Dispatch	14.00
Overall L1	17.13

Vectorization ratios

all	5%
load	6%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

all	11%
load	14%
store	11%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.13 cycles. At this rate:

6% of peak load performance is reached (16.82 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.94 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 17.13 to 14.00 cycles (1.22x speedup).

ASM code

In the binary file, the address of the function is: 2315e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 231c07 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x627>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 231c07 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x627>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%R12),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %ECX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RCX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
IMUL %RBX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA -0xc8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x293b7(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x78(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 231bf5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x615>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R13,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RSI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R10,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 231b40 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x560>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RBX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x20452(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x2056b(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
VPBROADCASTD %R14D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x48(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTD %R12D,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %R13,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R8,%YMM10	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R12,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTD %EAX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RBX,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x40(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %R14,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %EAX,%XMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RBX,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x98(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x58(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x90(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,-0x88(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 231bf5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x615>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x28e39(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_cell.cpp:136-140
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136-140
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 17.13 to 6.50 cycles (2.63x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

5% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

6% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
16% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
9% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:136

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
VPBROADCASTD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
VPBROADCASTQ: 7 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:137

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 288 bytes. The binary function is storing 136 bytes.

General properties

nb instructions	126
nb uops	137
loop length	544
used x86 registers	16
used mmx registers	0
used xmm registers	5
used ymm registers	8
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	17.13 cycles
front end	17.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.50	6.50	6.50	6.50	6.50	6.50	14.00	14.00	14.00	14.00	0.50	6.50	6.50	0.50	0.00	0.00
cycles	6.50	6.50	6.50	6.50	6.50	6.50	14.00	14.00	14.00	14.00	0.50	6.50	6.50	0.50	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.13
Dispatch	14.00
Overall L1	17.13

Vectorization ratios

all	5%
load	6%
store	0%
mul	0%
add-sub	16%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Vector efficiency ratios

all	11%
load	14%
store	11%
mul	12%
add-sub	14%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 17.13 cycles. At this rate:

6% of peak load performance is reached (16.82 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
6% of peak store performance is reached (7.94 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 2315e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 231c07 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x627>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
ADD $0x4,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JG 231c07 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x627>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
LEA -0x1(%RAX),%ECX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x1(%R12),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xc8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
SUB %ECX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RCX,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
IMUL %RBX,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x38(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %RAX,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
LEA -0xc8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x293b7(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x78(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x30(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x34(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x78(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 231bf5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x615>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x28(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R13,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R14,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R8),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RSI),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R9,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R10,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RAX),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8,-0xa0(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 231b40 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x560>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
VPBROADCASTQ %RBX,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %RAX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV -0x70(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x50(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x20452(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x2056b(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
VPBROADCASTD %R14D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x48(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
AND $-0x4,%RDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTD %R12D,%XMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %R13,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R8,%YMM10	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV %R12,-0x98(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
ADD %RDX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RDX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTD %EAX,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x68(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RBX,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x40(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %R14,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %EAX,%XMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RBX,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x80(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x98(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x60(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x58(%RBP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x90(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,-0x88(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 231bf5 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.8+0x615>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x34(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x28e39(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0xa8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	1.50	0.56
○Loop 140 - advec_cell.cpp:137-140 - exec	1.50	0.56
○Loop 139 - advec_cell.cpp:137-140 - exec	0.00	0.00

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512-bits vectorization

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Matching between your function (in the source code) and the binary function

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ASM code

Code clean check

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Vectorization

Details

Workaround

Execution units bottlenecks

512-bits vectorization

Workaround

CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code