OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:117-125 [...]	Coverage (incl. loops): 3.49% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 117 - 125

--------------------------------------------------------------------------------

117: #pragma omp parallel for simd collapse(2)

118:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

119:       for (int i = (x_min + 1); i < (x_max + 2); i++) {

120:         double pre_mass_s = density1(i, j) * pre_vol(i, j);

121:         double post_mass_s = pre_mass_s + mass_flux_x(i, j) - mass_flux_x(i + 1, j + 0);

122:         double post_ener_s = (energy1(i, j) * pre_mass_s + ener_flux(i, j) - ener_flux(i + 1, j + 0)) / post_mass_s;

123:         double advec_vol_s = pre_vol(i, j) + vol_flux_x(i, j) - vol_flux_x(i + 1, j + 0);

124:         density1(i, j) = post_mass_s / advec_vol_s;

125:         energy1(i, j) = post_ener_s;

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x230f00 PUSH	%RBP

0x230f01 MOV	%RSP,%RBP

0x230f04 PUSH	%R15

0x230f06 PUSH	%R14

0x230f08 PUSH	%R13

0x230f0a PUSH	%R12

0x230f0c PUSH	%RBX

0x230f0d SUB	$0x98,%RSP

0x230f14 MOV	(%RCX),%R15D

0x230f17 MOV	(%RDX),%R14D

0x230f1a INC	%R14D

0x230f1d ADD	$0x2,%R15D

0x230f21 SUB	%R14D,%R15D

0x230f24 JLE	2315c0

0x230f2a MOV	(%R9),%R13D

0x230f2d MOV	(%R8),%R12D

0x230f30 INC	%R12D

0x230f33 ADD	$0x2,%R13D

0x230f37 CMP	%R12D,%R13D

0x230f3a JLE	2315c0

0x230f40 SUB	%R12D,%R13D

0x230f43 MOV	(%RDI),%ESI

0x230f45 MOVQ	$0,-0x70(%RBP)

0x230f4d MOVQ	$0x1,-0xb8(%RBP)

0x230f58 MOVL	$0,-0x40(%RBP)

0x230f5f IMUL	%R13,%R15

0x230f63 DEC	%R15

0x230f66 MOV	%R15,-0x38(%RBP)

0x230f6a SUB	$0x8,%RSP

0x230f6e LEA	-0x40(%RBP),%RCX

0x230f72 LEA	-0xb8(%RBP),%RAX

0x230f79 LEA	0x29a58(%RIP),%RDI

0x230f80 LEA	-0x70(%RBP),%R8

0x230f84 LEA	-0x38(%RBP),%R9

0x230f88 MOV	%ESI,-0x3c(%RBP)

0x230f8b MOV	$0x22,%EDX

0x230f90 PUSH	$0x1

0x230f92 PUSH	$0x1

0x230f94 PUSH	%RAX

0x230f95 CALL	259680 <@plt_start@+0x530>

0x230f9a ADD	$0x20,%RSP

0x230f9e MOV	-0x38(%RBP),%RAX

0x230fa2 MOV	-0x70(%RBP),%RCX

0x230fa6 CMP	%R15,%RAX

0x230fa9 CMOVL	%RAX,%R15

0x230fad MOV	%R15,-0x38(%RBP)

0x230fb1 CMP	%R15,%RCX

0x230fb4 JG	2315ae

0x230fba MOV	0x18(%RBP),%R9

0x230fbe MOV	0x20(%RBP),%RDI

0x230fc2 MOV	0x10(%RBP),%R8

0x230fc6 MOV	0x28(%RBP),%RSI

0x230fca MOV	0x38(%RBP),%RAX

0x230fce MOV	0x30(%RBP),%RDX

0x230fd2 MOV	%R14D,-0x30(%RBP)

0x230fd6 MOV	%R12D,-0x2c(%RBP)

0x230fda MOV	%R13,-0x68(%RBP)

0x230fde MOV	(%R9),%R11

0x230fe1 MOV	(%R8),%R10

0x230fe4 MOV	0x10(%RDI),%RBX

0x230fe8 MOV	0x10(%R8),%R8

0x230fec MOV	%R11,-0x58(%RBP)

0x230ff0 MOV	(%RDI),%R11

0x230ff3 MOV	(%RSI),%RDI

0x230ff6 MOV	%R10,-0x60(%RBP)

0x230ffa MOV	0x10(%R9),%R10

0x230ffe MOV	0x10(%RSI),%R9

0x231002 MOV	(%RDX),%RSI

0x231005 MOV	%R11,-0x50(%RBP)

0x231009 MOV	%RDI,-0x48(%RBP)

0x23100d MOV	0x10(%RDX),%RDI

0x231011 MOV	(%RAX),%RDX

0x231014 MOV	0x10(%RAX),%R11

0x231018 MOV	%R15,%RAX

0x23101b SUB	%RCX,%RAX

0x23101e MOV	%RSI,-0x90(%RBP)

0x231025 INC	%RAX

0x231028 MOV	%RDX,-0x88(%RBP)

0x23102f CMP	$0x4,%RAX

0x231033 JB	2314e0

0x231039 VPBROADCASTQ	%R13,%YMM1

0x23103f VPBROADCASTD	%R12D,%XMM3

0x231045 MOV	-0x60(%RBP),%R13

0x231049 MOV	-0x58(%RBP),%R12

0x23104d VPBROADCASTQ	%RCX,%YMM0

0x231053 VPADDQ	-0x1fd7b(%RIP),%YMM0,%YMM0

0x23105b VPBROADCASTQ	-0x1fe94(%RIP),%YMM12

0x231064 MOV	%RAX,-0x80(%RBP)

0x231068 AND	$-0x4,%RAX

0x23106c VPBROADCASTD	%R14D,%XMM2

0x231072 VPBROADCASTQ	%RSI,%YMM8

0x231078 VPBROADCASTQ	%RDX,%YMM9

0x23107e VPCMPEQD	%XMM11,%XMM11,%XMM11

0x231083 ADD	%RAX,%RCX

0x231086 VEXTRACTI128	$0x1,%YMM1,%XMM10

0x23108c MOV	%RAX,-0x78(%RBP)

0x231090 VPBROADCASTQ	%R13,%YMM4

0x231096 VPBROADCASTQ	%R12,%YMM5

0x23109c MOV	-0x50(%RBP),%R13

0x2310a0 MOV	-0x48(%RBP),%R12

0x2310a4 VPBROADCASTQ	%R13,%YMM6

0x2310aa VPBROADCASTQ	%R12,%YMM7

(138) 0x2310b0 VEXTRACTI128	$0x1,%YMM0,%XMM13

(138) 0x2310b6 MOV	%RAX,-0xb0(%RBP)

(138) 0x2310bd VPEXTRQ	$0x1,%XMM10,%RSI

(138) 0x2310c3 VMOVQ	%XMM10,%R13

(138) 0x2310c8 VPEXTRQ	$0x1,%XMM13,%RAX

(138) 0x2310ce CQTO

(138) 0x2310d0 IDIV	%RSI

(138) 0x2310d3 MOV	%RAX,%RSI

(138) 0x2310d6 VMOVQ	%XMM13,%RAX

(138) 0x2310db VMOVQ	%RSI,%XMM13

(138) 0x2310e0 VPEXTRQ	$0x1,%XMM1,%RSI

(138) 0x2310e6 CQTO

(138) 0x2310e8 IDIV	%R13

(138) 0x2310eb VMOVQ	%RAX,%XMM14

(138) 0x2310f0 VPEXTRQ	$0x1,%XMM0,%RAX

(138) 0x2310f6 CQTO

(138) 0x2310f8 VPUNPCKLQDQ	%XMM13,%XMM14,%XMM13

(138) 0x2310fd IDIV	%RSI

(138) 0x231100 VMOVQ	%XMM1,%RSI

(138) 0x231105 VMOVQ	%RAX,%XMM14

(138) 0x23110a VMOVQ	%XMM0,%RAX

(138) 0x23110f CQTO

(138) 0x231111 IDIV	%RSI

(138) 0x231114 VMOVQ	%RAX,%XMM15

(138) 0x231119 VPUNPCKLQDQ	%XMM14,%XMM15,%XMM14

(138) 0x23111e VINSERTI128	$0x1,%XMM13,%YMM14,%YMM13

(138) 0x231124 VPMOVQD	%YMM13,%XMM14

(138) 0x23112a VPMULLQ	%YMM1,%YMM13,%YMM13

(138) 0x231130 VPSUBQ	%YMM13,%YMM0,%YMM13

(138) 0x231135 VPADDQ	%YMM0,%YMM12,%YMM0

(138) 0x231139 VPMOVQD	%YMM13,%XMM13

(138) 0x23113f VPADDD	%XMM2,%XMM14,%XMM15

(138) 0x231143 VPMOVSXDQ	%XMM15,%YMM15

(138) 0x231148 VPMULLQ	%YMM15,%YMM6,%YMM19

(138) 0x23114e VPADDD	%XMM13,%XMM3,%XMM17

(138) 0x231154 VPMULLQ	%YMM15,%YMM4,%YMM13

(138) 0x23115a VPMOVSXDQ	%XMM17,%YMM14

(138) 0x231160 VPSUBD	%XMM11,%XMM17,%XMM17

(138) 0x231166 VPADDQ	%YMM14,%YMM13,%YMM13

(138) 0x23116b VMOVQ	%XMM13,%RAX

(138) 0x231170 VPEXTRQ	$0x1,%XMM13,%R14

(138) 0x231176 VEXTRACTI128	$0x1,%YMM13,%XMM13

(138) 0x23117c VMOVQ	%XMM13,%RDX

(138) 0x231181 VPEXTRQ	$0x1,%XMM13,%RSI

(138) 0x231187 VMOVSD	(%R8,%RAX,8),%XMM16

(138) 0x23118e MOV	%RAX,-0xa8(%RBP)

(138) 0x231195 MOV	%R14,-0x98(%RBP)

(138) 0x23119c VMOVSD	(%R8,%RDX,8),%XMM13

(138) 0x2311a2 VMOVHPD	(%R8,%R14,8),%XMM16,%XMM16

(138) 0x2311a9 MOV	%RSI,-0xa0(%RBP)

(138) 0x2311b0 VMOVHPD	(%R8,%RSI,8),%XMM13,%XMM13

(138) 0x2311b6 MOV	-0xa8(%RBP),%RSI

(138) 0x2311bd VINSERTF32X4	$0x1,%XMM13,%YMM16,%YMM13

(138) 0x2311c4 VPMULLQ	%YMM15,%YMM5,%YMM16

(138) 0x2311ca VPADDQ	%YMM14,%YMM16,%YMM16

(138) 0x2311d0 VMOVQ	%XMM16,%RAX

(138) 0x2311d6 VPEXTRQ	$0x1,%XMM16,%R13

(138) 0x2311dd VEXTRACTI32X4	$0x1,%YMM16,%XMM16

(138) 0x2311e4 VMOVQ	%XMM16,%R12

(138) 0x2311ea VMOVSD	(%R10,%RAX,8),%XMM18

(138) 0x2311f1 VPEXTRQ	$0x1,%XMM16,%R14

(138) 0x2311f8 VMOVSD	(%R10,%R12,8),%XMM16

(138) 0x2311ff VMOVHPD	(%R10,%R13,8),%XMM18,%XMM18

(138) 0x231206 VMOVHPD	(%R10,%R14,8),%XMM16,%XMM16

(138) 0x23120d VINSERTF32X4	$0x1,%XMM16,%YMM18,%YMM16

(138) 0x231214 VPADDQ	%YMM14,%YMM19,%YMM18

(138) 0x23121a VMOVQ	%XMM18,%RAX

(138) 0x231220 VPEXTRQ	$0x1,%XMM18,%R14

(138) 0x231227 VEXTRACTI32X4	$0x1,%YMM18,%XMM18

(138) 0x23122e VMOVQ	%XMM18,%R12

(138) 0x231234 VMOVSD	(%RBX,%RAX,8),%XMM20

(138) 0x23123b VPEXTRQ	$0x1,%XMM18,%R13

(138) 0x231242 VMULPD	%YMM13,%YMM16,%YMM13

(138) 0x231248 VMOVSD	(%RBX,%R12,8),%XMM18

(138) 0x23124f VMOVHPD	(%RBX,%R14,8),%XMM20,%XMM20

(138) 0x231256 VMOVHPD	(%RBX,%R13,8),%XMM18,%XMM18

(138) 0x23125d VINSERTF32X4	$0x1,%XMM18,%YMM20,%YMM18

(138) 0x231264 VADDPD	%YMM13,%YMM18,%YMM20

(138) 0x23126a VPMOVSXDQ	%XMM17,%YMM18

(138) 0x231270 VPADDQ	%YMM18,%YMM19,%YMM17

(138) 0x231276 VMOVQ	%XMM17,%RAX

(138) 0x23127c VPEXTRQ	$0x1,%XMM17,%R14

(138) 0x231283 VEXTRACTI32X4	$0x1,%YMM17,%XMM17

(138) 0x23128a VMOVQ	%XMM17,%R12

(138) 0x231290 VMOVSD	(%RBX,%RAX,8),%XMM19

(138) 0x231297 VPEXTRQ	$0x1,%XMM17,%R13

(138) 0x23129e VMOVSD	(%RBX,%R12,8),%XMM17

(138) 0x2312a5 VMOVHPD	(%RBX,%R14,8),%XMM19,%XMM19

(138) 0x2312ac VMOVHPD	(%RBX,%R13,8),%XMM17,%XMM17

(138) 0x2312b3 VINSERTF32X4	$0x1,%XMM17,%YMM19,%YMM17

(138) 0x2312ba VPMULLQ	%YMM15,%YMM7,%YMM19

(138) 0x2312c0 VSUBPD	%YMM17,%YMM20,%YMM17

(138) 0x2312c6 VPMULLQ	%YMM15,%YMM8,%YMM20

(138) 0x2312cc VPMULLQ	%YMM15,%YMM9,%YMM15

(138) 0x2312d2 VPADDQ	%YMM14,%YMM19,%YMM19

(138) 0x2312d8 VMOVQ	%XMM19,%RAX

(138) 0x2312de VPEXTRQ	$0x1,%XMM19,%R13

(138) 0x2312e5 VEXTRACTI32X4	$0x1,%YMM19,%XMM19

(138) 0x2312ec VPADDQ	%YMM14,%YMM20,%YMM21

(138) 0x2312f2 VPADDQ	%YMM18,%YMM20,%YMM20

(138) 0x2312f8 VPADDQ	%YMM14,%YMM15,%YMM14

(138) 0x2312fd VPADDQ	%YMM18,%YMM15,%YMM15

(138) 0x231303 VEXTRACTI32X4	$0x1,%YMM21,%XMM22

(138) 0x23130a VMOVQ	%XMM21,%R14

(138) 0x231310 VEXTRACTI32X4	$0x1,%YMM15,%XMM18

(138) 0x231317 VMOVQ	%XMM22,%R12

(138) 0x23131d VMOVSD	(%RDI,%R12,8),%XMM23

(138) 0x231324 VPEXTRQ	$0x1,%XMM22,%R12

(138) 0x23132b VMOVHPD	(%RDI,%R12,8),%XMM23,%XMM22

(138) 0x231332 VPEXTRQ	$0x1,%XMM21,%R12

(138) 0x231339 VMOVSD	(%RDI,%R14,8),%XMM21

(138) 0x231340 VEXTRACTI32X4	$0x1,%YMM20,%XMM23

(138) 0x231347 VMOVQ	%XMM20,%R14

(138) 0x23134d VMOVHPD	(%RDI,%R12,8),%XMM21,%XMM21

(138) 0x231354 VMOVQ	%XMM23,%R12

(138) 0x23135a VMOVSD	(%RDI,%R12,8),%XMM24

(138) 0x231361 VPEXTRQ	$0x1,%XMM23,%R12

(138) 0x231368 VMOVHPD	(%RDI,%R12,8),%XMM24,%XMM23

(138) 0x23136f VEXTRACTI32X4	$0x1,%YMM14,%XMM24

(138) 0x231376 VPEXTRQ	$0x1,%XMM20,%R12

(138) 0x23137d VMOVSD	(%RDI,%R14,8),%XMM20

(138) 0x231384 VMOVQ	%XMM24,%R14

(138) 0x23138a VMOVHPD	(%RDI,%R12,8),%XMM20,%XMM20

(138) 0x231391 VPEXTRQ	$0x1,%XMM24,%R12

(138) 0x231398 VMOVSD	(%R11,%R14,8),%XMM24

(138) 0x23139f VMOVQ	%XMM14,%R14

(138) 0x2313a4 VMOVHPD	(%R11,%R12,8),%XMM24,%XMM24

(138) 0x2313ab VPEXTRQ	$0x1,%XMM14,%R12

(138) 0x2313b1 VMOVSD	(%R11,%R14,8),%XMM14

(138) 0x2313b7 VMOVQ	%XMM18,%R14

(138) 0x2313bd VMOVHPD	(%R11,%R12,8),%XMM14,%XMM14

(138) 0x2313c3 VPEXTRQ	$0x1,%XMM18,%R12

(138) 0x2313ca VMOVSD	(%R11,%R14,8),%XMM18

(138) 0x2313d1 VMOVQ	%XMM15,%R14

(138) 0x2313d6 VMOVHPD	(%R11,%R12,8),%XMM18,%XMM18

(138) 0x2313dd VPEXTRQ	$0x1,%XMM15,%R12

(138) 0x2313e3 VMOVSD	(%R11,%R14,8),%XMM15

(138) 0x2313e9 VMOVQ	%XMM19,%R14

(138) 0x2313ef VMOVHPD	(%R11,%R12,8),%XMM15,%XMM15

(138) 0x2313f5 VPEXTRQ	$0x1,%XMM19,%R12

(138) 0x2313fc VINSERTF32X4	$0x1,%XMM24,%YMM14,%YMM14

(138) 0x231403 VADDPD	%YMM16,%YMM14,%YMM14

(138) 0x231409 VMOVSD	(%R9,%R14,8),%XMM16

(138) 0x231410 VINSERTF32X4	$0x1,%XMM18,%YMM15,%YMM15

(138) 0x231417 VMOVSD	(%R9,%RAX,8),%XMM18

(138) 0x23141e VMOVHPD	(%R9,%R12,8),%XMM16,%XMM16

(138) 0x231425 VMOVHPD	(%R9,%R13,8),%XMM18,%XMM18

(138) 0x23142c VSUBPD	%YMM15,%YMM14,%YMM14

(138) 0x231431 VINSERTF32X4	$0x1,%XMM22,%YMM21,%YMM15

(138) 0x231438 VDIVPD	%YMM14,%YMM17,%YMM14

(138) 0x23143e VINSERTF32X4	$0x1,%XMM16,%YMM18,%YMM16

(138) 0x231445 VFMADD231PD	%YMM16,%YMM13,%YMM15

(138) 0x23144b VINSERTF32X4	$0x1,%XMM23,%YMM20,%YMM13

(138) 0x231452 VSUBPD	%YMM13,%YMM15,%YMM13

(138) 0x231457 VDIVPD	%YMM17,%YMM13,%YMM13

(138) 0x23145d VMOVLPD	%XMM14,(%R8,%RSI,8)

(138) 0x231463 MOV	-0x98(%RBP),%RSI

(138) 0x23146a VMOVHPD	%XMM14,(%R8,%RSI,8)

(138) 0x231470 VEXTRACTF128	$0x1,%YMM14,%XMM14

(138) 0x231476 VMOVLPD	%XMM14,(%R8,%RDX,8)

(138) 0x23147c MOV	-0xa0(%RBP),%RDX

(138) 0x231483 VMOVHPD	%XMM14,(%R8,%RDX,8)

(138) 0x231489 VMOVLPD	%XMM13,(%R9,%RAX,8)

(138) 0x23148f MOV	-0xb0(%RBP),%RAX

(138) 0x231496 VMOVHPD	%XMM13,(%R9,%R13,8)

(138) 0x23149c VEXTRACTF128	$0x1,%YMM13,%XMM13

(138) 0x2314a2 VMOVLPD	%XMM13,(%R9,%R14,8)

(138) 0x2314a8 VMOVHPD	%XMM13,(%R9,%R12,8)

(138) 0x2314ae ADD	$-0x4,%RAX

(138) 0x2314b2 JNE	2310b0

0x2314b8 MOV	-0x78(%RBP),%RAX

0x2314bc MOV	-0x30(%RBP),%R14D

0x2314c0 MOV	-0x2c(%RBP),%R12D

0x2314c4 MOV	-0x68(%RBP),%R13

0x2314c8 CMP	%RAX,-0x80(%RBP)

0x2314cc JE	2315ae

0x2314d2 NOPW	%CS:(%RAX,%RAX,1)

(137) 0x2314e0 MOV	%RCX,%RAX

(137) 0x2314e3 CQTO

(137) 0x2314e5 IDIV	%R13

(137) 0x2314e8 ADD	%R12D,%EDX

(137) 0x2314eb MOVSXD	%EDX,%RDX

(137) 0x2314ee ADD	%R14D,%EAX

(137) 0x2314f1 MOV	-0x58(%RBP),%R14

(137) 0x2314f5 MOVSXD	%EAX,%RSI

(137) 0x2314f8 MOV	-0x60(%RBP),%RAX

(137) 0x2314fc IMUL	%RSI,%R14

(137) 0x231500 IMUL	%RSI,%RAX

(137) 0x231504 ADD	%RDX,%R14

(137) 0x231507 VMOVSD	(%R10,%R14,8),%XMM0

(137) 0x23150d MOV	-0x50(%RBP),%R14

(137) 0x231511 ADD	%RDX,%RAX

(137) 0x231514 VMULSD	(%R8,%RAX,8),%XMM0,%XMM1

(137) 0x23151a IMUL	%RSI,%R14

(137) 0x23151e LEA	(%R14,%RDX,1),%R12

(137) 0x231522 LEA	0x1(%R14,%RDX,1),%R14

(137) 0x231527 VADDSD	(%RBX,%R12,8),%XMM1,%XMM2

(137) 0x23152d MOV	-0x90(%RBP),%R12

(137) 0x231534 VSUBSD	(%RBX,%R14,8),%XMM2,%XMM2

(137) 0x23153a MOV	-0x48(%RBP),%R14

(137) 0x23153e IMUL	%RSI,%R12

(137) 0x231542 IMUL	%RSI,%R14

(137) 0x231546 IMUL	-0x88(%RBP),%RSI

(137) 0x23154e LEA	(%R12,%RDX,1),%R13

(137) 0x231552 LEA	0x1(%R12,%RDX,1),%R12

(137) 0x231557 ADD	%RDX,%R14

(137) 0x23155a VMOVSD	(%R9,%R14,8),%XMM3

(137) 0x231560 VFMADD213SD	(%RDI,%R13,8),%XMM1,%XMM3

(137) 0x231566 MOV	-0x68(%RBP),%R13

(137) 0x23156a VSUBSD	(%RDI,%R12,8),%XMM3,%XMM1

(137) 0x231570 LEA	(%RSI,%RDX,1),%R12

(137) 0x231574 LEA	0x1(%RSI,%RDX,1),%RDX

(137) 0x231579 VADDSD	(%R11,%R12,8),%XMM0,%XMM0

(137) 0x23157f MOV	-0x2c(%RBP),%R12D

(137) 0x231583 VSUBSD	(%R11,%RDX,8),%XMM0,%XMM0

(137) 0x231589 VDIVSD	%XMM2,%XMM1,%XMM1

(137) 0x23158d VDIVSD	%XMM0,%XMM2,%XMM0

(137) 0x231591 VMOVSD	%XMM0,(%R8,%RAX,8)

(137) 0x231597 VMOVSD	%XMM1,(%R9,%R14,8)

(137) 0x23159d MOV	-0x30(%RBP),%R14D

(137) 0x2315a1 CMP	%R15,%RCX

(137) 0x2315a4 LEA	0x1(%RCX),%RCX

(137) 0x2315a8 JL	2314e0

0x2315ae MOV	-0x3c(%RBP),%ESI

0x2315b1 LEA	0x29438(%RIP),%RDI

0x2315b8 VZEROUPPER

0x2315bb CALL	259690 <@plt_start@+0x540>

0x2315c0 ADD	$0x98,%RSP

0x2315c7 POP	%RBX

0x2315c8 POP	%R12

0x2315ca POP	%R13

0x2315cc POP	%R14

0x2315ce POP	%R15

0x2315d0 POP	%RBP

0x2315d1 RET

0x2315d2 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.63 to 6.00 cycles (2.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
12% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
15% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
VPBROADCASTQ: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 288 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	122
nb uops	133
loop length	522
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	9
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.63 cycles
front end	16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.33	6.33	6.33	6.33	6.33	6.33	14.00	14.00	14.00	14.00	1.00	6.00	6.00	1.00	0.00	0.00
cycles	6.33	6.33	6.33	6.33	6.33	6.33	14.00	14.00	14.00	14.00	1.00	6.00	6.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.63
Dispatch	14.00
Overall L1	16.63

Vectorization ratios

all	6%
load	5%
store	0%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

all	11%
load	12%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.63 cycles. At this rate:

6% of peak load performance is reached (17.32 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.63 to 14.00 cycles (1.19x speedup).

ASM code

In the binary file, the address of the function is: 230f00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2315c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.6+0x6c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2315c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.6+0x6c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R13,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0xb8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x29a58(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 2315ae <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.6+0x6ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R14D,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R12D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R13,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R10,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R9),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R11,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RDX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2314e0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.6+0x5e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTQ %R13,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R12D,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x60(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x58(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x1fd7b(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x1fe94(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTD %R14D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RSI,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPCMPEQD %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %R13,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R12,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x50(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x48(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %R13,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R12,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x30(%RBP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV -0x2c(%RBP),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV -0x68(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,-0x80(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 2315ae <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.6+0x6ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x29438(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_cell.cpp:117-125
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117-125
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.63 to 6.00 cycles (2.77x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions).

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
12% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
15% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:117

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
VPBROADCASTD: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
VPBROADCASTQ: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:118

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 288 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	122
nb uops	133
loop length	522
used x86 registers	16
used mmx registers	0
used xmm registers	4
used ymm registers	9
used zmm registers	0
nb stack references	22

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.63 cycles
front end	16.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.33	6.33	6.33	6.33	6.33	6.33	14.00	14.00	14.00	14.00	1.00	6.00	6.00	1.00	0.00	0.00
cycles	6.33	6.33	6.33	6.33	6.33	6.33	14.00	14.00	14.00	14.00	1.00	6.00	6.00	1.00	0.00	0.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.63
Dispatch	14.00
Overall L1	16.63

Vectorization ratios

all	6%
load	5%
store	0%
mul	0%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

Vector efficiency ratios

all	11%
load	12%
store	10%
mul	12%
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.63 cycles. At this rate:

6% of peak load performance is reached (17.32 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (7.22 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 230f00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R15D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
SUB %R14D,%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2315c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.6+0x6c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
INC %R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
ADD $0x2,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
CMP %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 2315c0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.6+0x6c0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R12D,%R13D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOVQ $0,-0x70(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,-0xb8(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,-0x40(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R13,%R15	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R15	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA -0x40(%RBP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0xb8(%RBP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x29a58(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x70(%RBP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA -0x38(%RBP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,-0x3c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV -0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x70(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
CMP %R15,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R15	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 2315ae <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.6+0x6ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x30(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R14D,-0x30(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R12D,-0x2c(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (6.3%)
MOV %R13,-0x68(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%R8),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RDI),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R11,-0x58(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV (%RSI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R10,-0x60(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R9),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RSI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RDX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV %R11,-0x50(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,-0x48(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RDX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
SUB %RCX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RSI,-0x90(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
INC %RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDX,-0x88(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
CMP $0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 2314e0 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.6+0x5e0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VPBROADCASTQ %R13,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTD %R12D,%XMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
MOV -0x60(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x58(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %RCX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPADDQ -0x1fd7b(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	1	0.50	vect (50.0%)
VPBROADCASTQ -0x1fe94(%RIP),%YMM12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	1	0.50	scal (12.5%)
MOV %RAX,-0x80(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTD %R14D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (6.3%)
VPBROADCASTQ %RSI,%YMM8	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPCMPEQD %XMM11,%XMM11,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	1	0.25	vect (25.0%)
ADD %RAX,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
VEXTRACTI128 $0x1,%YMM1,%XMM10	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	3	0.50	vect (25.0%)
MOV %RAX,-0x78(%RBP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	4	0.50	scal (12.5%)
VPBROADCASTQ %R13,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R12,%YMM5	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x50(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
MOV -0x48(%RBP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
VPBROADCASTQ %R13,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
VPBROADCASTQ %R12,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	1	1	scal (12.5%)
MOV -0x78(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
MOV -0x30(%RBP),%R14D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV -0x2c(%RBP),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (6.3%)
MOV -0x68(%RBP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	scal (12.5%)
CMP %RAX,-0x80(%RBP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25	scal (12.5%)
JE 2315ae <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.6+0x6ae>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50-1	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV -0x3c(%RBP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	3	0.25	N/A
LEA 0x29438(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0.50	N/A
ADD $0x98,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	1	0.17	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.49	1.31
○Loop 138 - advec_cell.cpp:118-125 - exec	3.49	1.30
○Loop 137 - advec_cell.cpp:118-125 - exec	0.00	0.00

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Code clean check

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Vectorization

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Execution units bottlenecks

512-bits vectorization

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CALL instructions

Details

Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code