OV - exec - Function advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D<double>&, clover::Buffer1 ...	Module: exec	Source: advec_cell.cpp:65-110 [...]	Coverage (incl. loops): 3.46% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp: 65 - 110

--------------------------------------------------------------------------------

65: #pragma omp parallel for simd collapse(2)

66:     for (int j = (y_min + 1); j < (y_max + 2); j++) {

67:       for (int i = (x_min + 1); i < (x_max + 2 + 2); i++)

68:         ({

69:           int upwind, donor, downwind, dif;

70:           double sigmat, sigma3, sigma4, sigmav, sigmam, diffuw, diffdw, limiter, wind;

71:           if (vol_flux_x(i, j) > 0.0) {

72:             upwind = i - 2;

73:             donor = i - 1;

74:             downwind = i;

75:             dif = donor;

76:           } else {

77:             upwind = std::min(i + 1, x_max + 2);

78:             donor = i;

79:             downwind = i - 1;

80:             dif = upwind;

81:           }

82:           sigmat = std::fabs(vol_flux_x(i, j)) / pre_vol(donor, j);

83:           sigma3 = (1.0 + sigmat) * (vertexdx[i] / vertexdx[dif]);

84:           sigma4 = 2.0 - sigmat;

85:           sigmav = sigmat;

86:           diffuw = density1(donor, j) - density1(upwind, j);

87:           diffdw = density1(downwind, j) - density1(donor, j);

88:           wind = 1.0;

89:           if (diffdw <= 0.0) wind = -1.0;

90:           if (diffuw * diffdw > 0.0) {

91:             limiter = (1.0 - sigmav) * wind *

92:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

93:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

94:           } else {

95:             limiter = 0.0;

96:           }

97:           mass_flux_x(i, j) = vol_flux_x(i, j) * (density1(donor, j) + limiter);

98:           sigmam = std::fabs(mass_flux_x(i, j)) / (density1(donor, j) * pre_vol(donor, j));

99:           diffuw = energy1(donor, j) - energy1(upwind, j);

100:           diffdw = energy1(downwind, j) - energy1(donor, j);

101:           wind = 1.0;

102:           if (diffdw <= 0.0) wind = -1.0;

103:           if (diffuw * diffdw > 0.0) {

104:             limiter = (1.0 - sigmam) * wind *

105:                       std::fmin(std::fmin(std::fabs(diffuw), std::fabs(diffdw)),

106:                                 one_by_six * (sigma3 * std::fabs(diffuw) + sigma4 * std::fabs(diffdw)));

107:           } else {

108:             limiter = 0.0;

109:           }

110:           ener_flux(i, j) = mass_flux_x(i, j) * (energy1(donor, j) + limiter);

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 46 - 69

--------------------------------------------------------------------------------

46:   T &operator[](size_t i) const { return data[i]; }

[...]

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x22fcb0 PUSH	%RBP

0x22fcb1 MOV	%RSP,%RBP

0x22fcb4 PUSH	%R15

0x22fcb6 PUSH	%R14

0x22fcb8 PUSH	%R13

0x22fcba PUSH	%R12

0x22fcbc PUSH	%RBX

0x22fcbd AND	$-0x20,%RSP

0x22fcc1 SUB	$0x320,%RSP

0x22fcc8 MOV	(%RCX),%EBX

0x22fcca MOV	(%RDX),%EAX

0x22fccc INC	%EAX

0x22fcce ADD	$0x2,%EBX

0x22fcd1 SUB	%EAX,%EBX

0x22fcd3 MOV	%EAX,0xc(%RSP)

0x22fcd7 JLE	230ca3

0x22fcdd MOV	(%R9),%R12D

0x22fce0 MOV	(%R8),%EAX

0x22fce3 MOV	%R9,%R14

0x22fce6 LEA	0x1(%RAX),%R15D

0x22fcea ADD	$0x4,%R12D

0x22fcee MOV	%RAX,0x18(%RSP)

0x22fcf3 CMP	%R15D,%R12D

0x22fcf6 JLE	230ca3

0x22fcfc SUB	%R15D,%R12D

0x22fcff MOV	(%RDI),%ESI

0x22fd01 MOVQ	$0,0x70(%RSP)

0x22fd0a MOVQ	$0x1,0x128(%RSP)

0x22fd16 MOVL	$0,0x34(%RSP)

0x22fd1e IMUL	%R12,%RBX

0x22fd22 DEC	%RBX

0x22fd25 MOV	%RBX,0x28(%RSP)

0x22fd2a SUB	$0x8,%RSP

0x22fd2e LEA	0x130(%RSP),%RAX

0x22fd36 LEA	0x2ac53(%RIP),%RDI

0x22fd3d LEA	0x3c(%RSP),%RCX

0x22fd42 LEA	0x78(%RSP),%R8

0x22fd47 LEA	0x30(%RSP),%R9

0x22fd4c MOV	%ESI,0x38(%RSP)

0x22fd50 MOV	$0x22,%EDX

0x22fd55 PUSH	$0x1

0x22fd57 PUSH	$0x1

0x22fd59 PUSH	%RAX

0x22fd5a CALL	259680 <@plt_start@+0x530>

0x22fd5f ADD	$0x20,%RSP

0x22fd63 MOV	0x28(%RSP),%RAX

0x22fd68 MOV	0x70(%RSP),%R13

0x22fd6d CMP	%RBX,%RAX

0x22fd70 CMOVL	%RAX,%RBX

0x22fd74 MOV	%RBX,0x28(%RSP)

0x22fd79 MOV	%RBX,0x58(%RSP)

0x22fd7e CMP	%RBX,%R13

0x22fd81 JG	230c90

0x22fd87 MOV	0x10(%RBP),%R9

0x22fd8b MOV	0x18(%RBP),%R11

0x22fd8f MOV	0x28(%RBP),%RSI

0x22fd93 MOV	0x38(%RBP),%RAX

0x22fd97 MOV	0x20(%RBP),%R10

0x22fd9b MOV	0x48(%RBP),%RDI

0x22fd9f MOV	(%R14),%R8D

0x22fda2 MOV	0x40(%RBP),%RBX

0x22fda6 MOV	%R15,0x50(%RSP)

0x22fdab MOV	%R12,0x48(%RSP)

0x22fdb0 MOV	(%R9),%RCX

0x22fdb3 MOV	0x10(%R9),%R9

0x22fdb7 MOV	0x8(%R10),%R14

0x22fdbb MOV	(%RSI),%RDX

0x22fdbe MOV	0x10(%RSI),%R10

0x22fdc2 MOV	(%RAX),%RSI

0x22fdc5 MOV	0x10(%RAX),%RAX

0x22fdc9 ADD	$0x2,%R8D

0x22fdcd MOV	%R8D,0x8(%RSP)

0x22fdd2 MOV	%RCX,0x40(%RSP)

0x22fdd7 MOV	(%R11),%RCX

0x22fdda MOV	%R9,0x68(%RSP)

0x22fddf MOV	%RAX,0x60(%RSP)

0x22fde4 MOV	(%RBX),%RAX

0x22fde7 MOV	0x10(%R11),%R11

0x22fdeb MOV	0x10(%RBX),%RBX

0x22fdef MOV	%RDX,0x38(%RSP)

0x22fdf4 MOV	%RSI,0x98(%RSP)

0x22fdfc MOV	%RCX,0x10(%RSP)

0x22fe01 MOV	%RDI,%RCX

0x22fe04 MOV	0x10(%RCX),%R9

0x22fe08 MOV	0x58(%RSP),%RCX

0x22fe0d MOV	(%RDI),%RDI

0x22fe10 MOV	%RAX,0x90(%RSP)

0x22fe18 SUB	%R13,%RCX

0x22fe1b MOV	%RDI,0x88(%RSP)

0x22fe23 INC	%RCX

0x22fe26 CMP	$0x8,%RCX

0x22fe2a JB	230cb2

0x22fe30 MOV	%RCX,0x80(%RSP)

0x22fe38 AND	$-0x8,%RCX

0x22fe3c VPBROADCASTQ	%R13,%YMM0

0x22fe42 VPBROADCASTQ	%RDX,%YMM3

0x22fe48 VPBROADCASTQ	%R12,%YMM1

0x22fe4e MOV	%RAX,%R12

0x22fe51 VPBROADCASTQ	%RSI,%YMM4

0x22fe57 VPADDQ	-0x1eb7f(%RIP),%YMM0,%YMM0

0x22fe5f VBROADCASTSD	-0x1ed08(%RIP),%YMM15

0x22fe68 VBROADCASTSD	-0x1ed1a(%RIP),%YMM16

0x22fe72 MOV	0x18(%RSP),%RAX

0x22fe77 VXORPD	%XMM14,%XMM14,%XMM14

0x22fe7c ADD	%RCX,%R13

0x22fe7f VMOVDQA	%YMM3,0x240(%RSP)

0x22fe88 VPBROADCASTQ	%R12,%YMM3

0x22fe8e VMOVDQA	%YMM4,0x220(%RSP)

0x22fe97 VPBROADCASTQ	%RDI,%YMM4

0x22fe9d VEXTRACTI128	$0x1,%YMM1,0x140(%RSP)

0x22fea8 MOV	%RCX,0x78(%RSP)

0x22fead MOV	%R13,0x20(%RSP)

0x22feb2 MOV	0xc(%RSP),%R13D

0x22feb7 VMOVDQA	%YMM3,0x200(%RSP)

0x22fec0 VBROADCASTSD	-0x1ecf9(%RIP),%YMM3

0x22fec9 VMOVDQA	%YMM4,0x1e0(%RSP)

0x22fed2 VPBROADCASTQ	-0x1edd3(%RIP),%YMM4

0x22fedb VPBROADCASTD	%R13D,%XMM2

0x22fee1 VMOVDQA	%XMM2,0x170(%RSP)

0x22feea VPBROADCASTD	%R15D,%XMM2

0x22fef0 MOV	0x40(%RSP),%R15

0x22fef5 VMOVDQA	%XMM2,0x160(%RSP)

0x22fefe VMOVAPS	%YMM3,0x1c0(%RSP)

0x22ff07 VBROADCASTSD	-0x1ee28(%RIP),%YMM3

0x22ff10 VMOVDQA	%YMM4,0x1a0(%RSP)

0x22ff19 VPBROADCASTQ	%R15,%YMM2

0x22ff1f VMOVDQA	%YMM2,0x280(%RSP)

0x22ff28 VPBROADCASTD	%R8D,%XMM2

0x22ff2e MOV	0x10(%RSP),%R8

0x22ff33 VMOVDQA	%XMM2,0x130(%RSP)

0x22ff3c VPBROADCASTD	%EAX,%XMM2

0x22ff42 VMOVDQA	%XMM2,0x150(%RSP)

0x22ff4b VMOVAPD	%YMM3,0x180(%RSP)

0x22ff54 VPBROADCASTQ	%R8,%YMM2

0x22ff5a VMOVDQA	%YMM2,0x260(%RSP)

0x22ff63 JMP	230052

0x22ff68 NOPL	(%RAX,%RAX,1)

(136) 0x22ff70 VCMPPD	$0x1,%YMM4,%YMM14,%YMM4

(136) 0x22ff75 VCMPPD	$0x1,%YMM6,%YMM14,%YMM6

(136) 0x22ff7a VPADDQ	0x180(%RSP),%YMM0,%YMM0

(136) 0x22ff83 VANDPD	%YMM4,%YMM15,%YMM4

(136) 0x22ff87 VANDPD	%YMM6,%YMM15,%YMM6

(136) 0x22ff8b VPCMPEQQ	%YMM15,%YMM4,%K2

(136) 0x22ff91 VPCMPEQQ	%YMM15,%YMM6,%K1

(136) 0x22ff97 VADDPD	%YMM8,%YMM3,%YMM3{%K2}

(136) 0x22ff9d VADDPD	%YMM7,%YMM2,%YMM2{%K1}

(136) 0x22ffa3 VMULPD	%YMM5,%YMM3,%YMM3

(136) 0x22ffa7 VMOVDQA	0x1e0(%RSP),%YMM5

(136) 0x22ffb0 VMULPD	%YMM2,%YMM12,%YMM2

(136) 0x22ffb4 VPMULLQ	%YMM21,%YMM5,%YMM4

(136) 0x22ffba VPMULLQ	%YMM22,%YMM5,%YMM5

(136) 0x22ffc0 VPADDQ	%YMM19,%YMM4,%YMM4

(136) 0x22ffc6 VPADDQ	%YMM20,%YMM5,%YMM5

(136) 0x22ffcc VMOVQ	%XMM4,%RCX

(136) 0x22ffd1 VPEXTRQ	$0x1,%XMM4,%RAX

(136) 0x22ffd7 VEXTRACTI128	$0x1,%YMM4,%XMM4

(136) 0x22ffdd VMOVQ	%XMM5,%RDI

(136) 0x22ffe2 VPEXTRQ	$0x1,%XMM5,%R8

(136) 0x22ffe8 VMOVLPD	%XMM2,(%R9,%RCX,8)

(136) 0x22ffee MOV	0x120(%RSP),%RCX

(136) 0x22fff6 VMOVHPD	%XMM2,(%R9,%RAX,8)

(136) 0x22fffc VEXTRACTF128	$0x1,%YMM2,%XMM2

(136) 0x230002 VMOVQ	%XMM4,%RDX

(136) 0x230007 VPEXTRQ	$0x1,%XMM4,%RSI

(136) 0x23000d VEXTRACTI128	$0x1,%YMM5,%XMM4

(136) 0x230013 VMOVQ	%XMM4,%R15

(136) 0x230018 VPEXTRQ	$0x1,%XMM4,%R12

(136) 0x23001e VMOVLPD	%XMM2,(%R9,%RDX,8)

(136) 0x230024 VMOVHPD	%XMM2,(%R9,%RSI,8)

(136) 0x23002a VEXTRACTF128	$0x1,%YMM3,%XMM2

(136) 0x230030 VMOVLPD	%XMM3,(%R9,%RDI,8)

(136) 0x230036 VMOVHPD	%XMM3,(%R9,%R8,8)

(136) 0x23003c VMOVLPD	%XMM2,(%R9,%R15,8)

(136) 0x230042 VMOVHPD	%XMM2,(%R9,%R12,8)

(136) 0x230048 ADD	$-0x8,%RCX

(136) 0x23004c JE	230c6d

(136) 0x230052 VMOVDQA	0x140(%RSP),%XMM5

(136) 0x23005b VEXTRACTI128	$0x1,%YMM0,%XMM3

(136) 0x230061 MOV	%RCX,0x120(%RSP)

(136) 0x230069 VPADDQ	0x1c0(%RSP),%YMM0,%YMM2

(136) 0x230072 VPEXTRQ	$0x1,%XMM1,%R8

(136) 0x230078 VPEXTRQ	$0x1,%XMM3,%RAX

(136) 0x23007e CQTO

(136) 0x230080 VPEXTRQ	$0x1,%XMM5,%RCX

(136) 0x230086 VMOVQ	%XMM5,%RSI

(136) 0x23008b IDIV	%RCX

(136) 0x23008e VMOVQ	%RAX,%XMM4

(136) 0x230093 VMOVQ	%XMM3,%RAX

(136) 0x230098 CQTO

(136) 0x23009a IDIV	%RSI

(136) 0x23009d VMOVQ	%RAX,%XMM3

(136) 0x2300a2 VPEXTRQ	$0x1,%XMM0,%RAX

(136) 0x2300a8 CQTO

(136) 0x2300aa VPUNPCKLQDQ	%XMM4,%XMM3,%XMM3

(136) 0x2300ae IDIV	%R8

(136) 0x2300b1 VMOVQ	%XMM1,%R8

(136) 0x2300b6 VMOVQ	%RAX,%XMM4

(136) 0x2300bb VMOVQ	%XMM0,%RAX

(136) 0x2300c0 CQTO

(136) 0x2300c2 IDIV	%R8

(136) 0x2300c5 VMOVQ	%RAX,%XMM5

(136) 0x2300ca VPUNPCKLQDQ	%XMM4,%XMM5,%XMM4

(136) 0x2300ce VEXTRACTI128	$0x1,%YMM2,%XMM5

(136) 0x2300d4 VPEXTRQ	$0x1,%XMM5,%RAX

(136) 0x2300da VINSERTI128	$0x1,%XMM3,%YMM4,%YMM3

(136) 0x2300e0 CQTO

(136) 0x2300e2 IDIV	%RCX

(136) 0x2300e5 VPEXTRQ	$0x1,%XMM1,%RCX

(136) 0x2300eb VMOVQ	%RAX,%XMM4

(136) 0x2300f0 VMOVQ	%XMM5,%RAX

(136) 0x2300f5 CQTO

(136) 0x2300f7 IDIV	%RSI

(136) 0x2300fa VMOVQ	%RAX,%XMM5

(136) 0x2300ff VPEXTRQ	$0x1,%XMM2,%RAX

(136) 0x230105 CQTO

(136) 0x230107 VPUNPCKLQDQ	%XMM4,%XMM5,%XMM4

(136) 0x23010b IDIV	%RCX

(136) 0x23010e VMOVQ	%XMM1,%RCX

(136) 0x230113 MOV	%RAX,%RSI

(136) 0x230116 VMOVQ	%XMM2,%RAX

(136) 0x23011b VMOVQ	%RSI,%XMM5

(136) 0x230120 CQTO

(136) 0x230122 IDIV	%RCX

(136) 0x230125 VMOVDQA	0x170(%RSP),%XMM8

(136) 0x23012e MOV	0x68(%RSP),%RDI

(136) 0x230133 VMOVQ	%RAX,%XMM6

(136) 0x230138 VPUNPCKLQDQ	%XMM5,%XMM6,%XMM5

(136) 0x23013c VPMOVQD	%YMM3,%XMM6

(136) 0x230142 VPMULLQ	%YMM1,%YMM3,%YMM3

(136) 0x230148 VINSERTI128	$0x1,%XMM4,%YMM5,%YMM4

(136) 0x23014e VPMOVQD	%YMM4,%XMM5

(136) 0x230154 VPMULLQ	%YMM1,%YMM4,%YMM4

(136) 0x23015a VPSUBQ	%YMM3,%YMM0,%YMM3

(136) 0x23015e VPADDD	%XMM6,%XMM8,%XMM6

(136) 0x230162 VPSUBQ	%YMM4,%YMM2,%YMM2

(136) 0x230166 VPMOVQD	%YMM3,%XMM4

(136) 0x23016c VPMOVSXDQ	%XMM6,%YMM21

(136) 0x230172 VMOVDQA	0x160(%RSP),%XMM3

(136) 0x23017b VMOVDQA	0x280(%RSP),%YMM6

(136) 0x230184 VPMOVQD	%YMM2,%XMM7

(136) 0x23018a VPADDD	%XMM5,%XMM8,%XMM5

(136) 0x23018e VPMOVSXDQ	%XMM5,%YMM22

(136) 0x230194 VPADDD	%XMM4,%XMM3,%XMM2

(136) 0x230198 VPMULLQ	%YMM21,%YMM6,%YMM5

(136) 0x23019e VPADDD	%XMM7,%XMM3,%XMM3

(136) 0x2301a2 VPMULLQ	%YMM22,%YMM6,%YMM6

(136) 0x2301a8 VPMOVSXDQ	%XMM2,%YMM19

(136) 0x2301ae VPMOVSXDQ	%XMM3,%YMM20

(136) 0x2301b4 VPADDQ	%YMM19,%YMM5,%YMM5

(136) 0x2301ba VPADDQ	%YMM20,%YMM6,%YMM6

(136) 0x2301c0 VMOVQ	%XMM5,%RAX

(136) 0x2301c5 VPEXTRQ	$0x1,%XMM5,%RCX

(136) 0x2301cb VEXTRACTI128	$0x1,%YMM5,%XMM5

(136) 0x2301d1 VMOVQ	%XMM6,%R8

(136) 0x2301d6 VPEXTRQ	$0x1,%XMM6,%R15

(136) 0x2301dc VMOVQ	%XMM5,%RDX

(136) 0x2301e1 VPEXTRQ	$0x1,%XMM5,%RSI

(136) 0x2301e7 VEXTRACTI128	$0x1,%YMM6,%XMM5

(136) 0x2301ed VMOVSD	(%RDI,%RAX,8),%XMM6

(136) 0x2301f2 VPEXTRQ	$0x1,%XMM5,%R12

(136) 0x2301f8 VMOVQ	%XMM5,%R13

(136) 0x2301fd VMOVSD	(%RDI,%RDX,8),%XMM5

(136) 0x230202 VMOVHPD	(%RDI,%RCX,8),%XMM6,%XMM6

(136) 0x230207 VMOVHPD	(%RDI,%RSI,8),%XMM5,%XMM5

(136) 0x23020c VINSERTF128	$0x1,%XMM5,%YMM6,%YMM12

(136) 0x230212 VMOVSD	(%RDI,%R13,8),%XMM5

(136) 0x230218 VMOVSD	(%RDI,%R8,8),%XMM6

(136) 0x23021e VMOVHPD	(%RDI,%R12,8),%XMM5,%XMM5

(136) 0x230224 VMOVHPD	(%RDI,%R15,8),%XMM6,%XMM6

(136) 0x23022a VCMPPD	$0x1,%YMM12,%YMM14,%K0

(136) 0x230231 VINSERTF128	$0x1,%XMM5,%YMM6,%YMM5

(136) 0x230237 VMOVDQA	0x150(%RSP),%XMM6

(136) 0x230240 VCMPPD	$0x1,%YMM5,%YMM14,%K1

(136) 0x230247 KSHIFTLB	$0x4,%K1,%K1

(136) 0x23024d KORB	%K1,%K0,%K0

(136) 0x230251 KORTESTB	%K0,%K0

(136) 0x230255 VPADDD	%XMM4,%XMM6,%XMM4

(136) 0x230259 VPADDD	%XMM7,%XMM6,%XMM6

(136) 0x23025d JB	230299

(136) 0x23025f VMOVDQA	0x130(%RSP),%XMM9

(136) 0x230268 VPCMPEQD	%XMM8,%XMM8,%XMM8

(136) 0x23026d VPMOVSXDQ	%XMM4,%YMM23

(136) 0x230273 VPMOVSXDQ	%XMM6,%YMM24

(136) 0x230279 VPSUBD	%XMM8,%XMM2,%XMM7

(136) 0x23027e VPSUBD	%XMM8,%XMM3,%XMM8

(136) 0x230283 VPMINSD	%XMM7,%XMM9,%XMM7

(136) 0x230288 VPMINSD	%XMM8,%XMM9,%XMM8

(136) 0x23028d VPMOVSXDQ	%XMM7,%YMM26

(136) 0x230293 VPMOVSXDQ	%XMM8,%YMM25

(136) 0x230299 VCMPPD	$0x1,%YMM5,%YMM14,%YMM8

(136) 0x23029e VCMPPD	$0x1,%YMM12,%YMM14,%YMM7

(136) 0x2302a4 VANDPD	%YMM15,%YMM8,%YMM8

(136) 0x2302a9 VANDPD	%YMM7,%YMM15,%YMM7

(136) 0x2302ad VPCMPEQQ	%YMM15,%YMM8,%K2

(136) 0x2302b3 VPCMPEQQ	%YMM15,%YMM7,%K1

(136) 0x2302b9 KSHIFTLB	$0x4,%K2,%K0

(136) 0x2302bf KORB	%K0,%K1,%K0

(136) 0x2302c3 KORTESTB	%K0,%K0

(136) 0x2302c7 JE	2302ee

(136) 0x2302c9 VPBROADCASTD	-0x2d6be(%RIP),%XMM7

(136) 0x2302d2 VPMOVSXDQ	%XMM6,%YMM8

(136) 0x2302d7 VPADDD	%XMM7,%XMM2,%XMM2

(136) 0x2302db VPADDD	%XMM7,%XMM3,%XMM3

(136) 0x2302df VPMOVSXDQ	%XMM4,%YMM7

(136) 0x2302e4 VPMOVSXDQ	%XMM2,%YMM9

(136) 0x2302e9 VPMOVSXDQ	%XMM3,%YMM10

(136) 0x2302ee VMOVDQA	0x260(%RSP),%YMM6

(136) 0x2302f7 VPBLENDMQ	%YMM7,%YMM19,%YMM28{%K1}

(136) 0x2302fd VPBLENDMQ	%YMM8,%YMM20,%YMM18{%K2}

(136) 0x230303 VANDPD	%YMM16,%YMM12,%YMM2

(136) 0x230309 VANDPD	%YMM16,%YMM5,%YMM3

(136) 0x23030f VPBLENDMQ	%YMM9,%YMM26,%YMM11{%K1}

(136) 0x230315 VMOVDQA64	%YMM7,%YMM26{%K1}

(136) 0x23031b VPBLENDMQ	%YMM10,%YMM25,%YMM10{%K2}

(136) 0x230321 VMOVDQA64	%YMM8,%YMM25{%K2}

(136) 0x230327 VEXTRACTI32X4	$0x1,%YMM25,%XMM8

(136) 0x23032e VMOVDQA64	%YMM19,%YMM23{%K1}

(136) 0x230334 VMOVDQA64	%YMM20,%YMM24{%K2}

(136) 0x23033a VMOVAPD	0x1a0(%RSP),%YMM30

(136) 0x230342 VMOVDQA	%YMM10,0x2c0(%RSP)

(136) 0x23034b VMOVDQA	%YMM11,0x2e0(%RSP)

(136) 0x230354 VPMULLQ	%YMM21,%YMM6,%YMM4

(136) 0x23035a VPMULLQ	%YMM22,%YMM6,%YMM6

(136) 0x230360 VPADDQ	%YMM4,%YMM28,%YMM4

(136) 0x230366 VPADDQ	%YMM6,%YMM18,%YMM6

(136) 0x23036c VMOVQ	%XMM4,%RDX

(136) 0x230371 VPEXTRQ	$0x1,%XMM4,%RSI

(136) 0x230377 VEXTRACTI128	$0x1,%YMM4,%XMM4

(136) 0x23037d VPEXTRQ	$0x1,%XMM6,%RAX

(136) 0x230383 VMOVQ	%XMM6,%RCX

(136) 0x230388 VMOVQ	%XMM4,%R15

(136) 0x23038d VPEXTRQ	$0x1,%XMM4,%R12

(136) 0x230393 VEXTRACTI128	$0x1,%YMM6,%XMM4

(136) 0x230399 VMOVSD	(%R11,%RDX,8),%XMM6

(136) 0x23039f MOV	%RDX,0x108(%RSP)

(136) 0x2303a7 MOV	%RAX,0x118(%RSP)

(136) 0x2303af MOV	%RSI,0x100(%RSP)

(136) 0x2303b7 MOV	%RCX,0x110(%RSP)

(136) 0x2303bf VMOVQ	%XMM4,%RDI

(136) 0x2303c4 VPEXTRQ	$0x1,%XMM4,%R8

(136) 0x2303ca VMOVSD	(%R11,%R15,8),%XMM4

(136) 0x2303d0 VMOVHPD	(%R11,%RSI,8),%XMM6,%XMM6

(136) 0x2303d6 MOV	%R15,0xe8(%RSP)

(136) 0x2303de MOV	%R12,0xe0(%RSP)

(136) 0x2303e6 VMOVHPD	(%R11,%R12,8),%XMM4,%XMM4

(136) 0x2303ec MOV	%RDI,0xf8(%RSP)

(136) 0x2303f4 MOV	%R8,0xf0(%RSP)

(136) 0x2303fc VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

(136) 0x230402 VMOVSD	(%R11,%RCX,8),%XMM6

(136) 0x230408 VPEXTRQ	$0x1,%XMM19,%RCX

(136) 0x23040f VMOVHPD	(%R11,%RAX,8),%XMM6,%XMM6

(136) 0x230415 VMOVQ	%XMM19,%RAX

(136) 0x23041b VDIVPD	%YMM4,%YMM2,%YMM2

(136) 0x23041f VMOVSD	(%R11,%RDI,8),%XMM4

(136) 0x230425 VMOVSD	(%R14,%RAX,8),%XMM7

(136) 0x23042b VMOVQ	%XMM20,%RDI

(136) 0x230431 VMOVHPD	(%R11,%R8,8),%XMM4,%XMM4

(136) 0x230437 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

(136) 0x23043d VEXTRACTI32X4	$0x1,%YMM20,%XMM6

(136) 0x230444 VPEXTRQ	$0x1,%XMM6,%RAX

(136) 0x23044a VDIVPD	%YMM4,%YMM3,%YMM3

(136) 0x23044e VEXTRACTI32X4	$0x1,%YMM19,%XMM4

(136) 0x230455 VMOVQ	%XMM4,%RDX

(136) 0x23045a VPEXTRQ	$0x1,%XMM4,%RSI

(136) 0x230460 VMOVSD	(%R14,%RDX,8),%XMM4

(136) 0x230466 VPEXTRQ	$0x1,%XMM20,%RDX

(136) 0x23046d VMOVHPD	(%R14,%RSI,8),%XMM4,%XMM4

(136) 0x230473 VMOVQ	%XMM6,%RSI

(136) 0x230478 VMOVHPD	(%R14,%RCX,8),%XMM7,%XMM6

(136) 0x23047e VMOVSD	(%R14,%RDI,8),%XMM7

(136) 0x230484 VPEXTRQ	$0x1,%XMM26,%RCX

(136) 0x23048b VMOVQ	%XMM25,%RDI

(136) 0x230491 VMOVHPD	(%R14,%RDX,8),%XMM7,%XMM7

(136) 0x230497 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

(136) 0x23049d VMOVSD	(%R14,%RSI,8),%XMM6

(136) 0x2304a3 VMOVHPD	(%R14,%RAX,8),%XMM6,%XMM6

(136) 0x2304a9 VMOVQ	%XMM26,%RAX

(136) 0x2304af VMOVSD	(%R14,%RAX,8),%XMM9

(136) 0x2304b5 VPEXTRQ	$0x1,%XMM8,%RAX

(136) 0x2304bb VFMADD213PD	%YMM4,%YMM2,%YMM4

(136) 0x2304c0 VINSERTF128	$0x1,%XMM6,%YMM7,%YMM6

(136) 0x2304c6 VEXTRACTI32X4	$0x1,%YMM26,%XMM7

(136) 0x2304cd VMOVQ	%XMM7,%RDX

(136) 0x2304d2 VPEXTRQ	$0x1,%XMM7,%RSI

(136) 0x2304d8 VMOVSD	(%R14,%RDX,8),%XMM7

(136) 0x2304de VPEXTRQ	$0x1,%XMM25,%RDX

(136) 0x2304e5 VFMADD213PD	%YMM6,%YMM3,%YMM6

(136) 0x2304ea VSUBPD	%YMM2,%YMM30,%YMM25

(136) 0x2304f0 VMOVHPD	(%R14,%RSI,8),%XMM7,%XMM7

(136) 0x2304f6 VMOVQ	%XMM8,%RSI

(136) 0x2304fb VMOVHPD	(%R14,%RCX,8),%XMM9,%XMM8

(136) 0x230501 VMOVSD	(%R14,%RDI,8),%XMM9

(136) 0x230507 VMOVHPD	(%R14,%RDX,8),%XMM9,%XMM9

(136) 0x23050d VINSERTF128	$0x1,%XMM7,%YMM8,%YMM7

(136) 0x230513 VMOVSD	(%R14,%RSI,8),%XMM8

(136) 0x230519 VMOVHPD	(%R14,%RAX,8),%XMM8,%XMM8

(136) 0x23051f VDIVPD	%YMM7,%YMM4,%YMM4

(136) 0x230523 VINSERTF128	$0x1,%XMM8,%YMM9,%YMM8

(136) 0x230529 VDIVPD	%YMM8,%YMM6,%YMM31

(136) 0x23052f VMOVAPD	%YMM4,0x2a0(%RSP)

(136) 0x230538 VMOVDQA	0x240(%RSP),%YMM4

(136) 0x230541 VPMULLQ	%YMM21,%YMM4,%YMM6

(136) 0x230547 VPMULLQ	%YMM22,%YMM4,%YMM7

(136) 0x23054d VPADDQ	%YMM6,%YMM11,%YMM8

(136) 0x230551 VPADDQ	%YMM7,%YMM10,%YMM9

(136) 0x230555 VPADDQ	%YMM6,%YMM28,%YMM4

(136) 0x23055b VPADDQ	%YMM6,%YMM23,%YMM6

(136) 0x230561 VPADDQ	%YMM7,%YMM18,%YMM29

(136) 0x230567 VPADDQ	%YMM7,%YMM24,%YMM7

(136) 0x23056d VEXTRACTI128	$0x1,%YMM8,%XMM10

(136) 0x230573 VMOVQ	%XMM4,%RCX

(136) 0x230578 VPEXTRQ	$0x1,%XMM4,%RDX

(136) 0x23057e VEXTRACTI128	$0x1,%YMM4,%XMM4

(136) 0x230584 VMOVQ	%XMM10,%RAX

(136) 0x230589 VMOVQ	%XMM4,%RSI

(136) 0x23058e VPEXTRQ	$0x1,%XMM4,%RDI

(136) 0x230594 VMOVSD	(%R10,%RCX,8),%XMM27

(136) 0x23059b VEXTRACTI32X4	$0x1,%YMM29,%XMM4

(136) 0x2305a2 MOV	%RCX,0xd8(%RSP)

(136) 0x2305aa MOV	%RDX,0xd0(%RSP)

(136) 0x2305b2 VMOVSD	(%R10,%RAX,8),%XMM11

(136) 0x2305b8 VPEXTRQ	$0x1,%XMM10,%RAX

(136) 0x2305be VMOVHPD	(%R10,%RDX,8),%XMM27,%XMM27

(136) 0x2305c5 VPEXTRQ	$0x1,%XMM4,%RCX

(136) 0x2305cb MOV	%RSI,0xc8(%RSP)

(136) 0x2305d3 MOV	%RDI,0xc0(%RSP)

(136) 0x2305db VMOVHPD	(%R10,%RAX,8),%XMM11,%XMM10

(136) 0x2305e1 VMOVQ	%XMM8,%RAX

(136) 0x2305e6 MOV	%RCX,0xb0(%RSP)

(136) 0x2305ee VMOVSD	(%R10,%RAX,8),%XMM11

(136) 0x2305f4 VPEXTRQ	$0x1,%XMM8,%RAX

(136) 0x2305fa VEXTRACTI128	$0x1,%YMM9,%XMM8

(136) 0x230600 VMOVHPD	(%R10,%RAX,8),%XMM11,%XMM11

(136) 0x230606 VMOVQ	%XMM8,%RAX

(136) 0x23060b VMOVSD	(%R10,%RAX,8),%XMM13

(136) 0x230611 VPEXTRQ	$0x1,%XMM8,%RAX

(136) 0x230617 VMOVHPD	(%R10,%RAX,8),%XMM13,%XMM8

(136) 0x23061d VMOVQ	%XMM9,%RAX

(136) 0x230622 VMOVSD	(%R10,%RAX,8),%XMM13

(136) 0x230628 VPEXTRQ	$0x1,%XMM9,%RAX

(136) 0x23062e VMOVHPD	(%R10,%RAX,8),%XMM13,%XMM9

(136) 0x230634 VEXTRACTI128	$0x1,%YMM6,%XMM13

(136) 0x23063a VMOVQ	%XMM13,%RAX

(136) 0x23063f VMOVSD	(%R10,%RAX,8),%XMM17

(136) 0x230646 VPEXTRQ	$0x1,%XMM13,%RAX

(136) 0x23064c VMOVHPD	(%R10,%RAX,8),%XMM17,%XMM13

(136) 0x230653 VMOVQ	%XMM6,%RAX

(136) 0x230658 VMOVSD	(%R10,%RAX,8),%XMM17

(136) 0x23065f VPEXTRQ	$0x1,%XMM6,%RAX

(136) 0x230665 VEXTRACTI128	$0x1,%YMM7,%XMM6

(136) 0x23066b VINSERTF128	$0x1,%XMM10,%YMM11,%YMM10

(136) 0x230671 VMOVHPD	(%R10,%RAX,8),%XMM17,%XMM17

(136) 0x230678 VMOVQ	%XMM6,%RAX

(136) 0x23067d VMOVSD	(%R10,%RAX,8),%XMM26

(136) 0x230684 VPEXTRQ	$0x1,%XMM6,%RAX

(136) 0x23068a VMOVHPD	(%R10,%RAX,8),%XMM26,%XMM26

(136) 0x230691 VMOVQ	%XMM7,%RAX

(136) 0x230696 VMOVSD	(%R10,%RAX,8),%XMM6

(136) 0x23069c VPEXTRQ	$0x1,%XMM7,%RAX

(136) 0x2306a2 VINSERTF128	$0x1,%XMM8,%YMM9,%YMM8

(136) 0x2306a8 VMOVHPD	(%R10,%RAX,8),%XMM6,%XMM7

(136) 0x2306ae VMOVSD	(%R10,%RSI,8),%XMM6

(136) 0x2306b4 VMOVQ	%XMM4,%RAX

(136) 0x2306b9 VMOVHPD	(%R10,%RDI,8),%XMM6,%XMM6

(136) 0x2306bf VMOVSD	(%R10,%RAX,8),%XMM4

(136) 0x2306c5 MOV	%RAX,0xb8(%RSP)

(136) 0x2306cd VMOVQ	%XMM29,%RAX

(136) 0x2306d3 MOV	%RAX,0xa8(%RSP)

(136) 0x2306db VMOVHPD	(%R10,%RCX,8),%XMM4,%XMM4

(136) 0x2306e1 VINSERTF32X4	$0x1,%XMM26,%YMM7,%YMM7

(136) 0x2306e8 VINSERTF32X4	$0x1,%XMM6,%YMM27,%YMM6

(136) 0x2306ef VMOVSD	(%R10,%RAX,8),%XMM27

(136) 0x2306f6 VPEXTRQ	$0x1,%XMM29,%RAX

(136) 0x2306fd VSUBPD	%YMM3,%YMM30,%YMM29

(136) 0x230703 VMOVAPD	0x2a0(%RSP),%YMM30

(136) 0x23070b VMOVHPD	(%R10,%RAX,8),%XMM27,%XMM27

(136) 0x230712 MOV	%RAX,0xa0(%RSP)

(136) 0x23071a VSUBPD	%YMM10,%YMM6,%YMM10

(136) 0x23071f VINSERTF32X4	$0x1,%XMM4,%YMM27,%YMM4

(136) 0x230726 VSUBPD	%YMM8,%YMM4,%YMM9

(136) 0x23072b VINSERTF32X4	$0x1,%XMM13,%YMM17,%YMM8

(136) 0x230732 VSUBPD	%YMM4,%YMM7,%YMM11

(136) 0x230736 VSUBPD	%YMM6,%YMM8,%YMM13

(136) 0x23073a VMULPD	%YMM9,%YMM11,%YMM7

(136) 0x23073f VMULPD	%YMM10,%YMM13,%YMM8

(136) 0x230744 VCMPPD	$0x1,%YMM7,%YMM14,%K1

(136) 0x23074b VCMPPD	$0x1,%YMM8,%YMM14,%K0

(136) 0x230752 KSHIFTLB	$0x4,%K1,%K1

(136) 0x230758 KORB	%K1,%K0,%K0

(136) 0x23075c KORTESTB	%K0,%K0

(136) 0x230760 JE	23080b

(136) 0x230766 VBROADCASTSD	-0x1f620(%RIP),%YMM17

(136) 0x230770 VCMPPD	$0x1,%YMM13,%YMM14,%K1

(136) 0x230777 VCMPPD	$0x1,%YMM11,%YMM14,%K2

(136) 0x23077e VSUBPD	%YMM2,%YMM17,%YMM2

(136) 0x230784 VSUBPD	%YMM3,%YMM17,%YMM3

(136) 0x23078a VBROADCASTSD	-0x1f61c(%RIP),%YMM17

(136) 0x230794 VXORPD	%YMM17,%YMM2,%YMM26

(136) 0x23079a VXORPD	%YMM17,%YMM3,%YMM27

(136) 0x2307a0 VANDPD	%YMM16,%YMM13,%YMM17

(136) 0x2307a6 VMOVAPD	%YMM2,%YMM26{%K1}

(136) 0x2307ac VMOVAPD	%YMM3,%YMM27{%K2}

(136) 0x2307b2 VANDPD	%YMM16,%YMM10,%YMM2

(136) 0x2307b8 VANDPD	%YMM16,%YMM11,%YMM10

(136) 0x2307be VANDPD	%YMM16,%YMM9,%YMM3

(136) 0x2307c4 VMINPD	%YMM3,%YMM10,%YMM13

(136) 0x2307c8 VMULPD	%YMM31,%YMM3,%YMM3

(136) 0x2307ce VMINPD	%YMM17,%YMM2,%YMM11

(136) 0x2307d4 VMULPD	%YMM30,%YMM2,%YMM2

(136) 0x2307da VFMADD231PD	%YMM10,%YMM29,%YMM3

(136) 0x2307e0 VBROADCASTSD	-0x1f601(%RIP),%YMM10

(136) 0x2307e9 VFMADD231PD	%YMM17,%YMM25,%YMM2

(136) 0x2307ef VMULPD	%YMM2,%YMM10,%YMM2

(136) 0x2307f3 VMINPD	%YMM2,%YMM11,%YMM2

(136) 0x2307f7 VMULPD	%YMM26,%YMM2,%YMM17

(136) 0x2307fd VMULPD	%YMM3,%YMM10,%YMM2

(136) 0x230801 VMINPD	%YMM2,%YMM13,%YMM2

(136) 0x230805 VMULPD	%YMM27,%YMM2,%YMM26

(136) 0x23080b VCMPPD	$0x1,%YMM7,%YMM14,%YMM3

(136) 0x230810 VCMPPD	$0x1,%YMM8,%YMM14,%YMM2

(136) 0x230816 MOV	0x60(%RSP),%RSI

(136) 0x23081b VANDPD	%YMM3,%YMM15,%YMM3

(136) 0x23081f VANDPD	%YMM2,%YMM15,%YMM2

(136) 0x230823 VPCMPEQQ	%YMM15,%YMM3,%K2

(136) 0x230829 VMOVDQA	0x220(%RSP),%YMM3

(136) 0x230832 VPCMPEQQ	%YMM15,%YMM2,%K1

(136) 0x230838 VADDPD	%YMM17,%YMM6,%YMM6{%K1}

(136) 0x23083e VADDPD	%YMM26,%YMM4,%YMM4{%K2}

(136) 0x230844 VMULPD	%YMM6,%YMM12,%YMM12

(136) 0x230848 VMULPD	%YMM5,%YMM4,%YMM5

(136) 0x23084c VPMULLQ	%YMM21,%YMM3,%YMM2

(136) 0x230852 VPMULLQ	%YMM22,%YMM3,%YMM3

(136) 0x230858 VPADDQ	%YMM19,%YMM2,%YMM2

(136) 0x23085e VPADDQ	%YMM20,%YMM3,%YMM3

(136) 0x230864 VMOVQ	%XMM2,%RCX

(136) 0x230869 VPEXTRQ	$0x1,%XMM2,%RDI

(136) 0x23086f VEXTRACTI128	$0x1,%YMM2,%XMM2

(136) 0x230875 VMOVQ	%XMM3,%R13

(136) 0x23087a VPEXTRQ	$0x1,%XMM3,%R15

(136) 0x230880 VMOVQ	%XMM2,%R8

(136) 0x230885 VPEXTRQ	$0x1,%XMM2,%R12

(136) 0x23088b VEXTRACTI128	$0x1,%YMM3,%XMM2

(136) 0x230891 VMOVLPD	%XMM12,(%RSI,%RCX,8)

(136) 0x230896 VMOVHPD	%XMM12,(%RSI,%RDI,8)

(136) 0x23089b VPEXTRQ	$0x1,%XMM2,%RAX

(136) 0x2308a1 VMOVQ	%XMM2,%RDX

(136) 0x2308a6 VEXTRACTF128	$0x1,%YMM12,%XMM2

(136) 0x2308ac VMOVLPD	%XMM2,(%RSI,%R8,8)

(136) 0x2308b2 VMOVHPD	%XMM2,(%RSI,%R12,8)

(136) 0x2308b8 VEXTRACTF128	$0x1,%YMM5,%XMM2

(136) 0x2308be VMOVLPD	%XMM5,(%RSI,%R13,8)

(136) 0x2308c4 VMOVHPD	%XMM5,(%RSI,%R15,8)

(136) 0x2308ca VMOVLPD	%XMM2,(%RSI,%RDX,8)

(136) 0x2308cf VMOVHPD	%XMM2,(%RSI,%RAX,8)

(136) 0x2308d4 VMOVDQA	0x200(%RSP),%YMM2

(136) 0x2308dd VPMULLQ	%YMM21,%YMM2,%YMM4

(136) 0x2308e3 VPMULLQ	%YMM22,%YMM2,%YMM6

(136) 0x2308e9 VPADDQ	0x2c0(%RSP),%YMM6,%YMM8

(136) 0x2308f2 VPADDQ	%YMM4,%YMM28,%YMM2

(136) 0x2308f8 VPADDQ	%YMM6,%YMM18,%YMM3

(136) 0x2308fe VPADDQ	%YMM6,%YMM24,%YMM6

(136) 0x230904 VMOVQ	%XMM2,%RAX

(136) 0x230909 VPEXTRQ	$0x1,%XMM2,%RCX

(136) 0x23090f VEXTRACTI128	$0x1,%YMM2,%XMM2

(136) 0x230915 VMOVQ	%XMM3,%R15

(136) 0x23091a VPEXTRQ	$0x1,%XMM3,%R8

(136) 0x230920 VMOVQ	%XMM2,%RDX

(136) 0x230925 VPEXTRQ	$0x1,%XMM2,%RDI

(136) 0x23092b VEXTRACTI128	$0x1,%YMM3,%XMM2

(136) 0x230931 VMOVSD	(%RBX,%RAX,8),%XMM3

(136) 0x230936 VMOVSD	(%RBX,%R15,8),%XMM7

(136) 0x23093c VMOVQ	%XMM2,%R12

(136) 0x230941 VPEXTRQ	$0x1,%XMM2,%R13

(136) 0x230947 VMOVSD	(%RBX,%RDX,8),%XMM2

(136) 0x23094c VMOVHPD	(%RBX,%RCX,8),%XMM3,%XMM3

(136) 0x230951 VMOVHPD	(%RBX,%R8,8),%XMM7,%XMM7

(136) 0x230957 VMOVHPD	(%RBX,%RDI,8),%XMM2,%XMM2

(136) 0x23095c VMOVQ	%XMM8,%R8

(136) 0x230961 VPEXTRQ	$0x1,%XMM8,%R15

(136) 0x230967 VMOVSD	(%RBX,%R8,8),%XMM9

(136) 0x23096d VPEXTRQ	$0x1,%XMM6,%R8

(136) 0x230973 VMOVHPD	(%RBX,%R15,8),%XMM9,%XMM9

(136) 0x230979 VMOVQ	%XMM6,%R15

(136) 0x23097e VINSERTF128	$0x1,%XMM2,%YMM3,%YMM2

(136) 0x230984 VMOVSD	(%RBX,%R12,8),%XMM3

(136) 0x23098a VMOVHPD	(%RBX,%R13,8),%XMM3,%XMM3

(136) 0x230990 VINSERTF128	$0x1,%XMM3,%YMM7,%YMM3

(136) 0x230996 VPADDQ	0x2e0(%RSP),%YMM4,%YMM7

(136) 0x23099f VPADDQ	%YMM4,%YMM23,%YMM4

(136) 0x2309a5 VMOVQ	%XMM7,%RAX

(136) 0x2309aa VPEXTRQ	$0x1,%XMM7,%RCX

(136) 0x2309b0 VEXTRACTI128	$0x1,%YMM7,%XMM7

(136) 0x2309b6 VMOVQ	%XMM7,%RDX

(136) 0x2309bb VPEXTRQ	$0x1,%XMM7,%RDI

(136) 0x2309c1 VEXTRACTI128	$0x1,%YMM8,%XMM7

(136) 0x2309c7 VMOVSD	(%RBX,%RAX,8),%XMM8

(136) 0x2309cc VMOVQ	%XMM4,%RAX

(136) 0x2309d1 VPEXTRQ	$0x1,%XMM7,%R12

(136) 0x2309d7 VMOVQ	%XMM7,%R13

(136) 0x2309dc VMOVSD	(%RBX,%RDX,8),%XMM7

(136) 0x2309e1 VMOVHPD	(%RBX,%RCX,8),%XMM8,%XMM8

(136) 0x2309e6 VPEXTRQ	$0x1,%XMM4,%RCX

(136) 0x2309ec VEXTRACTI128	$0x1,%YMM4,%XMM4

(136) 0x2309f2 VMOVHPD	(%RBX,%RDI,8),%XMM7,%XMM7

(136) 0x2309f7 VMOVQ	%XMM4,%RDX

(136) 0x2309fc VPEXTRQ	$0x1,%XMM4,%RDI

(136) 0x230a02 VEXTRACTI128	$0x1,%YMM6,%XMM4

(136) 0x230a08 VMOVSD	(%RBX,%RAX,8),%XMM6

(136) 0x230a0d VMOVHPD	(%RBX,%RCX,8),%XMM6,%XMM6

(136) 0x230a12 VINSERTF128	$0x1,%XMM7,%YMM8,%YMM7

(136) 0x230a18 VMOVSD	(%RBX,%R13,8),%XMM8

(136) 0x230a1e VPEXTRQ	$0x1,%XMM4,%R13

(136) 0x230a24 VMOVHPD	(%RBX,%R12,8),%XMM8,%XMM8

(136) 0x230a2a VMOVQ	%XMM4,%R12

(136) 0x230a2f VMOVSD	(%RBX,%RDX,8),%XMM4

(136) 0x230a34 VMOVHPD	(%RBX,%RDI,8),%XMM4,%XMM4

(136) 0x230a39 VSUBPD	%YMM7,%YMM2,%YMM18

(136) 0x230a3f VMOVSD	(%RBX,%R15,8),%XMM7

(136) 0x230a45 VMOVHPD	(%RBX,%R8,8),%XMM7,%XMM7

(136) 0x230a4b VINSERTF128	$0x1,%XMM8,%YMM9,%YMM8

(136) 0x230a51 VINSERTF128	$0x1,%XMM4,%YMM6,%YMM4

(136) 0x230a57 VMOVSD	(%RBX,%R12,8),%XMM6

(136) 0x230a5d VMOVHPD	(%RBX,%R13,8),%XMM6,%XMM6

(136) 0x230a63 VSUBPD	%YMM8,%YMM3,%YMM28

(136) 0x230a69 VSUBPD	%YMM2,%YMM4,%YMM23

(136) 0x230a6f VINSERTF128	$0x1,%XMM6,%YMM7,%YMM6

(136) 0x230a75 VSUBPD	%YMM3,%YMM6,%YMM24

(136) 0x230a7b VMULPD	%YMM18,%YMM23,%YMM6

(136) 0x230a81 VMULPD	%YMM28,%YMM24,%YMM4

(136) 0x230a87 VCMPPD	$0x1,%YMM6,%YMM14,%K0

(136) 0x230a8e VCMPPD	$0x1,%YMM4,%YMM14,%K1

(136) 0x230a95 KSHIFTLB	$0x4,%K1,%K1

(136) 0x230a9b KORB	%K1,%K0,%K0

(136) 0x230a9f KORTESTB	%K0,%K0

(136) 0x230aa3 JE	22ff70

(136) 0x230aa9 MOV	0xc8(%RSP),%RAX

(136) 0x230ab1 VCMPPD	$0x1,%YMM24,%YMM14,%K2

(136) 0x230ab8 VCMPPD	$0x1,%YMM23,%YMM14,%K1

(136) 0x230abf VMOVSD	(%R10,%RAX,8),%XMM7

(136) 0x230ac5 MOV	0xc0(%RSP),%RAX

(136) 0x230acd VMOVHPD	(%R10,%RAX,8),%XMM7,%XMM7

(136) 0x230ad3 MOV	0xd8(%RSP),%RAX

(136) 0x230adb VMOVSD	(%R10,%RAX,8),%XMM8

(136) 0x230ae1 MOV	0xd0(%RSP),%RAX

(136) 0x230ae9 VMOVHPD	(%R10,%RAX,8),%XMM8,%XMM8

(136) 0x230aef MOV	0xb8(%RSP),%RAX

(136) 0x230af7 VMOVSD	(%R10,%RAX,8),%XMM9

(136) 0x230afd MOV	0xb0(%RSP),%RAX

(136) 0x230b05 VINSERTF128	$0x1,%XMM7,%YMM8,%YMM7

(136) 0x230b0b VMOVHPD	(%R10,%RAX,8),%XMM9,%XMM9

(136) 0x230b11 MOV	0xa8(%RSP),%RAX

(136) 0x230b19 VMOVSD	(%R10,%RAX,8),%XMM10

(136) 0x230b1f MOV	0xa0(%RSP),%RAX

(136) 0x230b27 VMOVHPD	(%R10,%RAX,8),%XMM10,%XMM10

(136) 0x230b2d MOV	0xe8(%RSP),%RAX

(136) 0x230b35 VMOVSD	(%R11,%RAX,8),%XMM11

(136) 0x230b3b MOV	0xe0(%RSP),%RAX

(136) 0x230b43 VINSERTF128	$0x1,%XMM9,%YMM10,%YMM8

(136) 0x230b49 VANDPD	%YMM16,%YMM12,%YMM10

(136) 0x230b4f VMOVHPD	(%R11,%RAX,8),%XMM11,%XMM11

(136) 0x230b55 MOV	0x108(%RSP),%RAX

(136) 0x230b5d VMOVSD	(%R11,%RAX,8),%XMM13

(136) 0x230b63 MOV	0x100(%RSP),%RAX

(136) 0x230b6b VMOVHPD	(%R11,%RAX,8),%XMM13,%XMM13

(136) 0x230b71 MOV	0xf8(%RSP),%RAX

(136) 0x230b79 VMOVSD	(%R11,%RAX,8),%XMM17

(136) 0x230b80 MOV	0xf0(%RSP),%RAX

(136) 0x230b88 VINSERTF128	$0x1,%XMM11,%YMM13,%YMM9

(136) 0x230b8e VANDPD	%YMM16,%YMM24,%YMM13

(136) 0x230b94 VANDPD	%YMM16,%YMM23,%YMM11

(136) 0x230b9a VMOVHPD	(%R11,%RAX,8),%XMM17,%XMM17

(136) 0x230ba1 MOV	0x110(%RSP),%RAX

(136) 0x230ba9 VMULPD	%YMM7,%YMM9,%YMM7

(136) 0x230bad VANDPD	%YMM16,%YMM5,%YMM9

(136) 0x230bb3 VDIVPD	%YMM7,%YMM10,%YMM7

(136) 0x230bb7 VMOVSD	(%R11,%RAX,8),%XMM26

(136) 0x230bbe MOV	0x118(%RSP),%RAX

(136) 0x230bc6 VMOVHPD	(%R11,%RAX,8),%XMM26,%XMM26

(136) 0x230bcd VINSERTF32X4	$0x1,%XMM17,%YMM26,%YMM10

(136) 0x230bd4 VMULPD	%YMM8,%YMM10,%YMM8

(136) 0x230bd9 VDIVPD	%YMM8,%YMM9,%YMM8

(136) 0x230bde VBROADCASTSD	-0x1fa97(%RIP),%YMM9

(136) 0x230be7 VSUBPD	%YMM7,%YMM9,%YMM7

(136) 0x230beb VSUBPD	%YMM8,%YMM9,%YMM8

(136) 0x230bf0 VBROADCASTSD	-0x1fa81(%RIP),%YMM9

(136) 0x230bf9 VXORPD	%YMM7,%YMM9,%YMM10

(136) 0x230bfd VXORPD	%YMM9,%YMM8,%YMM9

(136) 0x230c02 VMOVAPD	%YMM8,%YMM9{%K2}

(136) 0x230c08 VANDPD	%YMM16,%YMM28,%YMM8

(136) 0x230c0e VMOVAPD	%YMM7,%YMM10{%K1}

(136) 0x230c14 VANDPD	%YMM16,%YMM18,%YMM7

(136) 0x230c1a VMINPD	%YMM13,%YMM8,%YMM18

(136) 0x230c20 VMULPD	%YMM31,%YMM8,%YMM8

(136) 0x230c26 VMINPD	%YMM11,%YMM7,%YMM17

(136) 0x230c2c VMULPD	%YMM30,%YMM7,%YMM7

(136) 0x230c32 VFMADD213PD	%YMM8,%YMM13,%YMM29

(136) 0x230c38 VBROADCASTSD	-0x1fa59(%RIP),%YMM8

(136) 0x230c41 VFMADD213PD	%YMM7,%YMM11,%YMM25

(136) 0x230c47 VMULPD	%YMM8,%YMM25,%YMM7

(136) 0x230c4d VMULPD	%YMM8,%YMM29,%YMM8

(136) 0x230c53 VMINPD	%YMM7,%YMM17,%YMM7

(136) 0x230c59 VMINPD	%YMM8,%YMM18,%YMM8

(136) 0x230c5f VMULPD	%YMM7,%YMM10,%YMM7

(136) 0x230c63 VMULPD	%YMM8,%YMM9,%YMM8

(136) 0x230c68 JMP	22ff70

0x230c6d MOV	0x78(%RSP),%RAX

0x230c72 MOV	0x50(%RSP),%R15

0x230c77 MOV	0x48(%RSP),%R12

0x230c7c MOV	0x20(%RSP),%R13

0x230c81 MOV	0x8(%RSP),%R8D

0x230c86 CMP	%RAX,0x80(%RSP)

0x230c8e JNE	230cb2

0x230c90 MOV	0x30(%RSP),%ESI

0x230c94 LEA	0x29d0d(%RIP),%RDI

0x230c9b VZEROUPPER

0x230c9e CALL	259690 <@plt_start@+0x540>

0x230ca3 LEA	-0x28(%RBP),%RSP

0x230ca7 POP	%RBX

0x230ca8 POP	%R12

0x230caa POP	%R13

0x230cac POP	%R14

0x230cae POP	%R15

0x230cb0 POP	%RBP

0x230cb1 RET

0x230cb2 VMOVDDUP	-0x1fb62(%RIP),%XMM1

0x230cba VMOVSD	-0x1fbba(%RIP),%XMM2

0x230cc2 VMOVSD	-0x1fb7a(%RIP),%XMM3

0x230cca VMOVDDUP	-0x1fb5a(%RIP),%XMM4

0x230cd2 VMOVDDUP	-0x1fb82(%RIP),%XMM5

0x230cda VMOVSD	-0x1fafa(%RIP),%XMM6

0x230ce2 VPXOR	%XMM0,%XMM0,%XMM0

0x230ce6 JMP	230d29

0x230ce8 NOPL	(%RAX,%RAX,1)

(135) 0x230cf0 IMUL	0x88(%RSP),%RAX

(135) 0x230cf9 VADDSD	%XMM11,%XMM10,%XMM8

(135) 0x230cfe MOV	0x20(%RSP),%RCX

(135) 0x230d03 MOV	0x50(%RSP),%R15

(135) 0x230d08 VMULSD	%XMM7,%XMM8,%XMM7

(135) 0x230d0c LEA	0x1(%RCX),%R13

(135) 0x230d10 ADD	%R12,%RAX

(135) 0x230d13 MOV	0x48(%RSP),%R12

(135) 0x230d18 VMOVSD	%XMM7,(%R9,%RAX,8)

(135) 0x230d1e CMP	%RCX,0x58(%RSP)

(135) 0x230d23 JLE	230c90

(135) 0x230d29 MOV	%R13,%RAX

(135) 0x230d2c CQTO

(135) 0x230d2e IDIV	%R12

(135) 0x230d31 MOV	0x40(%RSP),%RSI

(135) 0x230d36 MOV	0x68(%RSP),%RDI

(135) 0x230d3b MOV	%R13,0x20(%RSP)

(135) 0x230d40 LEA	(%R15,%RDX,1),%ECX

(135) 0x230d44 MOVSXD	%ECX,%R12

(135) 0x230d47 ADD	0xc(%RSP),%EAX

(135) 0x230d4b CLTQ

(135) 0x230d4d IMUL	%RAX,%RSI

(135) 0x230d51 ADD	%R12,%RSI

(135) 0x230d54 VMOVSD	(%RDI,%RSI,8),%XMM7

(135) 0x230d59 VUCOMISD	%XMM7,%XMM0

(135) 0x230d5d JAE	230d80

(135) 0x230d5f ADD	0x18(%RSP),%EDX

(135) 0x230d63 ADD	$-0x2,%ECX

(135) 0x230d66 MOVSXD	%ECX,%R15

(135) 0x230d69 MOVSXD	%EDX,%R8

(135) 0x230d6c MOV	%R12,%RDX

(135) 0x230d6f MOV	%R8,%RSI

(135) 0x230d72 JMP	230d99

0x230d74 NOPW	%CS:(%RAX,%RAX,1)

(135) 0x230d80 INC	%ECX

(135) 0x230d82 MOV	%R12,%RSI

(135) 0x230d85 CMP	%ECX,%R8D

(135) 0x230d88 CMOVL	%R8D,%ECX

(135) 0x230d8c ADD	0x18(%RSP),%EDX

(135) 0x230d90 MOVSXD	%ECX,%R15

(135) 0x230d93 MOV	%R15,%R8

(135) 0x230d96 MOVSXD	%EDX,%RDX

(135) 0x230d99 MOV	0x10(%RSP),%R13

(135) 0x230d9e VANDPD	%XMM1,%XMM7,%XMM8

(135) 0x230da2 MOV	0x38(%RSP),%RCX

(135) 0x230da7 IMUL	%RAX,%R13

(135) 0x230dab ADD	%RSI,%R13

(135) 0x230dae VDIVSD	(%R11,%R13,8),%XMM8,%XMM12

(135) 0x230db4 VMOVSD	(%R14,%R12,8),%XMM8

(135) 0x230dba VFMADD213SD	%XMM8,%XMM12,%XMM8

(135) 0x230dbf VDIVSD	(%R14,%R8,8),%XMM8,%XMM8

(135) 0x230dc5 MOV	%RCX,%R8

(135) 0x230dc8 IMUL	%RAX,%R8

(135) 0x230dcc VSUBSD	%XMM12,%XMM2,%XMM9

(135) 0x230dd1 LEA	(%RSI,%R8,1),%RCX

(135) 0x230dd5 LEA	(%R15,%R8,1),%RDI

(135) 0x230dd9 ADD	%RDX,%R8

(135) 0x230ddc VMOVSD	(%R10,%RCX,8),%XMM11

(135) 0x230de2 VMOVSD	(%R10,%R8,8),%XMM10

(135) 0x230de8 VSUBSD	(%R10,%RDI,8),%XMM11,%XMM13

(135) 0x230dee VSUBSD	%XMM11,%XMM10,%XMM14

(135) 0x230df3 VXORPD	%XMM10,%XMM10,%XMM10

(135) 0x230df8 VMULSD	%XMM13,%XMM14,%XMM15

(135) 0x230dfd VUCOMISD	%XMM10,%XMM15

(135) 0x230e02 VXORPD	%XMM15,%XMM15,%XMM15

(135) 0x230e07 JBE	230e44

(135) 0x230e09 VSUBSD	%XMM12,%XMM3,%XMM12

(135) 0x230e0e VCMPSD	$0x1,%XMM14,%XMM0,%K1

(135) 0x230e15 VXORPD	%XMM4,%XMM12,%XMM15

(135) 0x230e19 VMOVSD	%XMM12,%XMM15,%XMM15{%K1}

(135) 0x230e1f VANDPD	%XMM5,%XMM13,%XMM12

(135) 0x230e23 VANDPD	%XMM5,%XMM14,%XMM13

(135) 0x230e27 VMINSD	%XMM13,%XMM12,%XMM14

(135) 0x230e2c VMULSD	%XMM8,%XMM12,%XMM12

(135) 0x230e31 VFMADD231SD	%XMM13,%XMM9,%XMM12

(135) 0x230e36 VMULSD	%XMM6,%XMM12,%XMM12

(135) 0x230e3a VMINSD	%XMM12,%XMM14,%XMM12

(135) 0x230e3f VMULSD	%XMM15,%XMM12,%XMM15

(135) 0x230e44 MOV	0x98(%RSP),%RDI

(135) 0x230e4c VADDSD	%XMM11,%XMM15,%XMM11

(135) 0x230e51 MOV	0x60(%RSP),%R8

(135) 0x230e56 VMULSD	%XMM7,%XMM11,%XMM7

(135) 0x230e5a IMUL	%RAX,%RDI

(135) 0x230e5e ADD	%R12,%RDI

(135) 0x230e61 VMOVSD	%XMM7,(%R8,%RDI,8)

(135) 0x230e67 MOV	0x90(%RSP),%RDI

(135) 0x230e6f MOV	0x8(%RSP),%R8D

(135) 0x230e74 IMUL	%RAX,%RDI

(135) 0x230e78 ADD	%RDI,%RSI

(135) 0x230e7b ADD	%RDI,%RDX

(135) 0x230e7e ADD	%RDI,%R15

(135) 0x230e81 VMOVSD	(%RBX,%RSI,8),%XMM11

(135) 0x230e86 VMOVSD	(%RBX,%RDX,8),%XMM13

(135) 0x230e8b VSUBSD	(%RBX,%R15,8),%XMM11,%XMM12

(135) 0x230e91 VSUBSD	%XMM11,%XMM13,%XMM13

(135) 0x230e96 VMULSD	%XMM12,%XMM13,%XMM14

(135) 0x230e9b VUCOMISD	%XMM10,%XMM14

(135) 0x230ea0 JBE	230cf0

(135) 0x230ea6 VMOVSD	(%R11,%R13,8),%XMM14

(135) 0x230eac VANDPD	%XMM5,%XMM7,%XMM10

(135) 0x230eb0 VCMPSD	$0x1,%XMM13,%XMM0,%K1

(135) 0x230eb7 VMULSD	(%R10,%RCX,8),%XMM14,%XMM14

(135) 0x230ebd VDIVSD	%XMM14,%XMM10,%XMM10

(135) 0x230ec2 VSUBSD	%XMM10,%XMM3,%XMM10

(135) 0x230ec7 VXORPD	%XMM4,%XMM10,%XMM14

(135) 0x230ecb VMOVSD	%XMM10,%XMM14,%XMM14{%K1}

(135) 0x230ed1 VANDPD	%XMM5,%XMM12,%XMM10

(135) 0x230ed5 VANDPD	%XMM5,%XMM13,%XMM12

(135) 0x230ed9 VMULSD	%XMM8,%XMM10,%XMM8

(135) 0x230ede VMINSD	%XMM12,%XMM10,%XMM13

(135) 0x230ee3 VFMADD213SD	%XMM8,%XMM12,%XMM9

(135) 0x230ee8 VMULSD	%XMM6,%XMM9,%XMM8

(135) 0x230eec VMINSD	%XMM8,%XMM13,%XMM8

(135) 0x230ef1 VMULSD	%XMM8,%XMM14,%XMM10

(135) 0x230ef6 JMP	230cf0

0x230efb NOPL	(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65-110
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.75 to 8.38 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
37% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
VEXTRACTI128: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
VPBROADCASTD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
VPBROADCASTQ: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 404 bytes. The binary function is storing 536 bytes.

General properties

nb instructions	167
nb uops	179
loop length	852
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	7
used zmm registers	0
nb stack references	45

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.38 cycles
front end	22.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.00	7.00	7.00	7.00	7.00	7.00	22.75	22.75	22.75	22.75	2.00	7.00	7.00	2.00	7.00	7.00
cycles	7.00	7.00	7.00	7.00	7.00	7.00	22.75	22.75	22.75	22.75	2.00	7.00	7.00	2.00	7.00	7.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.38
Dispatch	22.75
Overall L1	22.75

Vectorization ratios

INT

all	22%
load	11%
store	34%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	23%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	22%
load	5%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	16%
load	15%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	19%
load	12%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	17%
load	13%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.75 cycles. At this rate:

6% of peak load performance is reached (17.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (23.56 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 22fcb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x320,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EAX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
JLE 230ca3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xff3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x4,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 230ca3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xff3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVQ $0,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R12,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x130(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x2ac53(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x3c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x78(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x30(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RBX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 230c90 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xfe0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R14),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R10),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8D,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RCX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R11),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RCX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %R13,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 230cb2 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x1002>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R13,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %R12,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VPBROADCASTQ %RSI,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ -0x1eb7f(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VBROADCASTSD -0x1ed08(%RIP),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x1ed1a(%RIP),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %RCX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVDQA %YMM3,0x240(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R12,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM4,0x220(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RDI,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VEXTRACTI128 $0x1,%YMM1,0x140(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0.50	0.50	3	0.50	vect (25.0%)
MOV %RCX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xc(%RSP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
VMOVDQA %YMM3,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x1ecf9(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA %YMM4,0x1e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ -0x1edd3(%RIP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTD %R13D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %XMM2,0x170(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %R15D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x40(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVDQA %XMM2,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPS %YMM3,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x1ee28(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA %YMM4,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R15,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM2,0x280(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTD %R8D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x10(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM2,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %XMM2,0x150(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %YMM3,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R8,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM2,0x260(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
JMP 230052 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x3a2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x50(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x48(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x20(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,0x80(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 230cb2 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x1002>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x29d0d(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVDDUP -0x1fb62(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x1fbba(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x1fb7a(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x1fb5a(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x1fb82(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x1fafa(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 230d29 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x1079>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	advec_cell.cpp:65-110
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65-110
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:46,69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 22.75 to 8.38 cycles (2.72x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 17% of vector register length is used (average across all SSE/AVX instructions).

Details

22% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
37% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
12% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

Workaround

Read less array elements
Write less array elements

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:65

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
VEXTRACTI128: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
VPBROADCASTD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
VPBROADCASTQ: 8 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/advec_cell.cpp:66

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 404 bytes. The binary function is storing 536 bytes.

General properties

nb instructions	167
nb uops	179
loop length	852
used x86 registers	16
used mmx registers	0
used xmm registers	8
used ymm registers	7
used zmm registers	0
nb stack references	45

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	22.38 cycles
front end	22.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	7.00	7.00	7.00	7.00	7.00	7.00	22.75	22.75	22.75	22.75	2.00	7.00	7.00	2.00	7.00	7.00
cycles	7.00	7.00	7.00	7.00	7.00	7.00	22.75	22.75	22.75	22.75	2.00	7.00	7.00	2.00	7.00	7.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	22.38
Dispatch	22.75
Overall L1	22.75

Vectorization ratios

INT

all	22%
load	11%
store	34%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	23%
load	0%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	20%

INT+FP

all	22%
load	5%
store	37%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Vector efficiency ratios

INT

all	16%
load	15%
store	20%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	19%
load	12%
store	50%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	15%

INT+FP

all	17%
load	13%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 22.75 cycles. At this rate:

6% of peak load performance is reached (17.76 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
18% of peak store performance is reached (23.56 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 22fcb0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x320,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%EBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
INC %EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD $0x2,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB %EAX,%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %EAX,0xc(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
JLE 230ca3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xff3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%R8),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1(%RAX),%R15D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x4,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 230ca3 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xff3>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %R15D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVQ $0,0x70(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0x34(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %R12,%RBX	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	N/A
DEC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LEA 0x130(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x2ac53(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x3c(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x78(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x30(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0x28(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x70(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
CMP %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%RBX	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
MOV %RBX,0x28(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RBX,0x58(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %RBX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 230c90 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0xfe0>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x20(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R14),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x40(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,0x50(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,0x48(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x8(%R10),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RSI),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD $0x2,%R8D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R8D,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV %RCX,0x40(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R11),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,0x68(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x60(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R11),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBX),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,0x38(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x98(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RCX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RDI,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x10(%RCX),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x90(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %R13,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RDI,0x88(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
INC %RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP $0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JB 230cb2 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x1002>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV %RCX,0x80(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x8,%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %R13,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %RDX,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %R12,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %RAX,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
VPBROADCASTQ %RSI,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPADDQ -0x1eb7f(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VBROADCASTSD -0x1ed08(%RIP),%YMM15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VBROADCASTSD -0x1ed1a(%RIP),%YMM16	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VXORPD %XMM14,%XMM14,%XMM14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	vect (25.0%)
ADD %RCX,%R13	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
VMOVDQA %YMM3,0x240(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R12,%YMM3	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM4,0x220(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RDI,%YMM4	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VEXTRACTI128 $0x1,%YMM1,0x140(%RSP)	2	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0.50	0.50	3	0.50	vect (25.0%)
MOV %RCX,0x78(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,0x20(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0xc(%RSP),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
VMOVDQA %YMM3,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x1ecf9(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA %YMM4,0x1e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ -0x1edd3(%RIP),%YMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTD %R13D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %XMM2,0x170(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %R15D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x40(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
VMOVDQA %XMM2,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPS %YMM3,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VBROADCASTSD -0x1ee28(%RIP),%YMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VMOVDQA %YMM4,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R15,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM2,0x280(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTD %R8D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x10(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM2,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %XMM2,0x150(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VMOVAPD %YMM3,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R8,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VMOVDQA %YMM2,0x260(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
JMP 230052 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x3a2>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x78(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x50(%RSP),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x48(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x20(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x8(%RSP),%R8D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,0x80(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
JNE 230cb2 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x1002>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x30(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x29d0d(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
VMOVDDUP -0x1fb62(%RIP),%XMM1	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x1fbba(%RIP),%XMM2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVSD -0x1fb7a(%RIP),%XMM3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x1fb5a(%RIP),%XMM4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVDDUP -0x1fb82(%RIP),%XMM5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	scal (12.5%)
VMOVSD -0x1fafa(%RIP),%XMM6	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
VPXOR %XMM0,%XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25	vect (25.0%)
JMP 230d29 <_Z17advec_cell_kerneliiiiiiRN6clover8Buffer1DIdEES2_RNS_8Buffer2DIdEES5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_S5_.omp_outlined.4+0x1079>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼advec_cell_kernel(int, int, int, int, int, int, clover::Buffer1D&, clover::Buffer1D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	3.46	1.29
○Loop 136 - advec_cell.cpp:66-110 - exec	3.46	1.29
○Loop 135 - advec_cell.cpp:66-110 - exec	0.00	0.00

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512-bits vectorization

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Complex instructions

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Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code