OV - exec - Function accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&, clover::Buffer2D<double>&) [clone .omp

	Function: accelerate_kernel(int, int, int, int, double, clover::Buffer2D<double>&, clover::Buffer2D< ...	Module: exec	Source: accelerate.cpp:40-53 [...]	Coverage (incl. loops): 5.35% \| (excl. loops): 0.00%

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp: 40 - 53

--------------------------------------------------------------------------------

40: #pragma omp parallel for simd collapse(2)

41:   for (int j = (y_min + 1); j < (y_max + 1 + 2); j++) {

42:     for (int i = (x_min + 1); i < (x_max + 1 + 2); i++) {

43:       double stepbymass_s = halfdt / ((density0(i - 1, j - 1) * volume(i - 1, j - 1) + density0(i - 1, j + 0) * volume(i - 1, j + 0) +

44:                                        density0(i, j) * volume(i, j) + density0(i + 0, j - 1) * volume(i + 0, j - 1)) *

45:                                       0.25);

46:       xvel1(i, j) = xvel0(i, j) - stepbymass_s * (xarea(i, j) * (pressure(i, j) - pressure(i - 1, j + 0)) +

47:                                                   xarea(i + 0, j - 1) * (pressure(i + 0, j - 1) - pressure(i - 1, j - 1)));

48:       yvel1(i, j) = yvel0(i, j) - stepbymass_s * (yarea(i, j) * (pressure(i, j) - pressure(i + 0, j - 1)) +

49:                                                   yarea(i - 1, j + 0) * (pressure(i - 1, j + 0) - pressure(i - 1, j - 1)));

50:       xvel1(i, j) = xvel1(i, j) - stepbymass_s * (xarea(i, j) * (viscosity(i, j) - viscosity(i - 1, j + 0)) +

51:                                                   xarea(i + 0, j - 1) * (viscosity(i + 0, j - 1) - viscosity(i - 1, j - 1)));

52:       yvel1(i, j) = yvel1(i, j) - stepbymass_s * (yarea(i, j) * (viscosity(i, j) - viscosity(i + 0, j - 1)) +

53:                                                   yarea(i - 1, j + 0) * (viscosity(i - 1, j + 0) - viscosity(i - 1, j - 1)));

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h: 69 - 69

--------------------------------------------------------------------------------

69:   T &operator()(size_t i, size_t j) const { return data[i + j * sizeX]; }

0x22d9d0 PUSH	%RBP

0x22d9d1 MOV	%RSP,%RBP

0x22d9d4 PUSH	%R15

0x22d9d6 PUSH	%R14

0x22d9d8 PUSH	%R13

0x22d9da PUSH	%R12

0x22d9dc PUSH	%RBX

0x22d9dd AND	$-0x20,%RSP

0x22d9e1 SUB	$0x260,%RSP

0x22d9e8 MOV	(%RCX),%R12D

0x22d9eb MOV	(%RDX),%EAX

0x22d9ed LEA	0x1(%RAX),%R14D

0x22d9f1 ADD	$0x3,%R12D

0x22d9f5 MOV	%RAX,0x148(%RSP)

0x22d9fd SUB	%R14D,%R12D

0x22da00 JLE	22ed57

0x22da06 MOV	(%R9),%EAX

0x22da09 MOV	(%R8),%R13D

0x22da0c LEA	0x1(%R13),%EBX

0x22da10 ADD	$0x3,%EAX

0x22da13 CMP	%EBX,%EAX

0x22da15 JLE	22ed57

0x22da1b SUB	%EBX,%EAX

0x22da1d MOV	(%RDI),%ESI

0x22da1f MOVQ	$0,0x170(%RSP)

0x22da2b MOVQ	$0x1,0x1b8(%RSP)

0x22da37 MOVL	$0,0xe4(%RSP)

0x22da42 IMUL	%RAX,%R12

0x22da46 DEC	%R12

0x22da49 MOV	%R12,0xd8(%RSP)

0x22da51 SUB	$0x8,%RSP

0x22da55 MOV	%RBX,%R15

0x22da58 MOV	%RAX,%RBX

0x22da5b LEA	0x1c0(%RSP),%RAX

0x22da63 LEA	0x2ce4e(%RIP),%RDI

0x22da6a LEA	0xec(%RSP),%RCX

0x22da72 LEA	0x178(%RSP),%R8

0x22da7a LEA	0xe0(%RSP),%R9

0x22da82 MOV	%ESI,0xe8(%RSP)

0x22da89 MOV	$0x22,%EDX

0x22da8e PUSH	$0x1

0x22da90 PUSH	$0x1

0x22da92 PUSH	%RAX

0x22da93 CALL	259680 <@plt_start@+0x530>

0x22da98 ADD	$0x20,%RSP

0x22da9c MOV	0xd8(%RSP),%RAX

0x22daa4 MOV	0x170(%RSP),%R10

0x22daac CMP	%R12,%RAX

0x22daaf CMOVL	%RAX,%R12

0x22dab3 MOV	%R12,0xd8(%RSP)

0x22dabb CMP	%R12,%R10

0x22dabe JG	22ed41

0x22dac4 MOV	0x18(%RBP),%R9

0x22dac8 MOV	%R10,0x10(%RSP)

0x22dacd MOV	0x30(%RBP),%RSI

0x22dad1 MOV	0x38(%RBP),%RDX

0x22dad5 MOV	%R15,%RAX

0x22dad8 MOV	0x50(%RBP),%RAX

0x22dadc MOV	0x58(%RBP),%R11

0x22dae0 MOV	%RBX,0x130(%RSP)

0x22dae8 MOV	0x20(%RBP),%RDI

0x22daec MOV	0x48(%RBP),%RBX

0x22daf0 MOV	%R15,0x18(%RSP)

0x22daf5 MOV	0x40(%RBP),%RCX

0x22daf9 MOV	0x28(%RBP),%R8

0x22dafd MOV	%R14,0x140(%RSP)

0x22db05 MOV	%R13,0x138(%RSP)

0x22db0d MOV	%R12,0x1a0(%RSP)

0x22db15 MOV	(%R9),%R10

0x22db18 MOV	0x10(%R9),%R9

0x22db1c MOV	0x10(%RSI),%R15

0x22db20 MOV	%R10,0xf0(%RSP)

0x22db28 MOV	(%RSI),%R10

0x22db2b MOV	0x10(%RAX),%RSI

0x22db2f MOV	%R9,0xe8(%RSP)

0x22db37 MOV	(%RDI),%R9

0x22db3a MOV	0x10(%RDI),%RDI

0x22db3e MOV	%R15,0x150(%RSP)

0x22db46 MOV	%R10,0x128(%RSP)

0x22db4e MOV	(%RDX),%R10

0x22db51 MOV	%RDI,0x168(%RSP)

0x22db59 MOV	(%RCX),%RDI

0x22db5c MOV	0x10(%RDX),%RDX

0x22db60 MOV	%R9,0x198(%RSP)

0x22db68 MOV	%RSI,0x158(%RSP)

0x22db70 MOV	%R10,0x120(%RSP)

0x22db78 MOV	(%RAX),%R10

0x22db7b MOV	0x10(%R11),%RAX

0x22db7f MOV	%RDI,0x118(%RSP)

0x22db87 MOV	0x10(%RCX),%RDI

0x22db8b MOV	(%R8),%RCX

0x22db8e MOV	0x10(%R8),%R8

0x22db92 MOV	%R10,0x110(%RSP)

0x22db9a MOV	(%R11),%R10

0x22db9d MOV	(%RBX),%R11

0x22dba0 MOV	%RAX,0x8(%RSP)

0x22dba5 MOV	0x10(%RBX),%RAX

0x22dba9 MOV	%R12,%RBX

0x22dbac MOV	%RCX,0x190(%RSP)

0x22dbb4 MOV	%R8,0x160(%RSP)

0x22dbbc MOV	%R10,0x108(%RSP)

0x22dbc4 MOV	0x60(%RBP),%R10

0x22dbc8 MOV	%R11,0x100(%RSP)

0x22dbd0 MOV	%RAX,0x30(%RSP)

0x22dbd5 MOV	0x10(%RSP),%RAX

0x22dbda MOV	(%R10),%R11

0x22dbdd SUB	%RAX,%RBX

0x22dbe0 INC	%RBX

0x22dbe3 MOV	%R11,0xf8(%RSP)

0x22dbeb MOV	0x10(%R10),%R11

0x22dbef CMP	$0x4,%RBX

0x22dbf3 JAE	22dc09

0x22dbf5 MOV	0x18(%RSP),%R10

0x22dbfa MOV	0x10(%RBP),%R9

0x22dbfe MOV	%RDX,%RBX

0x22dc01 MOV	%R8,%R15

0x22dc04 JMP	22ea67

0x22dc09 MOV	%RBX,0x180(%RSP)

0x22dc11 AND	$-0x4,%RBX

0x22dc15 VPBROADCASTQ	%RAX,%YMM0

0x22dc1b MOV	0x130(%RSP),%R8

0x22dc23 MOV	0xf0(%RSP),%RSI

0x22dc2b VPBROADCASTD	%R14D,%XMM2

0x22dc31 VBROADCASTSD	-0x1caab(%RIP),%YMM17

0x22dc3b VPADDQ	-0x1c963(%RIP),%YMM0,%YMM0

0x22dc43 VPBROADCASTQ	-0x1ca7d(%RIP),%YMM18

0x22dc4d VPBROADCASTQ	%R9,%YMM7

0x22dc53 MOV	0x8(%RSP),%R12

0x22dc58 MOV	0x10(%RBP),%R9

0x22dc5c ADD	%RBX,%RAX

0x22dc5f VMOVDQA	%XMM2,0x1f0(%RSP)

0x22dc68 MOV	%RBX,0x178(%RSP)

0x22dc70 MOV	%RAX,0x10(%RSP)

0x22dc75 MOV	0x18(%RSP),%RAX

0x22dc7a VPBROADCASTQ	%R8,%YMM1

0x22dc80 MOV	0x128(%RSP),%R8

0x22dc88 VPBROADCASTQ	%RSI,%YMM6

0x22dc8e MOV	0x120(%RSP),%RSI

0x22dc96 VEXTRACTI32X4	$0x1,%YMM1,%XMM16

0x22dc9d VPBROADCASTD	%EAX,%XMM2

0x22dca3 MOV	0x148(%RSP),%RAX

0x22dcab VMOVDQA	%XMM2,0x1e0(%RSP)

0x22dcb4 VPBROADCASTD	%R13D,%XMM2

0x22dcba MOV	0x30(%RSP),%R13

0x22dcbf VMOVDQA	%XMM2,0x1d0(%RSP)

0x22dcc8 VPBROADCASTQ	%RSI,%YMM9

0x22dcce MOV	0x110(%RSP),%RSI

0x22dcd6 VPBROADCASTD	%EAX,%XMM2

0x22dcdc VMOVDQA	%XMM2,0x1c0(%RSP)

0x22dce5 VPBROADCASTQ	%R8,%YMM2

0x22dceb MOV	0x118(%RSP),%R8

0x22dcf3 VMOVDQA	%YMM2,0x220(%RSP)

0x22dcfc VPBROADCASTQ	%RCX,%YMM2

0x22dd02 MOV	0x108(%RSP),%RCX

0x22dd0a VPBROADCASTQ	%RSI,%YMM12

0x22dd10 MOV	0x100(%RSP),%RSI

0x22dd18 VMOVDQA	%YMM2,0x200(%RSP)

0x22dd21 VPBROADCASTQ	%R8,%YMM10

0x22dd27 MOV	0xe8(%RSP),%R8

0x22dd2f VPBROADCASTQ	%RCX,%YMM13

0x22dd35 MOV	0xf8(%RSP),%RCX

0x22dd3d VPBROADCASTQ	%RSI,%YMM14

0x22dd43 VPBROADCASTQ	%RCX,%YMM15

0x22dd49 MOV	%RBX,%RCX

0x22dd4c MOV	%RDX,%RBX

0x22dd4f NOP

(128) 0x22dd50 VEXTRACTI32X4	$0x1,%YMM0,%XMM19

(128) 0x22dd57 MOV	%RCX,0x1b0(%RSP)

(128) 0x22dd5f VPEXTRQ	$0x1,%XMM16,%RCX

(128) 0x22dd66 MOV	%R8,%R14

(128) 0x22dd69 VPEXTRQ	$0x1,%XMM19,%RAX

(128) 0x22dd70 CQTO

(128) 0x22dd72 IDIV	%RCX

(128) 0x22dd75 VMOVQ	%XMM19,%RDX

(128) 0x22dd7b VMOVQ	%XMM16,%RCX

(128) 0x22dd81 VMOVQ	%RAX,%XMM19

(128) 0x22dd87 MOV	%RDX,%RAX

(128) 0x22dd8a CQTO

(128) 0x22dd8c IDIV	%RCX

(128) 0x22dd8f VPEXTRQ	$0x1,%XMM1,%RCX

(128) 0x22dd95 VMOVQ	%RAX,%XMM20

(128) 0x22dd9b VPEXTRQ	$0x1,%XMM0,%RAX

(128) 0x22dda1 CQTO

(128) 0x22dda3 VPUNPCKLQDQ	%XMM19,%XMM20,%XMM19

(128) 0x22dda9 IDIV	%RCX

(128) 0x22ddac VMOVQ	%XMM1,%RCX

(128) 0x22ddb1 MOV	%RAX,%RSI

(128) 0x22ddb4 VMOVQ	%XMM0,%RAX

(128) 0x22ddb9 VMOVQ	%RSI,%XMM20

(128) 0x22ddbf CQTO

(128) 0x22ddc1 IDIV	%RCX

(128) 0x22ddc4 MOV	0x168(%RSP),%R15

(128) 0x22ddcc VBROADCASTSD	(%R9),%YMM23

(128) 0x22ddd2 VMOVQ	%RAX,%XMM21

(128) 0x22ddd8 VPUNPCKLQDQ	%XMM20,%XMM21,%XMM20

(128) 0x22ddde VINSERTI32X4	$0x1,%XMM19,%YMM20,%YMM19

(128) 0x22dde5 VPMOVQD	%YMM19,%XMM20

(128) 0x22ddeb VPMULLQ	%YMM1,%YMM19,%YMM19

(128) 0x22ddf1 VPADDD	0x1f0(%RSP),%XMM20,%XMM21

(128) 0x22ddf9 VPADDD	0x1c0(%RSP),%XMM20,%XMM20

(128) 0x22de01 VPSUBQ	%YMM19,%YMM0,%YMM19

(128) 0x22de07 VPADDQ	%YMM18,%YMM0,%YMM0

(128) 0x22de0d VPMOVQD	%YMM19,%XMM19

(128) 0x22de13 VPADDD	0x1e0(%RSP),%XMM19,%XMM22

(128) 0x22de1b VPADDD	0x1d0(%RSP),%XMM19,%XMM19

(128) 0x22de23 VPMOVSXDQ	%XMM20,%YMM20

(128) 0x22de29 VPMOVSXDQ	%XMM21,%YMM21

(128) 0x22de2f VPMULLQ	%YMM20,%YMM6,%YMM24

(128) 0x22de35 VPMULLQ	%YMM21,%YMM6,%YMM30

(128) 0x22de3b VPMULLQ	%YMM21,%YMM7,%YMM3

(128) 0x22de41 VPMOVSXDQ	%XMM19,%YMM19

(128) 0x22de47 VPMOVSXDQ	%XMM22,%YMM22

(128) 0x22de4d VPADDQ	%YMM19,%YMM24,%YMM25

(128) 0x22de53 VPADDQ	%YMM19,%YMM30,%YMM31

(128) 0x22de59 VPADDQ	%YMM19,%YMM3,%YMM4

(128) 0x22de5f VPADDQ	%YMM22,%YMM30,%YMM30

(128) 0x22de65 VPADDQ	%YMM22,%YMM3,%YMM3

(128) 0x22de6b VPADDQ	%YMM22,%YMM24,%YMM24

(128) 0x22de71 VMOVQ	%XMM25,%RCX

(128) 0x22de77 VPEXTRQ	$0x1,%XMM25,%RDX

(128) 0x22de7e VEXTRACTI32X4	$0x1,%YMM25,%XMM25

(128) 0x22de85 VMOVQ	%XMM25,%RSI

(128) 0x22de8b VPEXTRQ	$0x1,%XMM25,%RAX

(128) 0x22de92 VPMULLQ	%YMM20,%YMM7,%YMM25

(128) 0x22de98 VMOVSD	(%R8,%RCX,8),%XMM26

(128) 0x22de9f VMOVSD	(%R8,%RSI,8),%XMM27

(128) 0x22dea6 VMOVHPD	(%R8,%RDX,8),%XMM26,%XMM26

(128) 0x22dead VPADDQ	%YMM19,%YMM25,%YMM28

(128) 0x22deb3 VMOVQ	%XMM28,%RCX

(128) 0x22deb9 VPEXTRQ	$0x1,%XMM28,%RSI

(128) 0x22dec0 VEXTRACTI32X4	$0x1,%YMM28,%XMM28

(128) 0x22dec7 VMOVQ	%XMM28,%RDX

(128) 0x22decd VPEXTRQ	$0x1,%XMM28,%R8

(128) 0x22ded4 VMOVSD	(%R15,%RCX,8),%XMM28

(128) 0x22dedb VMOVSD	(%R15,%RDX,8),%XMM29

(128) 0x22dee2 VMOVHPD	(%R15,%RSI,8),%XMM28,%XMM28

(128) 0x22dee9 VMOVQ	%XMM31,%RSI

(128) 0x22deef VPEXTRQ	$0x1,%XMM31,%RDX

(128) 0x22def6 VEXTRACTI32X4	$0x1,%YMM31,%XMM31

(128) 0x22defd VMOVSD	(%R14,%RSI,8),%XMM2

(128) 0x22df03 VMOVQ	%XMM31,%R9

(128) 0x22df09 VPEXTRQ	$0x1,%XMM31,%RCX

(128) 0x22df10 VMOVHPD	(%R14,%RAX,8),%XMM27,%XMM31

(128) 0x22df17 VMOVQ	%XMM4,%RAX

(128) 0x22df1c VPEXTRQ	$0x1,%XMM4,%RSI

(128) 0x22df22 VEXTRACTI128	$0x1,%YMM4,%XMM4

(128) 0x22df28 VMOVHPD	(%R15,%R8,8),%XMM29,%XMM29

(128) 0x22df2f VMOVHPD	(%R14,%RDX,8),%XMM2,%XMM2

(128) 0x22df35 VMOVQ	%XMM4,%RDX

(128) 0x22df3a VMOVSD	(%R15,%RAX,8),%XMM5

(128) 0x22df40 VPEXTRQ	$0x1,%XMM4,%R8

(128) 0x22df46 VMOVSD	(%R14,%R9,8),%XMM27

(128) 0x22df4d VMOVQ	%XMM30,%RAX

(128) 0x22df53 MOV	0x150(%RSP),%R9

(128) 0x22df5b VMOVSD	(%R15,%RDX,8),%XMM4

(128) 0x22df61 VMOVHPD	(%R15,%RSI,8),%XMM5,%XMM5

(128) 0x22df67 VMOVHPD	(%R14,%RCX,8),%XMM27,%XMM8

(128) 0x22df6e VPEXTRQ	$0x1,%XMM30,%RDX

(128) 0x22df75 VMOVSD	(%R14,%RAX,8),%XMM27

(128) 0x22df7c VMOVQ	%XMM3,%RAX

(128) 0x22df81 VEXTRACTI32X4	$0x1,%YMM30,%XMM30

(128) 0x22df88 VMOVHPD	(%R15,%R8,8),%XMM4,%XMM4

(128) 0x22df8e VMOVHPD	(%R14,%RDX,8),%XMM27,%XMM27

(128) 0x22df95 VPEXTRQ	$0x1,%XMM3,%RDX

(128) 0x22df9b VMOVQ	%XMM30,%RSI

(128) 0x22dfa1 VPEXTRQ	$0x1,%XMM30,%RCX

(128) 0x22dfa8 VEXTRACTI128	$0x1,%YMM3,%XMM3

(128) 0x22dfae MOV	%R14,%R8

(128) 0x22dfb1 VMOVSD	(%R14,%RSI,8),%XMM30

(128) 0x22dfb8 VPEXTRQ	$0x1,%XMM3,%RSI

(128) 0x22dfbe VMOVHPD	(%R14,%RCX,8),%XMM30,%XMM30

(128) 0x22dfc5 VMOVQ	%XMM3,%RCX

(128) 0x22dfca VMOVSD	(%R15,%RCX,8),%XMM3

(128) 0x22dfd0 VMOVQ	%XMM24,%RCX

(128) 0x22dfd6 VMOVHPD	(%R15,%RSI,8),%XMM3,%XMM3

(128) 0x22dfdc VINSERTF32X4	$0x1,%XMM31,%YMM26,%YMM31

(128) 0x22dfe3 VINSERTF32X4	$0x1,%XMM29,%YMM28,%YMM28

(128) 0x22dfea VMOVSD	(%R15,%RAX,8),%XMM26

(128) 0x22dff1 VPEXTRQ	$0x1,%XMM24,%RAX

(128) 0x22dff8 VEXTRACTI32X4	$0x1,%YMM24,%XMM24

(128) 0x22dfff VMOVHPD	(%R15,%RDX,8),%XMM26,%XMM11

(128) 0x22e006 VMOVQ	%XMM24,%RDX

(128) 0x22e00c VPEXTRQ	$0x1,%XMM24,%RSI

(128) 0x22e013 VMOVSD	(%R14,%RCX,8),%XMM24

(128) 0x22e01a VINSERTF128	$0x1,%XMM8,%YMM2,%YMM2

(128) 0x22e020 VMOVHPD	(%R14,%RAX,8),%XMM24,%XMM29

(128) 0x22e027 VPADDQ	%YMM22,%YMM25,%YMM24

(128) 0x22e02d VMOVSD	(%R14,%RDX,8),%XMM8

(128) 0x22e033 VINSERTF32X4	$0x1,%XMM4,%YMM5,%YMM26

(128) 0x22e03a VMULPD	%YMM31,%YMM28,%YMM5

(128) 0x22e040 VMOVQ	%XMM24,%RAX

(128) 0x22e046 VEXTRACTI32X4	$0x1,%YMM24,%XMM4

(128) 0x22e04d VPEXTRQ	$0x1,%XMM24,%RCX

(128) 0x22e054 VMOVHPD	(%R14,%RSI,8),%XMM8,%XMM8

(128) 0x22e05a VPMULLQ	%YMM21,%YMM10,%YMM28

(128) 0x22e060 VMOVSD	(%R15,%RAX,8),%XMM24

(128) 0x22e067 VMOVQ	%XMM4,%RDX

(128) 0x22e06c VPEXTRQ	$0x1,%XMM4,%RSI

(128) 0x22e072 VMOVSD	(%R15,%RDX,8),%XMM4

(128) 0x22e078 VINSERTF32X4	$0x1,%XMM30,%YMM27,%YMM27

(128) 0x22e07f VFMADD213PD	%YMM5,%YMM2,%YMM26

(128) 0x22e085 VPMULLQ	0x220(%RSP),%YMM21,%YMM5

(128) 0x22e08d VMOVHPD	(%R15,%RCX,8),%XMM24,%XMM2

(128) 0x22e094 VMOVHPD	(%R15,%RSI,8),%XMM4,%XMM4

(128) 0x22e09a VPADDQ	%YMM22,%YMM28,%YMM30

(128) 0x22e0a0 VPADDQ	%YMM19,%YMM28,%YMM28

(128) 0x22e0a6 MOV	0x160(%RSP),%R15

(128) 0x22e0ae VINSERTF128	$0x1,%XMM3,%YMM11,%YMM3

(128) 0x22e0b4 VINSERTF32X4	$0x1,%XMM8,%YMM29,%YMM8

(128) 0x22e0bb VFMADD213PD	%YMM26,%YMM27,%YMM3

(128) 0x22e0c1 VPMULLQ	%YMM20,%YMM9,%YMM26

(128) 0x22e0c7 VINSERTF128	$0x1,%XMM4,%YMM2,%YMM2

(128) 0x22e0cd VPADDQ	%YMM22,%YMM26,%YMM26

(128) 0x22e0d3 VEXTRACTI32X4	$0x1,%YMM26,%XMM27

(128) 0x22e0da VPADDQ	%YMM22,%YMM5,%YMM5

(128) 0x22e0e0 VFMADD213PD	%YMM3,%YMM8,%YMM2

(128) 0x22e0e5 VMOVQ	%XMM5,%RAX

(128) 0x22e0ea VPEXTRQ	$0x1,%XMM5,%RCX

(128) 0x22e0f0 VEXTRACTI128	$0x1,%YMM5,%XMM5

(128) 0x22e0f6 VMOVQ	%XMM5,%RDX

(128) 0x22e0fb VPEXTRQ	$0x1,%XMM5,%RSI

(128) 0x22e101 VMOVSD	(%R9,%RDX,8),%XMM5

(128) 0x22e107 VMOVHPD	(%R9,%RSI,8),%XMM5,%XMM24

(128) 0x22e10e VMOVSD	(%R9,%RAX,8),%XMM5

(128) 0x22e114 VMULPD	%YMM17,%YMM2,%YMM2

(128) 0x22e11a VMOVHPD	(%R9,%RCX,8),%XMM5,%XMM25

(128) 0x22e121 VPMULLQ	%YMM21,%YMM9,%YMM5

(128) 0x22e127 MOV	0x158(%RSP),%R9

(128) 0x22e12f VDIVPD	%YMM2,%YMM23,%YMM23

(128) 0x22e135 VPADDQ	%YMM22,%YMM5,%YMM5

(128) 0x22e13b VMOVQ	%XMM5,%RAX

(128) 0x22e140 VPEXTRQ	$0x1,%XMM5,%RCX

(128) 0x22e146 VEXTRACTI128	$0x1,%YMM5,%XMM5

(128) 0x22e14c VMOVQ	%XMM5,%RSI

(128) 0x22e151 VPEXTRQ	$0x1,%XMM5,%RDX

(128) 0x22e157 VMOVSD	(%RBX,%RAX,8),%XMM11

(128) 0x22e15c MOV	%RAX,0xc8(%RSP)

(128) 0x22e164 VMOVQ	%XMM30,%RAX

(128) 0x22e16a MOV	%RCX,0xc0(%RSP)

(128) 0x22e172 VMOVSD	(%RBX,%RSI,8),%XMM5

(128) 0x22e177 VMOVHPD	(%RBX,%RCX,8),%XMM11,%XMM11

(128) 0x22e17c VPEXTRQ	$0x1,%XMM30,%RCX

(128) 0x22e183 VEXTRACTI32X4	$0x1,%YMM30,%XMM30

(128) 0x22e18a VMOVSD	(%RDI,%RAX,8),%XMM4

(128) 0x22e18f MOV	%RDX,0xb8(%RSP)

(128) 0x22e197 MOV	%RSI,0xd0(%RSP)

(128) 0x22e19f MOV	%RAX,0x68(%RSP)

(128) 0x22e1a4 VPEXTRQ	$0x1,%XMM28,%RAX

(128) 0x22e1ab VMOVHPD	(%RBX,%RDX,8),%XMM5,%XMM5

(128) 0x22e1b0 VMOVQ	%XMM30,%RDX

(128) 0x22e1b6 VPEXTRQ	$0x1,%XMM30,%RSI

(128) 0x22e1bd MOV	%RCX,0x60(%RSP)

(128) 0x22e1c2 VMOVHPD	(%RDI,%RCX,8),%XMM4,%XMM4

(128) 0x22e1c7 VMOVQ	%XMM28,%RCX

(128) 0x22e1cd MOV	%RAX,0x90(%RSP)

(128) 0x22e1d5 VMOVSD	(%RDI,%RDX,8),%XMM29

(128) 0x22e1dc MOV	%RDX,0x58(%RSP)

(128) 0x22e1e1 MOV	%RSI,0x70(%RSP)

(128) 0x22e1e6 MOV	%RCX,0x88(%RSP)

(128) 0x22e1ee VMOVHPD	(%RDI,%RSI,8),%XMM29,%XMM29

(128) 0x22e1f5 VINSERTF128	$0x1,%XMM5,%YMM11,%YMM5

(128) 0x22e1fb VEXTRACTI32X4	$0x1,%YMM28,%XMM11

(128) 0x22e202 VMOVSD	(%RDI,%RCX,8),%XMM28

(128) 0x22e209 VPEXTRQ	$0x1,%XMM27,%RCX

(128) 0x22e210 VMOVQ	%XMM11,%RDX

(128) 0x22e215 VPEXTRQ	$0x1,%XMM11,%RSI

(128) 0x22e21b VMOVHPD	(%RDI,%RAX,8),%XMM28,%XMM28

(128) 0x22e222 VMOVQ	%XMM27,%RAX

(128) 0x22e228 MOV	%RCX,0xb0(%RSP)

(128) 0x22e230 VMOVSD	(%RDI,%RDX,8),%XMM11

(128) 0x22e235 VMOVSD	(%RBX,%RAX,8),%XMM27

(128) 0x22e23c MOV	%RAX,0xa0(%RSP)

(128) 0x22e244 VMOVQ	%XMM26,%RAX

(128) 0x22e24a VINSERTF32X4	$0x1,%XMM29,%YMM4,%YMM4

(128) 0x22e251 MOV	%RSI,0x78(%RSP)

(128) 0x22e256 MOV	%RDX,0x80(%RSP)

(128) 0x22e25e VMOVHPD	(%RDI,%RSI,8),%XMM11,%XMM11

(128) 0x22e263 MOV	%RAX,0xa8(%RSP)

(128) 0x22e26b VMOVHPD	(%RBX,%RCX,8),%XMM27,%XMM27

(128) 0x22e272 VINSERTF32X4	$0x1,%XMM11,%YMM28,%YMM11

(128) 0x22e279 VMOVSD	(%RBX,%RAX,8),%XMM28

(128) 0x22e280 VPEXTRQ	$0x1,%XMM26,%RAX

(128) 0x22e287 VMOVHPD	(%RBX,%RAX,8),%XMM28,%XMM26

(128) 0x22e28e MOV	%RAX,0x98(%RSP)

(128) 0x22e296 VSUBPD	%YMM4,%YMM11,%YMM4

(128) 0x22e29a VMULPD	%YMM5,%YMM4,%YMM4

(128) 0x22e29e VINSERTF32X4	$0x1,%XMM27,%YMM26,%YMM26

(128) 0x22e2a5 VPMULLQ	%YMM20,%YMM10,%YMM27

(128) 0x22e2ab VPMULLQ	%YMM20,%YMM15,%YMM20

(128) 0x22e2b1 VPADDQ	%YMM22,%YMM27,%YMM28

(128) 0x22e2b7 VEXTRACTI32X4	$0x1,%YMM28,%XMM29

(128) 0x22e2be VMOVQ	%XMM28,%RAX

(128) 0x22e2c4 VPEXTRQ	$0x1,%XMM28,%RDX

(128) 0x22e2cb VPMULLQ	%YMM21,%YMM13,%YMM28

(128) 0x22e2d1 VMOVQ	%XMM29,%RSI

(128) 0x22e2d7 VMOVSD	(%RDI,%RAX,8),%XMM5

(128) 0x22e2dc VPEXTRQ	$0x1,%XMM29,%R14

(128) 0x22e2e3 VMOVSD	(%RDI,%RSI,8),%XMM11

(128) 0x22e2e8 VMOVHPD	(%RDI,%RDX,8),%XMM5,%XMM5

(128) 0x22e2ed VMOVHPD	(%RDI,%R14,8),%XMM11,%XMM11

(128) 0x22e2f3 VPADDQ	%YMM22,%YMM28,%YMM29

(128) 0x22e2f9 VEXTRACTI32X4	$0x1,%YMM29,%XMM30

(128) 0x22e300 VINSERTF128	$0x1,%XMM11,%YMM5,%YMM3

(128) 0x22e306 VPADDQ	%YMM19,%YMM27,%YMM5

(128) 0x22e30c VEXTRACTI128	$0x1,%YMM5,%XMM8

(128) 0x22e312 VMOVQ	%XMM8,%RCX

(128) 0x22e317 MOV	%RCX,0x50(%RSP)

(128) 0x22e31c VMOVSD	(%RDI,%RCX,8),%XMM11

(128) 0x22e321 VPEXTRQ	$0x1,%XMM8,%RCX

(128) 0x22e327 MOV	%RCX,0x38(%RSP)

(128) 0x22e32c VMOVHPD	(%RDI,%RCX,8),%XMM11,%XMM8

(128) 0x22e331 VMOVQ	%XMM5,%RCX

(128) 0x22e336 MOV	%RCX,0x40(%RSP)

(128) 0x22e33b VMOVSD	(%RDI,%RCX,8),%XMM11

(128) 0x22e340 VPEXTRQ	$0x1,%XMM5,%RCX

(128) 0x22e346 VMOVHPD	(%RDI,%RCX,8),%XMM11,%XMM2

(128) 0x22e34b MOV	%RCX,0x48(%RSP)

(128) 0x22e350 VINSERTF128	$0x1,%XMM8,%YMM2,%YMM2

(128) 0x22e356 VSUBPD	%YMM3,%YMM2,%YMM2

(128) 0x22e35a VINSERTF32X4	$0x1,%XMM24,%YMM25,%YMM3

(128) 0x22e361 VFMADD213PD	%YMM4,%YMM26,%YMM2

(128) 0x22e367 VFMADD213PD	%YMM3,%YMM23,%YMM2

(128) 0x22e36d VPMULLQ	0x200(%RSP),%YMM21,%YMM3

(128) 0x22e375 VPADDQ	%YMM22,%YMM3,%YMM3

(128) 0x22e37b VMOVQ	%XMM3,%RCX

(128) 0x22e380 VEXTRACTI128	$0x1,%YMM3,%XMM4

(128) 0x22e386 MOV	%RCX,(%RSP)

(128) 0x22e38a VMOVLPD	%XMM2,(%R15,%RCX,8)

(128) 0x22e390 VPEXTRQ	$0x1,%XMM3,%RCX

(128) 0x22e396 VPMULLQ	%YMM21,%YMM12,%YMM3

(128) 0x22e39c VMOVHPD	%XMM2,(%R15,%RCX,8)

(128) 0x22e3a2 VEXTRACTF128	$0x1,%YMM2,%XMM2

(128) 0x22e3a8 MOV	%RCX,%R10

(128) 0x22e3ab VMOVQ	%XMM4,%RCX

(128) 0x22e3b0 MOV	%RCX,0x28(%RSP)

(128) 0x22e3b5 VMOVLPD	%XMM2,(%R15,%RCX,8)

(128) 0x22e3bb VPEXTRQ	$0x1,%XMM4,%RCX

(128) 0x22e3c1 VPADDQ	%YMM22,%YMM3,%YMM3

(128) 0x22e3c7 VMOVHPD	%XMM2,(%R15,%RCX,8)

(128) 0x22e3cd VEXTRACTI128	$0x1,%YMM3,%XMM2

(128) 0x22e3d3 MOV	%RCX,0x20(%RSP)

(128) 0x22e3d8 VMOVSD	(%RDI,%RAX,8),%XMM11

(128) 0x22e3dd MOV	0x80(%RSP),%RAX

(128) 0x22e3e5 VMOVQ	%XMM2,%RCX

(128) 0x22e3ea VMOVSD	(%RDI,%RSI,8),%XMM8

(128) 0x22e3ef VMOVSD	(%R9,%RCX,8),%XMM4

(128) 0x22e3f5 VPEXTRQ	$0x1,%XMM2,%RCX

(128) 0x22e3fb VMOVHPD	(%RDI,%R14,8),%XMM8,%XMM8

(128) 0x22e401 VMOVHPD	(%RDI,%RDX,8),%XMM11,%XMM11

(128) 0x22e406 VMOVHPD	(%R9,%RCX,8),%XMM4,%XMM2

(128) 0x22e40c VMOVQ	%XMM3,%RCX

(128) 0x22e411 VMOVSD	(%R9,%RCX,8),%XMM4

(128) 0x22e417 MOV	0x58(%RSP),%RCX

(128) 0x22e41c VMOVSD	(%RDI,%RAX,8),%XMM24

(128) 0x22e423 MOV	0x78(%RSP),%RAX

(128) 0x22e428 VMOVSD	(%RDI,%RCX,8),%XMM5

(128) 0x22e42d VPEXTRQ	$0x1,%XMM3,%RCX

(128) 0x22e433 VMOVHPD	(%R9,%RCX,8),%XMM4,%XMM3

(128) 0x22e439 MOV	0x70(%RSP),%RCX

(128) 0x22e43e VINSERTF128	$0x1,%XMM8,%YMM11,%YMM8

(128) 0x22e444 VMOVHPD	(%RDI,%RAX,8),%XMM24,%XMM24

(128) 0x22e44b MOV	0x88(%RSP),%RAX

(128) 0x22e453 VMOVHPD	(%RDI,%RCX,8),%XMM5,%XMM4

(128) 0x22e458 MOV	0x68(%RSP),%RCX

(128) 0x22e45d VMOVSD	(%RDI,%RAX,8),%XMM25

(128) 0x22e464 MOV	0x50(%RSP),%RAX

(128) 0x22e469 VINSERTF128	$0x1,%XMM2,%YMM3,%YMM2

(128) 0x22e46f VMOVSD	(%RDI,%RCX,8),%XMM5

(128) 0x22e474 MOV	0x60(%RSP),%RCX

(128) 0x22e479 VMOVSD	(%RDI,%RAX,8),%XMM26

(128) 0x22e480 MOV	0x90(%RSP),%RAX

(128) 0x22e488 VMOVHPD	(%RDI,%RCX,8),%XMM5,%XMM5

(128) 0x22e48d VMOVHPD	(%RDI,%RAX,8),%XMM25,%XMM25

(128) 0x22e494 MOV	0x38(%RSP),%RAX

(128) 0x22e499 VMOVHPD	(%RDI,%RAX,8),%XMM26,%XMM26

(128) 0x22e4a0 MOV	0x40(%RSP),%RAX

(128) 0x22e4a5 VINSERTF128	$0x1,%XMM4,%YMM5,%YMM4

(128) 0x22e4ab VPADDQ	%YMM19,%YMM28,%YMM5

(128) 0x22e4b1 VEXTRACTI32X4	$0x1,%YMM5,%XMM28

(128) 0x22e4b8 VSUBPD	%YMM4,%YMM8,%YMM4

(128) 0x22e4bc VINSERTF32X4	$0x1,%XMM24,%YMM25,%YMM8

(128) 0x22e4c3 VMOVSD	(%RDI,%RAX,8),%XMM27

(128) 0x22e4ca MOV	0x48(%RSP),%RAX

(128) 0x22e4cf VMOVHPD	(%RDI,%RAX,8),%XMM27,%XMM27

(128) 0x22e4d6 VMOVQ	%XMM30,%RAX

(128) 0x22e4dc MOV	%RAX,0x48(%RSP)

(128) 0x22e4e1 VMOVSD	(%R12,%RAX,8),%XMM31

(128) 0x22e4e8 VPEXTRQ	$0x1,%XMM30,%RAX

(128) 0x22e4ef MOV	%RAX,0x40(%RSP)

(128) 0x22e4f4 VMOVHPD	(%R12,%RAX,8),%XMM31,%XMM30

(128) 0x22e4fb VMOVQ	%XMM29,%RAX

(128) 0x22e501 MOV	%RAX,0x38(%RSP)

(128) 0x22e506 VMOVSD	(%R12,%RAX,8),%XMM3

(128) 0x22e50c VPEXTRQ	$0x1,%XMM29,%RAX

(128) 0x22e513 VMOVHPD	(%R12,%RAX,8),%XMM3,%XMM3

(128) 0x22e519 MOV	%RAX,0x50(%RSP)

(128) 0x22e51e VMOVQ	%XMM28,%RAX

(128) 0x22e524 MOV	%RAX,0x78(%RSP)

(128) 0x22e529 VMOVSD	(%R12,%RAX,8),%XMM29

(128) 0x22e530 VPEXTRQ	$0x1,%XMM28,%RAX

(128) 0x22e537 MOV	%RAX,0x68(%RSP)

(128) 0x22e53c VMOVHPD	(%R12,%RAX,8),%XMM29,%XMM11

(128) 0x22e543 VMOVQ	%XMM5,%RAX

(128) 0x22e548 MOV	%RAX,0x70(%RSP)

(128) 0x22e54d VMOVSD	(%R12,%RAX,8),%XMM28

(128) 0x22e554 VPEXTRQ	$0x1,%XMM5,%RAX

(128) 0x22e55a VMOVHPD	(%R12,%RAX,8),%XMM28,%XMM5

(128) 0x22e561 MOV	%RAX,0x90(%RSP)

(128) 0x22e569 MOV	%R10,%R12

(128) 0x22e56c VINSERTF32X4	$0x1,%XMM30,%YMM3,%YMM3

(128) 0x22e573 VMULPD	%YMM3,%YMM4,%YMM3

(128) 0x22e577 VINSERTF32X4	$0x1,%XMM26,%YMM27,%YMM4

(128) 0x22e57e VSUBPD	%YMM8,%YMM4,%YMM4

(128) 0x22e583 VINSERTF128	$0x1,%XMM11,%YMM5,%YMM5

(128) 0x22e589 VFMADD213PD	%YMM3,%YMM5,%YMM4

(128) 0x22e58e VFMADD213PD	%YMM2,%YMM23,%YMM4

(128) 0x22e594 VPMULLQ	%YMM21,%YMM14,%YMM2

(128) 0x22e59a VPMULLQ	%YMM21,%YMM15,%YMM21

(128) 0x22e5a0 VPADDQ	%YMM22,%YMM2,%YMM2

(128) 0x22e5a6 VPADDQ	%YMM22,%YMM21,%YMM24

(128) 0x22e5ac VPADDQ	%YMM19,%YMM21,%YMM21

(128) 0x22e5b2 VPADDQ	%YMM22,%YMM20,%YMM22

(128) 0x22e5b8 VPADDQ	%YMM19,%YMM20,%YMM19

(128) 0x22e5be VMOVQ	%XMM2,%RAX

(128) 0x22e5c3 VEXTRACTI128	$0x1,%YMM2,%XMM3

(128) 0x22e5c9 VEXTRACTI32X4	$0x1,%YMM24,%XMM25

(128) 0x22e5d0 VMOVQ	%XMM24,%RSI

(128) 0x22e5d6 VPEXTRQ	$0x1,%XMM24,%R14

(128) 0x22e5dd VMOVQ	%XMM21,%RCX

(128) 0x22e5e3 VEXTRACTI32X4	$0x1,%YMM19,%XMM20

(128) 0x22e5ea MOV	%RAX,0x88(%RSP)

(128) 0x22e5f2 VMOVLPD	%XMM4,(%R13,%RAX,8)

(128) 0x22e5f9 VPEXTRQ	$0x1,%XMM2,%RAX

(128) 0x22e5ff VEXTRACTF128	$0x1,%YMM4,%XMM2

(128) 0x22e605 VMOVQ	%XMM25,%RDX

(128) 0x22e60b MOV	%RAX,0x80(%RSP)

(128) 0x22e613 VMOVHPD	%XMM4,(%R13,%RAX,8)

(128) 0x22e61a VMOVQ	%XMM3,%RAX

(128) 0x22e61f MOV	%RAX,0x60(%RSP)

(128) 0x22e624 VMOVLPD	%XMM2,(%R13,%RAX,8)

(128) 0x22e62b VPEXTRQ	$0x1,%XMM3,%RAX

(128) 0x22e631 VMOVHPD	%XMM2,(%R13,%RAX,8)

(128) 0x22e638 MOV	%RAX,0x58(%RSP)

(128) 0x22e63d MOV	0xd0(%RSP),%RAX

(128) 0x22e645 VMOVSD	(%R11,%RSI,8),%XMM26

(128) 0x22e64c VMOVHPD	(%R11,%R14,8),%XMM26,%XMM24

(128) 0x22e653 VEXTRACTI32X4	$0x1,%YMM21,%XMM26

(128) 0x22e65a VMOVSD	(%RBX,%RAX,8),%XMM2

(128) 0x22e65f MOV	0xb8(%RSP),%RAX

(128) 0x22e667 MOV	%RCX,0xb8(%RSP)

(128) 0x22e66f VMOVHPD	(%RBX,%RAX,8),%XMM2,%XMM2

(128) 0x22e674 MOV	0xc8(%RSP),%RAX

(128) 0x22e67c VMOVSD	(%RBX,%RAX,8),%XMM3

(128) 0x22e681 MOV	0xc0(%RSP),%RAX

(128) 0x22e689 VMOVHPD	(%RBX,%RAX,8),%XMM3,%XMM3

(128) 0x22e68e MOV	0xa0(%RSP),%RAX

(128) 0x22e696 VMOVSD	(%RBX,%RAX,8),%XMM4

(128) 0x22e69b MOV	0xb0(%RSP),%RAX

(128) 0x22e6a3 VINSERTF128	$0x1,%XMM2,%YMM3,%YMM2

(128) 0x22e6a9 VMOVHPD	(%RBX,%RAX,8),%XMM4,%XMM4

(128) 0x22e6ae MOV	0xa8(%RSP),%RAX

(128) 0x22e6b6 VMOVSD	(%RBX,%RAX,8),%XMM5

(128) 0x22e6bb MOV	0x98(%RSP),%RAX

(128) 0x22e6c3 VMOVHPD	(%RBX,%RAX,8),%XMM5,%XMM5

(128) 0x22e6c8 MOV	0x28(%RSP),%RAX

(128) 0x22e6cd VMOVSD	(%R15,%RAX,8),%XMM8

(128) 0x22e6d3 MOV	0x20(%RSP),%RAX

(128) 0x22e6d8 VINSERTF128	$0x1,%XMM4,%YMM5,%YMM4

(128) 0x22e6de VMOVHPD	(%R15,%RAX,8),%XMM8,%XMM8

(128) 0x22e6e4 MOV	(%RSP),%RAX

(128) 0x22e6e8 VMOVSD	(%R15,%RAX,8),%XMM11

(128) 0x22e6ee VPEXTRQ	$0x1,%XMM25,%RAX

(128) 0x22e6f5 VMOVSD	(%R11,%RDX,8),%XMM25

(128) 0x22e6fc VMOVHPD	(%R11,%RAX,8),%XMM25,%XMM25

(128) 0x22e703 MOV	%RAX,0x1a8(%RSP)

(128) 0x22e70b VMOVQ	%XMM26,%RAX

(128) 0x22e711 VMOVHPD	(%R15,%R10,8),%XMM11,%XMM11

(128) 0x22e717 VMOVQ	%XMM20,%R10

(128) 0x22e71d MOV	%RAX,0xd0(%RSP)

(128) 0x22e725 VMOVSD	(%R11,%RAX,8),%XMM27

(128) 0x22e72c VPEXTRQ	$0x1,%XMM26,%RAX

(128) 0x22e733 VEXTRACTI32X4	$0x1,%YMM22,%XMM26

(128) 0x22e73a MOV	%R10,0xa8(%RSP)

(128) 0x22e742 MOV	%RAX,0xc0(%RSP)

(128) 0x22e74a VMOVHPD	(%R11,%RAX,8),%XMM27,%XMM3

(128) 0x22e751 VPEXTRQ	$0x1,%XMM21,%RAX

(128) 0x22e758 VMOVSD	(%R11,%RCX,8),%XMM21

(128) 0x22e75f VMOVQ	%XMM26,%R13

(128) 0x22e765 VPEXTRQ	$0x1,%XMM26,%R9

(128) 0x22e76c VPEXTRQ	$0x1,%XMM22,%RCX

(128) 0x22e773 VMOVHPD	(%R11,%RAX,8),%XMM21,%XMM21

(128) 0x22e77a MOV	%RAX,0xc8(%RSP)

(128) 0x22e782 VMOVQ	%XMM22,%RAX

(128) 0x22e788 VINSERTF32X4	$0x1,%XMM25,%YMM24,%YMM24

(128) 0x22e78f VMOVSD	(%R11,%R13,8),%XMM25

(128) 0x22e796 VMOVHPD	(%R11,%R9,8),%XMM25,%XMM25

(128) 0x22e79d VINSERTF32X4	$0x1,%XMM3,%YMM21,%YMM3

(128) 0x22e7a4 VMOVSD	(%R11,%RAX,8),%XMM21

(128) 0x22e7ab VMOVHPD	(%R11,%RCX,8),%XMM21,%XMM21

(128) 0x22e7b2 VSUBPD	%YMM24,%YMM3,%YMM3

(128) 0x22e7b8 VMULPD	%YMM2,%YMM3,%YMM2

(128) 0x22e7bc VINSERTF32X4	$0x1,%XMM25,%YMM21,%YMM5

(128) 0x22e7c3 VMOVSD	(%R11,%R10,8),%XMM21

(128) 0x22e7ca VPEXTRQ	$0x1,%XMM20,%R10

(128) 0x22e7d1 MOV	%R10,0xb0(%RSP)

(128) 0x22e7d9 VMOVHPD	(%R11,%R10,8),%XMM21,%XMM20

(128) 0x22e7e0 VMOVQ	%XMM19,%R10

(128) 0x22e7e6 MOV	%R10,0xa0(%RSP)

(128) 0x22e7ee VMOVSD	(%R11,%R10,8),%XMM21

(128) 0x22e7f5 VPEXTRQ	$0x1,%XMM19,%R10

(128) 0x22e7fc VMOVHPD	(%R11,%R10,8),%XMM21,%XMM3

(128) 0x22e803 MOV	%R10,0x98(%RSP)

(128) 0x22e80b MOV	(%RSP),%R10

(128) 0x22e80f VINSERTF32X4	$0x1,%XMM20,%YMM3,%YMM3

(128) 0x22e816 VSUBPD	%YMM5,%YMM3,%YMM3

(128) 0x22e81a VINSERTF128	$0x1,%XMM8,%YMM11,%YMM5

(128) 0x22e820 VFMADD213PD	%YMM2,%YMM4,%YMM3

(128) 0x22e825 VFMADD213PD	%YMM5,%YMM23,%YMM3

(128) 0x22e82b VMOVLPD	%XMM3,(%R15,%R10,8)

(128) 0x22e831 MOV	0x28(%RSP),%R10

(128) 0x22e836 VEXTRACTF128	$0x1,%YMM3,%XMM2

(128) 0x22e83c VMOVHPD	%XMM3,(%R15,%R12,8)

(128) 0x22e842 MOV	0x48(%RSP),%R12

(128) 0x22e847 VMOVLPD	%XMM2,(%R15,%R10,8)

(128) 0x22e84d MOV	0x20(%RSP),%R10

(128) 0x22e852 VMOVHPD	%XMM2,(%R15,%R10,8)

(128) 0x22e858 MOV	0x8(%RSP),%R10

(128) 0x22e85d VMOVSD	(%R11,%RAX,8),%XMM11

(128) 0x22e863 MOV	0x78(%RSP),%RAX

(128) 0x22e868 VMOVSD	(%R11,%RDX,8),%XMM4

(128) 0x22e86e MOV	0x8(%RSP),%RDX

(128) 0x22e873 VMOVSD	(%R11,%RSI,8),%XMM5

(128) 0x22e879 VMOVSD	(%R11,%R13,8),%XMM8

(128) 0x22e87f MOV	0x30(%RSP),%R13

(128) 0x22e884 MOV	0x60(%RSP),%RSI

(128) 0x22e889 VMOVHPD	(%R11,%R9,8),%XMM8,%XMM8

(128) 0x22e88f VMOVHPD	(%R11,%RCX,8),%XMM11,%XMM11

(128) 0x22e895 VMOVHPD	(%R11,%R14,8),%XMM5,%XMM5

(128) 0x22e89b MOV	0x1b0(%RSP),%RCX

(128) 0x22e8a3 MOV	0x10(%RBP),%R9

(128) 0x22e8a7 VMOVSD	(%R10,%R12,8),%XMM2

(128) 0x22e8ad MOV	0x8(%RSP),%R10

(128) 0x22e8b2 MOV	0x40(%RSP),%R12

(128) 0x22e8b7 VMOVSD	(%R13,%RSI,8),%XMM26

(128) 0x22e8bf ADD	$-0x4,%RCX

(128) 0x22e8c3 VMOVHPD	(%R10,%R12,8),%XMM2,%XMM2

(128) 0x22e8c9 MOV	0x8(%RSP),%R10

(128) 0x22e8ce MOV	0x38(%RSP),%R12

(128) 0x22e8d3 VMOVSD	(%R10,%R12,8),%XMM3

(128) 0x22e8d9 MOV	0x8(%RSP),%R12

(128) 0x22e8de MOV	0x50(%RSP),%R10

(128) 0x22e8e3 VMOVSD	(%R12,%RAX,8),%XMM19

(128) 0x22e8ea MOV	0x68(%RSP),%RAX

(128) 0x22e8ef VMOVHPD	(%RDX,%R10,8),%XMM3,%XMM3

(128) 0x22e8f5 MOV	0x1a8(%RSP),%RDX

(128) 0x22e8fd MOV	0x58(%RSP),%R10

(128) 0x22e902 VMOVHPD	(%R12,%RAX,8),%XMM19,%XMM19

(128) 0x22e909 MOV	0x70(%RSP),%RAX

(128) 0x22e90e VMOVHPD	(%R11,%RDX,8),%XMM4,%XMM4

(128) 0x22e914 MOV	0x80(%RSP),%RDX

(128) 0x22e91c VMOVHPD	(%R13,%R10,8),%XMM26,%XMM26

(128) 0x22e924 VINSERTF128	$0x1,%XMM2,%YMM3,%YMM2

(128) 0x22e92a VMOVSD	(%R12,%RAX,8),%XMM20

(128) 0x22e931 MOV	0xd0(%RSP),%RAX

(128) 0x22e939 VINSERTF128	$0x1,%XMM4,%YMM5,%YMM3

(128) 0x22e93f VINSERTF128	$0x1,%XMM8,%YMM11,%YMM4

(128) 0x22e945 VMOVSD	(%R11,%RAX,8),%XMM21

(128) 0x22e94c MOV	0x90(%RSP),%RAX

(128) 0x22e954 VSUBPD	%YMM3,%YMM4,%YMM3

(128) 0x22e958 VMULPD	%YMM2,%YMM3,%YMM2

(128) 0x22e95c VMOVHPD	(%R12,%RAX,8),%XMM20,%XMM20

(128) 0x22e963 MOV	0xc0(%RSP),%RAX

(128) 0x22e96b VMOVHPD	(%R11,%RAX,8),%XMM21,%XMM21

(128) 0x22e972 MOV	0xb8(%RSP),%RAX

(128) 0x22e97a VINSERTF32X4	$0x1,%XMM19,%YMM20,%YMM4

(128) 0x22e981 VMOVSD	(%R11,%RAX,8),%XMM22

(128) 0x22e988 MOV	0xc8(%RSP),%RAX

(128) 0x22e990 VMOVHPD	(%R11,%RAX,8),%XMM22,%XMM22

(128) 0x22e997 MOV	0xa8(%RSP),%RAX

(128) 0x22e99f VMOVSD	(%R11,%RAX,8),%XMM24

(128) 0x22e9a6 MOV	0xa0(%RSP),%RAX

(128) 0x22e9ae VINSERTF32X4	$0x1,%XMM21,%YMM22,%YMM3

(128) 0x22e9b5 VMOVSD	(%R11,%RAX,8),%XMM25

(128) 0x22e9bc MOV	0xb0(%RSP),%RAX

(128) 0x22e9c4 VMOVHPD	(%R11,%RAX,8),%XMM24,%XMM24

(128) 0x22e9cb MOV	0x98(%RSP),%RAX

(128) 0x22e9d3 VMOVHPD	(%R11,%RAX,8),%XMM25,%XMM25

(128) 0x22e9da MOV	0x88(%RSP),%RAX

(128) 0x22e9e2 VMOVSD	(%R13,%RAX,8),%XMM27

(128) 0x22e9ea VMOVHPD	(%R13,%RDX,8),%XMM27,%XMM27

(128) 0x22e9f2 VINSERTF32X4	$0x1,%XMM24,%YMM25,%YMM5

(128) 0x22e9f9 VSUBPD	%YMM3,%YMM5,%YMM3

(128) 0x22e9fd VFMADD213PD	%YMM2,%YMM4,%YMM3

(128) 0x22ea02 VINSERTF32X4	$0x1,%XMM26,%YMM27,%YMM26

(128) 0x22ea09 VFMADD213PD	%YMM26,%YMM23,%YMM3

(128) 0x22ea0f VEXTRACTF128	$0x1,%YMM3,%XMM2

(128) 0x22ea15 VMOVLPD	%XMM3,(%R13,%RAX,8)

(128) 0x22ea1c VMOVHPD	%XMM3,(%R13,%RDX,8)

(128) 0x22ea23 VMOVLPD	%XMM2,(%R13,%RSI,8)

(128) 0x22ea2a VMOVHPD	%XMM2,(%R13,%R10,8)

(128) 0x22ea31 JNE	22dd50

0x22ea37 MOV	0x178(%RSP),%RAX

0x22ea3f MOV	0x140(%RSP),%R14

0x22ea47 MOV	0x138(%RSP),%R13

0x22ea4f MOV	0x18(%RSP),%R10

0x22ea54 CMP	%RAX,0x180(%RSP)

0x22ea5c MOV	0x10(%RSP),%RAX

0x22ea61 JE	22ed41

0x22ea67 VMOVSD	-0x1d8df(%RIP),%XMM0

0x22ea6f MOV	%RBX,0x188(%RSP)

0x22ea77 NOPW	(%RAX,%RAX,1)

(129) 0x22ea80 MOV	%RAX,0x10(%RSP)

(129) 0x22ea85 CQTO

(129) 0x22ea87 IDIVQ	0x130(%RSP)

(129) 0x22ea8f MOV	0xf0(%RSP),%R8

(129) 0x22ea97 MOV	0xe8(%RSP),%RBX

(129) 0x22ea9f VMOVSD	(%R9),%XMM1

(129) 0x22eaa4 LEA	(%R10,%RDX,1),%ECX

(129) 0x22eaa8 ADD	%R13D,%EDX

(129) 0x22eaab MOV	0x198(%RSP),%R13

(129) 0x22eab3 MOV	0x168(%RSP),%R10

(129) 0x22eabb MOV	%ECX,(%RSP)

(129) 0x22eabe MOV	%R8,%RCX

(129) 0x22eac1 MOVSXD	%EDX,%RDX

(129) 0x22eac4 MOV	%R13,%R12

(129) 0x22eac7 LEA	(%R14,%RAX,1),%ESI

(129) 0x22eacb ADD	0x148(%RSP),%EAX

(129) 0x22ead2 MOVSXD	%ESI,%RSI

(129) 0x22ead5 IMUL	%RSI,%R13

(129) 0x22ead9 CLTQ

(129) 0x22eadb IMUL	%RAX,%R12

(129) 0x22eadf IMUL	%RAX,%RCX

(129) 0x22eae3 LEA	(%R12,%RDX,1),%R14

(129) 0x22eae7 LEA	(%RCX,%RDX,1),%R9

(129) 0x22eaeb VMOVSD	(%R10,%R14,8),%XMM2

(129) 0x22eaf1 VMULSD	(%RBX,%R9,8),%XMM2,%XMM2

(129) 0x22eaf7 MOV	%R8,%R9

(129) 0x22eafa IMUL	%RSI,%R9

(129) 0x22eafe LEA	(%R13,%RDX,1),%R8

(129) 0x22eb03 VMOVSD	(%R10,%R8,8),%XMM3

(129) 0x22eb09 LEA	(%R9,%RDX,1),%R14

(129) 0x22eb0d VFMADD132SD	(%RBX,%R14,8),%XMM2,%XMM3

(129) 0x22eb13 MOVSXD	(%RSP),%R14

(129) 0x22eb17 ADD	%R14,%R13

(129) 0x22eb1a ADD	%R14,%R9

(129) 0x22eb1d ADD	%R14,%R12

(129) 0x22eb20 ADD	%R14,%RCX

(129) 0x22eb23 VMOVSD	(%R10,%R13,8),%XMM2

(129) 0x22eb29 VFMADD132SD	(%RBX,%R9,8),%XMM3,%XMM2

(129) 0x22eb2f VMOVSD	(%R10,%R12,8),%XMM3

(129) 0x22eb35 MOV	0x118(%RSP),%R10

(129) 0x22eb3d MOV	0x128(%RSP),%R9

(129) 0x22eb45 VFMADD132SD	(%RBX,%RCX,8),%XMM2,%XMM3

(129) 0x22eb4b MOV	0x120(%RSP),%RCX

(129) 0x22eb53 MOV	0x188(%RSP),%RBX

(129) 0x22eb5b MOV	%R10,%R13

(129) 0x22eb5e IMUL	%RSI,%R13

(129) 0x22eb62 IMUL	%RAX,%R10

(129) 0x22eb66 IMUL	%RSI,%R9

(129) 0x22eb6a ADD	%R14,%R9

(129) 0x22eb6d MOV	%RCX,%R8

(129) 0x22eb70 IMUL	%RSI,%R8

(129) 0x22eb74 IMUL	%RAX,%RCX

(129) 0x22eb78 ADD	%R14,%R8

(129) 0x22eb7b ADD	%R14,%RCX

(129) 0x22eb7e MOV	%R8,%R12

(129) 0x22eb81 MOV	%R8,0x28(%RSP)

(129) 0x22eb86 LEA	(%R13,%R14,1),%R8

(129) 0x22eb8b ADD	%RDX,%R13

(129) 0x22eb8e MOV	%R8,(%RSP)

(129) 0x22eb92 VMULSD	%XMM0,%XMM3,%XMM2

(129) 0x22eb96 VDIVSD	%XMM2,%XMM1,%XMM1

(129) 0x22eb9a VMOVSD	(%RDI,%R13,8),%XMM2

(129) 0x22eba0 VSUBSD	(%RDI,%R8,8),%XMM2,%XMM2

(129) 0x22eba6 MOV	0x150(%RSP),%R8

(129) 0x22ebae VMULSD	(%RBX,%R12,8),%XMM2,%XMM2

(129) 0x22ebb4 LEA	(%R10,%R14,1),%R12

(129) 0x22ebb8 ADD	%RDX,%R10

(129) 0x22ebbb VMOVSD	(%RDI,%R10,8),%XMM3

(129) 0x22ebc1 VSUBSD	(%RDI,%R12,8),%XMM3,%XMM3

(129) 0x22ebc7 VFMADD132SD	(%RBX,%RCX,8),%XMM2,%XMM3

(129) 0x22ebcd VFMADD213SD	(%R8,%R9,8),%XMM1,%XMM3

(129) 0x22ebd3 MOV	0x190(%RSP),%R9

(129) 0x22ebdb MOV	(%RSP),%R8

(129) 0x22ebdf IMUL	%RSI,%R9

(129) 0x22ebe3 ADD	%R14,%R9

(129) 0x22ebe6 VMOVSD	%XMM3,(%R15,%R9,8)

(129) 0x22ebec MOV	0x110(%RSP),%R15

(129) 0x22ebf4 VMOVSD	(%RDI,%R12,8),%XMM2

(129) 0x22ebfa VMOVSD	(%RDI,%R10,8),%XMM3

(129) 0x22ec00 VSUBSD	(%RDI,%R8,8),%XMM2,%XMM2

(129) 0x22ec06 MOV	0x108(%RSP),%R8

(129) 0x22ec0e VSUBSD	(%RDI,%R13,8),%XMM3,%XMM3

(129) 0x22ec14 MOV	0x8(%RSP),%R13

(129) 0x22ec19 IMUL	%RSI,%R15

(129) 0x22ec1d IMUL	%RSI,%R8

(129) 0x22ec21 ADD	%R14,%R15

(129) 0x22ec24 LEA	(%R8,%R14,1),%R10

(129) 0x22ec28 ADD	%RDX,%R8

(129) 0x22ec2b MOV	%R10,(%RSP)

(129) 0x22ec2f MOV	0x8(%RSP),%R10

(129) 0x22ec34 MOV	(%RSP),%R12

(129) 0x22ec38 VMULSD	(%R10,%R12,8),%XMM2,%XMM2

(129) 0x22ec3e MOV	0x158(%RSP),%R12

(129) 0x22ec46 MOV	0x30(%RSP),%R10

(129) 0x22ec4b VFMADD132SD	(%R13,%R8,8),%XMM2,%XMM3

(129) 0x22ec52 MOV	0x100(%RSP),%R13

(129) 0x22ec5a VFMADD213SD	(%R12,%R15,8),%XMM1,%XMM3

(129) 0x22ec60 MOV	0x160(%RSP),%R15

(129) 0x22ec68 IMUL	%RSI,%R13

(129) 0x22ec6c ADD	%R14,%R13

(129) 0x22ec6f VMOVSD	%XMM3,(%R10,%R13,8)

(129) 0x22ec75 MOV	0xf8(%RSP),%R10

(129) 0x22ec7d IMUL	%R10,%RSI

(129) 0x22ec81 IMUL	%R10,%RAX

(129) 0x22ec85 MOV	0x18(%RSP),%R10

(129) 0x22ec8a LEA	(%RSI,%R14,1),%R12

(129) 0x22ec8e ADD	%RDX,%RSI

(129) 0x22ec91 ADD	%RAX,%R14

(129) 0x22ec94 ADD	%RDX,%RAX

(129) 0x22ec97 MOV	0x8(%RSP),%RDX

(129) 0x22ec9c VMOVSD	(%R11,%RSI,8),%XMM2

(129) 0x22eca2 MOV	%R12,0x20(%RSP)

(129) 0x22eca7 VMOVSD	(%R11,%RAX,8),%XMM3

(129) 0x22ecad VSUBSD	(%R11,%R12,8),%XMM2,%XMM2

(129) 0x22ecb3 MOV	0x28(%RSP),%R12

(129) 0x22ecb8 VSUBSD	(%R11,%R14,8),%XMM3,%XMM3

(129) 0x22ecbe VMULSD	(%RBX,%R12,8),%XMM2,%XMM2

(129) 0x22ecc4 MOV	0x1a0(%RSP),%R12

(129) 0x22eccc VFMADD132SD	(%RBX,%RCX,8),%XMM2,%XMM3

(129) 0x22ecd2 MOV	0x20(%RSP),%RCX

(129) 0x22ecd7 VFMADD213SD	(%R15,%R9,8),%XMM1,%XMM3

(129) 0x22ecdd VMOVSD	%XMM3,(%R15,%R9,8)

(129) 0x22ece3 MOV	0x10(%RBP),%R9

(129) 0x22ece7 VMOVSD	(%R11,%R14,8),%XMM2

(129) 0x22eced VMOVSD	(%R11,%RAX,8),%XMM3

(129) 0x22ecf3 MOV	0x10(%RSP),%RAX

(129) 0x22ecf8 MOV	0x140(%RSP),%R14

(129) 0x22ed00 VSUBSD	(%R11,%RCX,8),%XMM2,%XMM2

(129) 0x22ed06 MOV	(%RSP),%RCX

(129) 0x22ed0a VSUBSD	(%R11,%RSI,8),%XMM3,%XMM3

(129) 0x22ed10 MOV	0x30(%RSP),%RSI

(129) 0x22ed15 VMULSD	(%RDX,%RCX,8),%XMM2,%XMM2

(129) 0x22ed1a VFMADD132SD	(%RDX,%R8,8),%XMM2,%XMM3

(129) 0x22ed20 VFMADD213SD	(%RSI,%R13,8),%XMM1,%XMM3

(129) 0x22ed26 VMOVSD	%XMM3,(%RSI,%R13,8)

(129) 0x22ed2c MOV	0x138(%RSP),%R13

(129) 0x22ed34 CMP	%R12,%RAX

(129) 0x22ed37 LEA	0x1(%RAX),%RAX

(129) 0x22ed3b JL	22ea80

0x22ed41 MOV	0xe0(%RSP),%ESI

0x22ed48 LEA	0x2bb81(%RIP),%RDI

0x22ed4f VZEROUPPER

0x22ed52 CALL	259690 <@plt_start@+0x540>

0x22ed57 LEA	-0x28(%RBP),%RSP

0x22ed5b POP	%RBX

0x22ed5c POP	%R12

0x22ed5e POP	%R13

0x22ed60 POP	%R14

0x22ed62 POP	%R15

0x22ed64 POP	%RBP

0x22ed65 RET

0x22ed66 NOPW	%CS:(%RAX,%RAX,1)

Coverage (%)	Name	Source Location	Module

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.00 to 9.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

12% of SSE/AVX loads are used in vector version.
15% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
7% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 27.00 to 25.63 cycles (1.05x speedup).

Workaround

Read less array elements
Write less array elements

512-bits vectorization

On some x86 processors supporting 512-bits vectorization, compilers are often too conservative and limit vectorization to 256 bits. Performance can then be improved by enforcing 512-bits vectorization, especially with many vectorized and high trip count loops. 512-bits vectorization performance overhead (compared to 256-bits) is generally lower on newer processors.

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
VPBROADCASTD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
VPBROADCASTQ: 12 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 528 bytes. The binary function is storing 392 bytes.

General properties

nb instructions	189
nb uops	205
loop length	1016
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	13
used zmm registers	0
nb stack references	51

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.63 cycles
front end	25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	27.00	27.00	27.00	27.00	0.50	9.00	9.00	0.50	3.00	3.00
cycles	6.67	6.67	6.67	6.67	6.67	6.67	27.00	27.00	27.00	27.00	0.50	9.00	9.00	0.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.63
Dispatch	27.00
Overall L1	27.00

Vectorization ratios

INT

all	12%
load	16%
store	15%
mul	0%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	11%
load	12%
store	15%
mul	0%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	14%
load	17%
store	15%
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	13%
load	16%
store	15%
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 27.00 cycles. At this rate:

7% of peak load performance is reached (19.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (14.52 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 22d9d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x260,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x3,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,0x148(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %R14D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 22ed57 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1387>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%R13),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 22ed57 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1387>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVQ $0,0x170(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0x1b8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0xe4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %RAX,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1c0(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x2ce4e(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xec(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x178(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xe0(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xd8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x170(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R12	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R12,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R12,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 22ed41 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1371>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R14,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R10,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,0x150(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x168(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,0x198(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x158(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R11),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R11),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0x190(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x60(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R10),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R10),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP $0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 22dc09 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x239>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 22ea67 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1097>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RBX,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %RAX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x130(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xf0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %R14D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VBROADCASTSD -0x1caab(%RIP),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPADDQ -0x1c963(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VPBROADCASTQ -0x1ca7d(%RIP),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R9,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x8(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQA %XMM2,0x1f0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RBX,0x178(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %R8,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x128(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x120(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VEXTRACTI32X4 $0x1,%YMM1,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x148(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM2,0x1e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %R13D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x30(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM2,0x1d0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTQ %RSI,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x110(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %XMM2,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTQ %R8,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x118(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x220(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RCX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x108(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM12	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x100(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R8,%YMM10	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0xe8(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM13	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0xf8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM14	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %RCX,%YMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x178(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x138(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,0x180(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x10(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JE 22ed41 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1371>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x1d8df(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x188(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xe0(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x2bb81(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run aocc_8

Source file and lines	accelerate.cpp:40-53
Module	exec

The function is defined in:

/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40-53
/home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/context.h:69

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 27.00 to 9.00 cycles (3.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions).

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

12% of SSE/AVX loads are used in vector version.
15% of SSE/AVX stores are used in vector version.
25% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX multiply instructions are used in vector version.
7% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Workaround

Read the "512-bits vectorization" report at "Potential" confidence level.

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 27.00 to 25.63 cycles (1.05x speedup).

Workaround

Read less array elements
Write less array elements

512-bits vectorization

Workaround

Recompile with -mprefer-vector-width=512

CALL instructions

Detected function call instructions.

Details

unknown: 2 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:40

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

CMOVL: 1 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
VPBROADCASTD: 4 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
VPBROADCASTQ: 12 occurrences►
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41
- /home/eoseret/qaas_runs_ZEN5/173-937-4090/intel/CloverLeaf2.0-CXX/build/CloverLeaf2.0-CXX/src/omp/accelerate.cpp:41

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 528 bytes. The binary function is storing 392 bytes.

General properties

nb instructions	189
nb uops	205
loop length	1016
used x86 registers	16
used mmx registers	0
used xmm registers	3
used ymm registers	13
used zmm registers	0
nb stack references	51

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	25.63 cycles
front end	25.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15
uops	6.67	6.67	6.67	6.67	6.67	6.67	27.00	27.00	27.00	27.00	0.50	9.00	9.00	0.50	3.00	3.00
cycles	6.67	6.67	6.67	6.67	6.67	6.67	27.00	27.00	27.00	27.00	0.50	9.00	9.00	0.50	3.00	3.00

Execution ports to units layout:

P0: ALU
P1: ALU
P2: ALU
P3: ALU, BRU
P4: ALU, BRU
P5: ALU, BRU
P6 (512 bits): store address, load
P7 (512 bits): store address, load
P8 (512 bits): store address, load
P9 (512 bits): store address, load
P10 (512 bits): VPU, DIV/SQRT
P11 (512 bits): VPU, DIV/SQRT
P12 (512 bits): VPU
P13 (512 bits): VPU
P14 (512 bits): FP store data
P15 (512 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	25.63
Dispatch	27.00
Overall L1	27.00

Vectorization ratios

INT

all	12%
load	16%
store	15%
mul	0%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	7%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	11%
load	12%
store	15%
mul	0%
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	7%

Vector efficiency ratios

INT

all	14%
load	17%
store	15%
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

INT+FP

all	13%
load	16%
store	15%
mul	12%
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 27.00 cycles. At this rate:

7% of peak load performance is reached (19.56 out of 256.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (14.52 out of 128.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 22d9d0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	Latency	Recip. throughput	Vectorization
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
AND $-0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB $0x260,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RCX),%R12D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (6.3%)
MOV (%RDX),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%RAX),%R14D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x3,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
MOV %RAX,0x148(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB %R14D,%R12D	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 22ed57 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1387>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV (%R9),%EAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%R13D	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x1(%R13),%EBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD $0x3,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (6.3%)
JLE 22ed57 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1387>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
SUB %EBX,%EAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV (%RDI),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOVQ $0,0x170(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVQ $0x1,0x1b8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOVL $0,0xe4(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
IMUL %RAX,%R12	1	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	0	0	3	0.33	scal (12.5%)
DEC %R12	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
MOV %R12,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
SUB $0x8,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %RBX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
LEA 0x1c0(%RSP),%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x2ce4e(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xec(%RSP),%RCX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0x178(%RSP),%R8	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LEA 0xe0(%RSP),%R9	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
MOV %ESI,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (6.3%)
MOV $0x22,%EDX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH $0x1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CALL 259680 <@plt_start@+0x530>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
ADD $0x20,%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV 0xd8(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x170(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %R12,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
CMOVL %RAX,%R12	2	0.33	0.33	0.33	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.33	scal (12.5%)
MOV %R12,0xd8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
CMP %R12,%R10	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JG 22ed41 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1371>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x30(%RBP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x38(%RBP),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV 0x50(%RBP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x58(%RBP),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RBX,0x130(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x20(%RBP),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x48(%RBP),%RBX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,0x18(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x40(%RBP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x28(%RBP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R14,0x140(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R13,0x138(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R12,0x1a0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R9),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R9),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RSI),%R15	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV %R10,0xf0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RSI),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RAX),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,0xe8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDI),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDI),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R15,0x150(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x128(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RDX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x168(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RDX),%RDX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R9,0x198(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RSI,0x158(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x120(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%RAX),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R11),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDI,0x118(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RCX),%RDI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R8),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%R8),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R10,0x110(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV (%R11),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%RBX),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RAX,0x8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RBX),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R12,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RCX,0x190(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R8,0x160(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %R10,0x108(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x60(%RBP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %R11,0x100(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x30(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV (%R10),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
SUB %RAX,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
INC %RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOV %R11,0xf8(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x10(%R10),%R11	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP $0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	scal (12.5%)
JAE 22dc09 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x239>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
MOV 0x18(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %R8,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	scal (12.5%)
JMP 22ea67 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1097>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	0	1	N/A
MOV %RBX,0x180(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
AND $-0x4,%RBX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VPBROADCASTQ %RAX,%YMM0	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x130(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0xf0(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %R14D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VBROADCASTSD -0x1caab(%RIP),%YMM17	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
VPADDQ -0x1c963(%RIP),%YMM0,%YMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0.25	0	0	1	0.50	vect (50.0%)
VPBROADCASTQ -0x1ca7d(%RIP),%YMM18	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0.50	0.50	0	0	0	1	0.50	scal (12.5%)
VPBROADCASTQ %R9,%YMM7	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x8(%RSP),%R12	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x10(%RBP),%R9	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
ADD %RBX,%RAX	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.17	N/A
VMOVDQA %XMM2,0x1f0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
MOV %RBX,0x178(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV %RAX,0x10(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
MOV 0x18(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %R8,%YMM1	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x128(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM6	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x120(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VEXTRACTI32X4 $0x1,%YMM1,%XMM16	1	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	3	0.50	vect (25.0%)
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x148(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM2,0x1e0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTD %R13D,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
MOV 0x30(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %XMM2,0x1d0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTQ %RSI,%YMM9	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x110(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTD %EAX,%XMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (6.3%)
VMOVDQA %XMM2,0x1c0(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (25.0%)
VPBROADCASTQ %R8,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x118(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x220(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %RCX,%YMM2	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x108(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM12	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0x100(%RSP),%RSI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VMOVDQA %YMM2,0x200(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0.50	0.50	4	0.50	vect (50.0%)
VPBROADCASTQ %R8,%YMM10	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0xe8(%RSP),%R8	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RCX,%YMM13	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV 0xf8(%RSP),%RCX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
VPBROADCASTQ %RSI,%YMM14	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
VPBROADCASTQ %RCX,%YMM15	2	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1	scal (12.5%)
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
MOV %RDX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17	N/A
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0x178(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x140(%RSP),%R14	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	scal (12.5%)
MOV 0x138(%RSP),%R13	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
MOV 0x18(%RSP),%R10	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
CMP %RAX,0x180(%RSP)	1	0.17	0.17	0.17	0.17	0.17	0.17	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25	N/A
MOV 0x10(%RSP),%RAX	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
JE 22ed41 <_Z17accelerate_kerneliiiidRN6clover8Buffer2DIdEES2_S2_S2_S2_S2_S2_S2_S2_S2_.omp_outlined+0x1371>	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50-1	N/A
VMOVSD -0x1d8df(%RIP),%XMM0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.50	scal (12.5%)
MOV %RBX,0x188(%RSP)	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	4	0.50	scal (12.5%)
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A
MOV 0xe0(%RSP),%ESI	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	3	0.25	N/A
LEA 0x2bb81(%RIP),%RDI	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	vect (25.0%)
CALL 259690 <@plt_start@+0x540>	2	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0.50	N/A
LEA -0x28(%RBP),%RSP	1	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	0	1	0.25	N/A
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33	N/A
RET	1	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09	N/A

Name	Coverage (%)	Time (s)
▼accelerate_kernel(int, int, int, int, double, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D&, clover::Buffer2D–	5.35	2.00
○Loop 128 - accelerate.cpp:41-53 - exec	5.35	1.99
○Loop 129 - accelerate.cpp:41-53 - exec	0.00	0.00

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512-bits vectorization

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Matching between your function (in the source code) and the binary function

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Code clean check

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Vectorization

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Execution units bottlenecks

Workaround

512-bits vectorization

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CALL instructions

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Complex instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code